1 /* 2 * QEMU Cadence GEM emulation 3 * 4 * Copyright (c) 2011 Xilinx, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include <zlib.h> /* For crc32 */ 27 28 #include "hw/irq.h" 29 #include "hw/net/cadence_gem.h" 30 #include "hw/qdev-properties.h" 31 #include "migration/vmstate.h" 32 #include "qapi/error.h" 33 #include "qemu/log.h" 34 #include "qemu/module.h" 35 #include "sysemu/dma.h" 36 #include "net/checksum.h" 37 38 #ifdef CADENCE_GEM_ERR_DEBUG 39 #define DB_PRINT(...) do { \ 40 fprintf(stderr, ": %s: ", __func__); \ 41 fprintf(stderr, ## __VA_ARGS__); \ 42 } while (0) 43 #else 44 #define DB_PRINT(...) 45 #endif 46 47 #define GEM_NWCTRL (0x00000000/4) /* Network Control reg */ 48 #define GEM_NWCFG (0x00000004/4) /* Network Config reg */ 49 #define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */ 50 #define GEM_USERIO (0x0000000C/4) /* User IO reg */ 51 #define GEM_DMACFG (0x00000010/4) /* DMA Control reg */ 52 #define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */ 53 #define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */ 54 #define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */ 55 #define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */ 56 #define GEM_ISR (0x00000024/4) /* Interrupt Status reg */ 57 #define GEM_IER (0x00000028/4) /* Interrupt Enable reg */ 58 #define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */ 59 #define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */ 60 #define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintenance reg */ 61 #define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */ 62 #define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */ 63 #define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */ 64 #define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */ 65 #define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */ 66 #define GEM_HASHHI (0x00000084/4) /* Hash High address reg */ 67 #define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */ 68 #define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */ 69 #define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */ 70 #define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */ 71 #define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */ 72 #define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */ 73 #define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */ 74 #define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */ 75 #define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */ 76 #define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */ 77 #define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */ 78 #define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */ 79 #define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */ 80 #define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */ 81 #define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */ 82 #define GEM_MODID (0x000000FC/4) /* Module ID reg */ 83 #define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */ 84 #define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */ 85 #define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */ 86 #define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */ 87 #define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */ 88 #define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */ 89 #define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */ 90 #define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */ 91 #define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */ 92 #define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */ 93 #define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */ 94 #define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */ 95 #define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */ 96 #define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */ 97 #define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */ 98 #define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */ 99 #define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */ 100 #define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */ 101 #define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */ 102 #define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */ 103 #define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */ 104 #define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */ 105 #define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */ 106 #define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */ 107 #define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */ 108 #define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */ 109 #define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */ 110 #define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */ 111 #define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */ 112 #define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */ 113 #define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */ 114 #define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */ 115 #define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */ 116 #define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */ 117 #define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */ 118 #define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */ 119 #define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */ 120 #define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */ 121 #define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */ 122 #define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */ 123 #define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */ 124 #define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */ 125 #define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */ 126 #define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */ 127 #define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */ 128 129 #define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */ 130 #define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */ 131 #define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */ 132 #define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */ 133 #define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */ 134 #define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */ 135 #define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */ 136 #define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */ 137 #define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */ 138 #define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */ 139 #define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */ 140 #define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */ 141 142 /* Design Configuration Registers */ 143 #define GEM_DESCONF (0x00000280/4) 144 #define GEM_DESCONF2 (0x00000284/4) 145 #define GEM_DESCONF3 (0x00000288/4) 146 #define GEM_DESCONF4 (0x0000028C/4) 147 #define GEM_DESCONF5 (0x00000290/4) 148 #define GEM_DESCONF6 (0x00000294/4) 149 #define GEM_DESCONF6_64B_MASK (1U << 23) 150 #define GEM_DESCONF7 (0x00000298/4) 151 152 #define GEM_INT_Q1_STATUS (0x00000400 / 4) 153 #define GEM_INT_Q1_MASK (0x00000640 / 4) 154 155 #define GEM_TRANSMIT_Q1_PTR (0x00000440 / 4) 156 #define GEM_TRANSMIT_Q7_PTR (GEM_TRANSMIT_Q1_PTR + 6) 157 158 #define GEM_RECEIVE_Q1_PTR (0x00000480 / 4) 159 #define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6) 160 161 #define GEM_TBQPH (0x000004C8 / 4) 162 #define GEM_RBQPH (0x000004D4 / 4) 163 164 #define GEM_INT_Q1_ENABLE (0x00000600 / 4) 165 #define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6) 166 167 #define GEM_INT_Q1_DISABLE (0x00000620 / 4) 168 #define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6) 169 170 #define GEM_INT_Q1_MASK (0x00000640 / 4) 171 #define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6) 172 173 #define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500 / 4) 174 175 #define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29) 176 #define GEM_ST1R_DSTC_ENABLE (1 << 28) 177 #define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12) 178 #define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1) 179 #define GEM_ST1R_DSTC_MATCH_SHIFT (4) 180 #define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1) 181 #define GEM_ST1R_QUEUE_SHIFT (0) 182 #define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1) 183 184 #define GEM_SCREENING_TYPE2_REGISTER_0 (0x00000540 / 4) 185 186 #define GEM_ST2R_COMPARE_A_ENABLE (1 << 18) 187 #define GEM_ST2R_COMPARE_A_SHIFT (13) 188 #define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1) 189 #define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12) 190 #define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9) 191 #define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \ 192 + 1) 193 #define GEM_ST2R_QUEUE_SHIFT (0) 194 #define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1) 195 196 #define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 (0x000006e0 / 4) 197 #define GEM_TYPE2_COMPARE_0_WORD_0 (0x00000700 / 4) 198 199 #define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7) 200 #define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1) 201 #define GEM_T2CW1_OFFSET_VALUE_SHIFT (0) 202 #define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1) 203 204 /*****************************************/ 205 #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ 206 #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */ 207 #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */ 208 #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */ 209 210 #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ 211 #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */ 212 #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ 213 #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ 214 #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ 215 #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ 216 #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ 217 #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ 218 219 #define GEM_DMACFG_ADDR_64B (1U << 30) 220 #define GEM_DMACFG_TX_BD_EXT (1U << 29) 221 #define GEM_DMACFG_RX_BD_EXT (1U << 28) 222 #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ 223 #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ 224 #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 225 #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ 226 227 #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 228 #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 229 230 #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 231 #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 232 233 /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 234 #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 235 #define GEM_INT_TXUSED 0x00000008 236 #define GEM_INT_RXUSED 0x00000004 237 #define GEM_INT_RXCMPL 0x00000002 238 239 #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 240 #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 241 #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 242 #define GEM_PHYMNTNC_ADDR_SHFT 23 243 #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 244 #define GEM_PHYMNTNC_REG_SHIFT 18 245 246 /* Marvell PHY definitions */ 247 #define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */ 248 249 #define PHY_REG_CONTROL 0 250 #define PHY_REG_STATUS 1 251 #define PHY_REG_PHYID1 2 252 #define PHY_REG_PHYID2 3 253 #define PHY_REG_ANEGADV 4 254 #define PHY_REG_LINKPABIL 5 255 #define PHY_REG_ANEGEXP 6 256 #define PHY_REG_NEXTP 7 257 #define PHY_REG_LINKPNEXTP 8 258 #define PHY_REG_100BTCTRL 9 259 #define PHY_REG_1000BTSTAT 10 260 #define PHY_REG_EXTSTAT 15 261 #define PHY_REG_PHYSPCFC_CTL 16 262 #define PHY_REG_PHYSPCFC_ST 17 263 #define PHY_REG_INT_EN 18 264 #define PHY_REG_INT_ST 19 265 #define PHY_REG_EXT_PHYSPCFC_CTL 20 266 #define PHY_REG_RXERR 21 267 #define PHY_REG_EACD 22 268 #define PHY_REG_LED 24 269 #define PHY_REG_LED_OVRD 25 270 #define PHY_REG_EXT_PHYSPCFC_CTL2 26 271 #define PHY_REG_EXT_PHYSPCFC_ST 27 272 #define PHY_REG_CABLE_DIAG 28 273 274 #define PHY_REG_CONTROL_RST 0x8000 275 #define PHY_REG_CONTROL_LOOP 0x4000 276 #define PHY_REG_CONTROL_ANEG 0x1000 277 #define PHY_REG_CONTROL_ANRESTART 0x0200 278 279 #define PHY_REG_STATUS_LINK 0x0004 280 #define PHY_REG_STATUS_ANEGCMPL 0x0020 281 282 #define PHY_REG_INT_ST_ANEGCMPL 0x0800 283 #define PHY_REG_INT_ST_LINKC 0x0400 284 #define PHY_REG_INT_ST_ENERGY 0x0010 285 286 /***********************************************************************/ 287 #define GEM_RX_REJECT (-1) 288 #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 289 #define GEM_RX_BROADCAST_ACCEPT (-3) 290 #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 291 #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 292 293 #define GEM_RX_SAR_ACCEPT 0 294 295 /***********************************************************************/ 296 297 #define DESC_1_USED 0x80000000 298 #define DESC_1_LENGTH 0x00001FFF 299 300 #define DESC_1_TX_WRAP 0x40000000 301 #define DESC_1_TX_LAST 0x00008000 302 303 #define DESC_0_RX_WRAP 0x00000002 304 #define DESC_0_RX_OWNERSHIP 0x00000001 305 306 #define R_DESC_1_RX_SAR_SHIFT 25 307 #define R_DESC_1_RX_SAR_LENGTH 2 308 #define R_DESC_1_RX_SAR_MATCH (1 << 27) 309 #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 310 #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 311 #define R_DESC_1_RX_BROADCAST (1 << 31) 312 313 #define DESC_1_RX_SOF 0x00004000 314 #define DESC_1_RX_EOF 0x00008000 315 316 #define GEM_MODID_VALUE 0x00020118 317 318 static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 319 { 320 uint64_t ret = desc[0]; 321 322 if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 323 ret |= (uint64_t)desc[2] << 32; 324 } 325 return ret; 326 } 327 328 static inline unsigned tx_desc_get_used(uint32_t *desc) 329 { 330 return (desc[1] & DESC_1_USED) ? 1 : 0; 331 } 332 333 static inline void tx_desc_set_used(uint32_t *desc) 334 { 335 desc[1] |= DESC_1_USED; 336 } 337 338 static inline unsigned tx_desc_get_wrap(uint32_t *desc) 339 { 340 return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 341 } 342 343 static inline unsigned tx_desc_get_last(uint32_t *desc) 344 { 345 return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 346 } 347 348 static inline void tx_desc_set_last(uint32_t *desc) 349 { 350 desc[1] |= DESC_1_TX_LAST; 351 } 352 353 static inline unsigned tx_desc_get_length(uint32_t *desc) 354 { 355 return desc[1] & DESC_1_LENGTH; 356 } 357 358 static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) 359 { 360 DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); 361 DB_PRINT("bufaddr: 0x%08x\n", *desc); 362 DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 363 DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 364 DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 365 DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 366 } 367 368 static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 369 { 370 uint64_t ret = desc[0] & ~0x3UL; 371 372 if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 373 ret |= (uint64_t)desc[2] << 32; 374 } 375 return ret; 376 } 377 378 static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) 379 { 380 int ret = 2; 381 382 if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 383 ret += 2; 384 } 385 if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT 386 : GEM_DMACFG_TX_BD_EXT)) { 387 ret += 2; 388 } 389 390 assert(ret <= DESC_MAX_NUM_WORDS); 391 return ret; 392 } 393 394 static inline unsigned rx_desc_get_wrap(uint32_t *desc) 395 { 396 return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 397 } 398 399 static inline unsigned rx_desc_get_ownership(uint32_t *desc) 400 { 401 return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 402 } 403 404 static inline void rx_desc_set_ownership(uint32_t *desc) 405 { 406 desc[0] |= DESC_0_RX_OWNERSHIP; 407 } 408 409 static inline void rx_desc_set_sof(uint32_t *desc) 410 { 411 desc[1] |= DESC_1_RX_SOF; 412 } 413 414 static inline void rx_desc_clear_control(uint32_t *desc) 415 { 416 desc[1] = 0; 417 } 418 419 static inline void rx_desc_set_eof(uint32_t *desc) 420 { 421 desc[1] |= DESC_1_RX_EOF; 422 } 423 424 static inline void rx_desc_set_length(uint32_t *desc, unsigned len) 425 { 426 desc[1] &= ~DESC_1_LENGTH; 427 desc[1] |= len; 428 } 429 430 static inline void rx_desc_set_broadcast(uint32_t *desc) 431 { 432 desc[1] |= R_DESC_1_RX_BROADCAST; 433 } 434 435 static inline void rx_desc_set_unicast_hash(uint32_t *desc) 436 { 437 desc[1] |= R_DESC_1_RX_UNICAST_HASH; 438 } 439 440 static inline void rx_desc_set_multicast_hash(uint32_t *desc) 441 { 442 desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 443 } 444 445 static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) 446 { 447 desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 448 sar_idx); 449 desc[1] |= R_DESC_1_RX_SAR_MATCH; 450 } 451 452 /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 453 static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 454 455 /* 456 * gem_init_register_masks: 457 * One time initialization. 458 * Set masks to identify which register bits have magical clear properties 459 */ 460 static void gem_init_register_masks(CadenceGEMState *s) 461 { 462 /* Mask of register bits which are read only */ 463 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 464 s->regs_ro[GEM_NWCTRL] = 0xFFF80000; 465 s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF; 466 s->regs_ro[GEM_DMACFG] = 0x8E00F000; 467 s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08; 468 s->regs_ro[GEM_RXQBASE] = 0x00000003; 469 s->regs_ro[GEM_TXQBASE] = 0x00000003; 470 s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0; 471 s->regs_ro[GEM_ISR] = 0xFFFFFFFF; 472 s->regs_ro[GEM_IMR] = 0xFFFFFFFF; 473 s->regs_ro[GEM_MODID] = 0xFFFFFFFF; 474 475 /* Mask of register bits which are clear on read */ 476 memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 477 s->regs_rtc[GEM_ISR] = 0xFFFFFFFF; 478 479 /* Mask of register bits which are write 1 to clear */ 480 memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 481 s->regs_w1c[GEM_TXSTATUS] = 0x000001F7; 482 s->regs_w1c[GEM_RXSTATUS] = 0x0000000F; 483 484 /* Mask of register bits which are write only */ 485 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 486 s->regs_wo[GEM_NWCTRL] = 0x00073E60; 487 s->regs_wo[GEM_IER] = 0x07FFFFFF; 488 s->regs_wo[GEM_IDR] = 0x07FFFFFF; 489 } 490 491 /* 492 * phy_update_link: 493 * Make the emulated PHY link state match the QEMU "interface" state. 494 */ 495 static void phy_update_link(CadenceGEMState *s) 496 { 497 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 498 499 /* Autonegotiation status mirrors link status. */ 500 if (qemu_get_queue(s->nic)->link_down) { 501 s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 502 PHY_REG_STATUS_LINK); 503 s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 504 } else { 505 s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 506 PHY_REG_STATUS_LINK); 507 s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 508 PHY_REG_INT_ST_ANEGCMPL | 509 PHY_REG_INT_ST_ENERGY); 510 } 511 } 512 513 static bool gem_can_receive(NetClientState *nc) 514 { 515 CadenceGEMState *s; 516 int i; 517 518 s = qemu_get_nic_opaque(nc); 519 520 /* Do nothing if receive is not enabled. */ 521 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) { 522 if (s->can_rx_state != 1) { 523 s->can_rx_state = 1; 524 DB_PRINT("can't receive - no enable\n"); 525 } 526 return false; 527 } 528 529 for (i = 0; i < s->num_priority_queues; i++) { 530 if (rx_desc_get_ownership(s->rx_desc[i]) != 1) { 531 break; 532 } 533 }; 534 535 if (i == s->num_priority_queues) { 536 if (s->can_rx_state != 2) { 537 s->can_rx_state = 2; 538 DB_PRINT("can't receive - all the buffer descriptors are busy\n"); 539 } 540 return false; 541 } 542 543 if (s->can_rx_state != 0) { 544 s->can_rx_state = 0; 545 DB_PRINT("can receive\n"); 546 } 547 return true; 548 } 549 550 /* 551 * gem_update_int_status: 552 * Raise or lower interrupt based on current status. 553 */ 554 static void gem_update_int_status(CadenceGEMState *s) 555 { 556 int i; 557 558 if (!s->regs[GEM_ISR]) { 559 /* ISR isn't set, clear all the interrupts */ 560 for (i = 0; i < s->num_priority_queues; ++i) { 561 qemu_set_irq(s->irq[i], 0); 562 } 563 return; 564 } 565 566 /* If we get here we know s->regs[GEM_ISR] is set, so we don't need to 567 * check it again. 568 */ 569 if (s->num_priority_queues == 1) { 570 /* No priority queues, just trigger the interrupt */ 571 DB_PRINT("asserting int.\n"); 572 qemu_set_irq(s->irq[0], 1); 573 return; 574 } 575 576 for (i = 0; i < s->num_priority_queues; ++i) { 577 if (s->regs[GEM_INT_Q1_STATUS + i]) { 578 DB_PRINT("asserting int. (q=%d)\n", i); 579 qemu_set_irq(s->irq[i], 1); 580 } 581 } 582 } 583 584 /* 585 * gem_receive_updatestats: 586 * Increment receive statistics. 587 */ 588 static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, 589 unsigned bytes) 590 { 591 uint64_t octets; 592 593 /* Total octets (bytes) received */ 594 octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) | 595 s->regs[GEM_OCTRXHI]; 596 octets += bytes; 597 s->regs[GEM_OCTRXLO] = octets >> 32; 598 s->regs[GEM_OCTRXHI] = octets; 599 600 /* Error-free Frames received */ 601 s->regs[GEM_RXCNT]++; 602 603 /* Error-free Broadcast Frames counter */ 604 if (!memcmp(packet, broadcast_addr, 6)) { 605 s->regs[GEM_RXBROADCNT]++; 606 } 607 608 /* Error-free Multicast Frames counter */ 609 if (packet[0] == 0x01) { 610 s->regs[GEM_RXMULTICNT]++; 611 } 612 613 if (bytes <= 64) { 614 s->regs[GEM_RX64CNT]++; 615 } else if (bytes <= 127) { 616 s->regs[GEM_RX65CNT]++; 617 } else if (bytes <= 255) { 618 s->regs[GEM_RX128CNT]++; 619 } else if (bytes <= 511) { 620 s->regs[GEM_RX256CNT]++; 621 } else if (bytes <= 1023) { 622 s->regs[GEM_RX512CNT]++; 623 } else if (bytes <= 1518) { 624 s->regs[GEM_RX1024CNT]++; 625 } else { 626 s->regs[GEM_RX1519CNT]++; 627 } 628 } 629 630 /* 631 * Get the MAC Address bit from the specified position 632 */ 633 static unsigned get_bit(const uint8_t *mac, unsigned bit) 634 { 635 unsigned byte; 636 637 byte = mac[bit / 8]; 638 byte >>= (bit & 0x7); 639 byte &= 1; 640 641 return byte; 642 } 643 644 /* 645 * Calculate a GEM MAC Address hash index 646 */ 647 static unsigned calc_mac_hash(const uint8_t *mac) 648 { 649 int index_bit, mac_bit; 650 unsigned hash_index; 651 652 hash_index = 0; 653 mac_bit = 5; 654 for (index_bit = 5; index_bit >= 0; index_bit--) { 655 hash_index |= (get_bit(mac, mac_bit) ^ 656 get_bit(mac, mac_bit + 6) ^ 657 get_bit(mac, mac_bit + 12) ^ 658 get_bit(mac, mac_bit + 18) ^ 659 get_bit(mac, mac_bit + 24) ^ 660 get_bit(mac, mac_bit + 30) ^ 661 get_bit(mac, mac_bit + 36) ^ 662 get_bit(mac, mac_bit + 42)) << index_bit; 663 mac_bit--; 664 } 665 666 return hash_index; 667 } 668 669 /* 670 * gem_mac_address_filter: 671 * Accept or reject this destination address? 672 * Returns: 673 * GEM_RX_REJECT: reject 674 * >= 0: Specific address accept (which matched SAR is returned) 675 * others for various other modes of accept: 676 * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 677 * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 678 */ 679 static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) 680 { 681 uint8_t *gem_spaddr; 682 int i; 683 684 /* Promiscuous mode? */ 685 if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) { 686 return GEM_RX_PROMISCUOUS_ACCEPT; 687 } 688 689 if (!memcmp(packet, broadcast_addr, 6)) { 690 /* Reject broadcast packets? */ 691 if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) { 692 return GEM_RX_REJECT; 693 } 694 return GEM_RX_BROADCAST_ACCEPT; 695 } 696 697 /* Accept packets -w- hash match? */ 698 if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) || 699 (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) { 700 unsigned hash_index; 701 702 hash_index = calc_mac_hash(packet); 703 if (hash_index < 32) { 704 if (s->regs[GEM_HASHLO] & (1<<hash_index)) { 705 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 706 GEM_RX_UNICAST_HASH_ACCEPT; 707 } 708 } else { 709 hash_index -= 32; 710 if (s->regs[GEM_HASHHI] & (1<<hash_index)) { 711 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 712 GEM_RX_UNICAST_HASH_ACCEPT; 713 } 714 } 715 } 716 717 /* Check all 4 specific addresses */ 718 gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]); 719 for (i = 3; i >= 0; i--) { 720 if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 721 return GEM_RX_SAR_ACCEPT + i; 722 } 723 } 724 725 /* No address match; reject the packet */ 726 return GEM_RX_REJECT; 727 } 728 729 /* Figure out which queue the received data should be sent to */ 730 static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, 731 unsigned rxbufsize) 732 { 733 uint32_t reg; 734 bool matched, mismatched; 735 int i, j; 736 737 for (i = 0; i < s->num_type1_screeners; i++) { 738 reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i]; 739 matched = false; 740 mismatched = false; 741 742 /* Screening is based on UDP Port */ 743 if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) { 744 uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23]; 745 if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT, 746 GEM_ST1R_UDP_PORT_MATCH_WIDTH)) { 747 matched = true; 748 } else { 749 mismatched = true; 750 } 751 } 752 753 /* Screening is based on DS/TC */ 754 if (reg & GEM_ST1R_DSTC_ENABLE) { 755 uint8_t dscp = rxbuf_ptr[14 + 1]; 756 if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT, 757 GEM_ST1R_DSTC_MATCH_WIDTH)) { 758 matched = true; 759 } else { 760 mismatched = true; 761 } 762 } 763 764 if (matched && !mismatched) { 765 return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH); 766 } 767 } 768 769 for (i = 0; i < s->num_type2_screeners; i++) { 770 reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i]; 771 matched = false; 772 mismatched = false; 773 774 if (reg & GEM_ST2R_ETHERTYPE_ENABLE) { 775 uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; 776 int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT, 777 GEM_ST2R_ETHERTYPE_INDEX_WIDTH); 778 779 if (et_idx > s->num_type2_screeners) { 780 qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " 781 "register index: %d\n", et_idx); 782 } 783 if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 + 784 et_idx]) { 785 matched = true; 786 } else { 787 mismatched = true; 788 } 789 } 790 791 /* Compare A, B, C */ 792 for (j = 0; j < 3; j++) { 793 uint32_t cr0, cr1, mask; 794 uint16_t rx_cmp; 795 int offset; 796 int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6, 797 GEM_ST2R_COMPARE_WIDTH); 798 799 if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) { 800 continue; 801 } 802 if (cr_idx > s->num_type2_screeners) { 803 qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare " 804 "register index: %d\n", cr_idx); 805 } 806 807 cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; 808 cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1]; 809 offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT, 810 GEM_T2CW1_OFFSET_VALUE_WIDTH); 811 812 switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT, 813 GEM_T2CW1_COMPARE_OFFSET_WIDTH)) { 814 case 3: /* Skip UDP header */ 815 qemu_log_mask(LOG_UNIMP, "TCP compare offsets" 816 "unimplemented - assuming UDP\n"); 817 offset += 8; 818 /* Fallthrough */ 819 case 2: /* skip the IP header */ 820 offset += 20; 821 /* Fallthrough */ 822 case 1: /* Count from after the ethertype */ 823 offset += 14; 824 break; 825 case 0: 826 /* Offset from start of frame */ 827 break; 828 } 829 830 rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; 831 mask = extract32(cr0, 0, 16); 832 833 if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) { 834 matched = true; 835 } else { 836 mismatched = true; 837 } 838 } 839 840 if (matched && !mismatched) { 841 return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH); 842 } 843 } 844 845 /* We made it here, assume it's queue 0 */ 846 return 0; 847 } 848 849 static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) 850 { 851 hwaddr desc_addr = 0; 852 853 if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 854 desc_addr = s->regs[tx ? GEM_TBQPH : GEM_RBQPH]; 855 } 856 desc_addr <<= 32; 857 desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; 858 return desc_addr; 859 } 860 861 static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q) 862 { 863 return gem_get_desc_addr(s, true, q); 864 } 865 866 static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q) 867 { 868 return gem_get_desc_addr(s, false, q); 869 } 870 871 static void gem_get_rx_desc(CadenceGEMState *s, int q) 872 { 873 hwaddr desc_addr = gem_get_rx_desc_addr(s, q); 874 875 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr); 876 877 /* read current descriptor */ 878 address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 879 s->rx_desc[q], 880 sizeof(uint32_t) * gem_get_desc_len(s, true)); 881 882 /* Descriptor owned by software ? */ 883 if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { 884 DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); 885 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 886 s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]); 887 /* Handle interrupt consequences */ 888 gem_update_int_status(s); 889 } 890 } 891 892 /* 893 * gem_receive: 894 * Fit a packet handed to us by QEMU into the receive descriptor ring. 895 */ 896 static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 897 { 898 CadenceGEMState *s; 899 unsigned rxbufsize, bytes_to_copy; 900 unsigned rxbuf_offset; 901 uint8_t rxbuf[2048]; 902 uint8_t *rxbuf_ptr; 903 bool first_desc = true; 904 int maf; 905 int q = 0; 906 907 s = qemu_get_nic_opaque(nc); 908 909 /* Is this destination MAC address "for us" ? */ 910 maf = gem_mac_address_filter(s, buf); 911 if (maf == GEM_RX_REJECT) { 912 return -1; 913 } 914 915 /* Discard packets with receive length error enabled ? */ 916 if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) { 917 unsigned type_len; 918 919 /* Fish the ethertype / length field out of the RX packet */ 920 type_len = buf[12] << 8 | buf[13]; 921 /* It is a length field, not an ethertype */ 922 if (type_len < 0x600) { 923 if (size < type_len) { 924 /* discard */ 925 return -1; 926 } 927 } 928 } 929 930 /* 931 * Determine configured receive buffer offset (probably 0) 932 */ 933 rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> 934 GEM_NWCFG_BUFF_OFST_S; 935 936 /* The configure size of each receive buffer. Determines how many 937 * buffers needed to hold this packet. 938 */ 939 rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> 940 GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; 941 bytes_to_copy = size; 942 943 /* Hardware allows a zero value here but warns against it. To avoid QEMU 944 * indefinite loops we enforce a minimum value here 945 */ 946 if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) { 947 rxbufsize = GEM_DMACFG_RBUFSZ_MUL; 948 } 949 950 /* Pad to minimum length. Assume FCS field is stripped, logic 951 * below will increment it to the real minimum of 64 when 952 * not FCS stripping 953 */ 954 if (size < 60) { 955 size = 60; 956 } 957 958 /* Strip of FCS field ? (usually yes) */ 959 if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) { 960 rxbuf_ptr = (void *)buf; 961 } else { 962 unsigned crc_val; 963 964 if (size > sizeof(rxbuf) - sizeof(crc_val)) { 965 size = sizeof(rxbuf) - sizeof(crc_val); 966 } 967 bytes_to_copy = size; 968 /* The application wants the FCS field, which QEMU does not provide. 969 * We must try and calculate one. 970 */ 971 972 memcpy(rxbuf, buf, size); 973 memset(rxbuf + size, 0, sizeof(rxbuf) - size); 974 rxbuf_ptr = rxbuf; 975 crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60))); 976 memcpy(rxbuf + size, &crc_val, sizeof(crc_val)); 977 978 bytes_to_copy += 4; 979 size += 4; 980 } 981 982 DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size); 983 984 /* Find which queue we are targeting */ 985 q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); 986 987 while (bytes_to_copy) { 988 hwaddr desc_addr; 989 990 /* Do nothing if receive is not enabled. */ 991 if (!gem_can_receive(nc)) { 992 return -1; 993 } 994 995 DB_PRINT("copy %u bytes to 0x%" PRIx64 "\n", 996 MIN(bytes_to_copy, rxbufsize), 997 rx_desc_get_buffer(s, s->rx_desc[q])); 998 999 /* Copy packet data to emulated DMA buffer */ 1000 address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) + 1001 rxbuf_offset, 1002 MEMTXATTRS_UNSPECIFIED, rxbuf_ptr, 1003 MIN(bytes_to_copy, rxbufsize)); 1004 rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 1005 bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 1006 1007 rx_desc_clear_control(s->rx_desc[q]); 1008 1009 /* Update the descriptor. */ 1010 if (first_desc) { 1011 rx_desc_set_sof(s->rx_desc[q]); 1012 first_desc = false; 1013 } 1014 if (bytes_to_copy == 0) { 1015 rx_desc_set_eof(s->rx_desc[q]); 1016 rx_desc_set_length(s->rx_desc[q], size); 1017 } 1018 rx_desc_set_ownership(s->rx_desc[q]); 1019 1020 switch (maf) { 1021 case GEM_RX_PROMISCUOUS_ACCEPT: 1022 break; 1023 case GEM_RX_BROADCAST_ACCEPT: 1024 rx_desc_set_broadcast(s->rx_desc[q]); 1025 break; 1026 case GEM_RX_UNICAST_HASH_ACCEPT: 1027 rx_desc_set_unicast_hash(s->rx_desc[q]); 1028 break; 1029 case GEM_RX_MULTICAST_HASH_ACCEPT: 1030 rx_desc_set_multicast_hash(s->rx_desc[q]); 1031 break; 1032 case GEM_RX_REJECT: 1033 abort(); 1034 default: /* SAR */ 1035 rx_desc_set_sar(s->rx_desc[q], maf); 1036 } 1037 1038 /* Descriptor write-back. */ 1039 desc_addr = gem_get_rx_desc_addr(s, q); 1040 address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 1041 s->rx_desc[q], 1042 sizeof(uint32_t) * gem_get_desc_len(s, true)); 1043 1044 /* Next descriptor */ 1045 if (rx_desc_get_wrap(s->rx_desc[q])) { 1046 DB_PRINT("wrapping RX descriptor list\n"); 1047 s->rx_desc_addr[q] = s->regs[GEM_RXQBASE]; 1048 } else { 1049 DB_PRINT("incrementing RX descriptor list\n"); 1050 s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true); 1051 } 1052 1053 gem_get_rx_desc(s, q); 1054 } 1055 1056 /* Count it */ 1057 gem_receive_updatestats(s, buf, size); 1058 1059 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 1060 s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]); 1061 1062 /* Handle interrupt consequences */ 1063 gem_update_int_status(s); 1064 1065 return size; 1066 } 1067 1068 /* 1069 * gem_transmit_updatestats: 1070 * Increment transmit statistics. 1071 */ 1072 static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, 1073 unsigned bytes) 1074 { 1075 uint64_t octets; 1076 1077 /* Total octets (bytes) transmitted */ 1078 octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) | 1079 s->regs[GEM_OCTTXHI]; 1080 octets += bytes; 1081 s->regs[GEM_OCTTXLO] = octets >> 32; 1082 s->regs[GEM_OCTTXHI] = octets; 1083 1084 /* Error-free Frames transmitted */ 1085 s->regs[GEM_TXCNT]++; 1086 1087 /* Error-free Broadcast Frames counter */ 1088 if (!memcmp(packet, broadcast_addr, 6)) { 1089 s->regs[GEM_TXBCNT]++; 1090 } 1091 1092 /* Error-free Multicast Frames counter */ 1093 if (packet[0] == 0x01) { 1094 s->regs[GEM_TXMCNT]++; 1095 } 1096 1097 if (bytes <= 64) { 1098 s->regs[GEM_TX64CNT]++; 1099 } else if (bytes <= 127) { 1100 s->regs[GEM_TX65CNT]++; 1101 } else if (bytes <= 255) { 1102 s->regs[GEM_TX128CNT]++; 1103 } else if (bytes <= 511) { 1104 s->regs[GEM_TX256CNT]++; 1105 } else if (bytes <= 1023) { 1106 s->regs[GEM_TX512CNT]++; 1107 } else if (bytes <= 1518) { 1108 s->regs[GEM_TX1024CNT]++; 1109 } else { 1110 s->regs[GEM_TX1519CNT]++; 1111 } 1112 } 1113 1114 /* 1115 * gem_transmit: 1116 * Fish packets out of the descriptor ring and feed them to QEMU 1117 */ 1118 static void gem_transmit(CadenceGEMState *s) 1119 { 1120 uint32_t desc[DESC_MAX_NUM_WORDS]; 1121 hwaddr packet_desc_addr; 1122 uint8_t tx_packet[2048]; 1123 uint8_t *p; 1124 unsigned total_bytes; 1125 int q = 0; 1126 1127 /* Do nothing if transmit is not enabled. */ 1128 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 1129 return; 1130 } 1131 1132 DB_PRINT("\n"); 1133 1134 /* The packet we will hand off to QEMU. 1135 * Packets scattered across multiple descriptors are gathered to this 1136 * one contiguous buffer first. 1137 */ 1138 p = tx_packet; 1139 total_bytes = 0; 1140 1141 for (q = s->num_priority_queues - 1; q >= 0; q--) { 1142 /* read current descriptor */ 1143 packet_desc_addr = gem_get_tx_desc_addr(s, q); 1144 1145 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 1146 address_space_read(&s->dma_as, packet_desc_addr, 1147 MEMTXATTRS_UNSPECIFIED, desc, 1148 sizeof(uint32_t) * gem_get_desc_len(s, false)); 1149 /* Handle all descriptors owned by hardware */ 1150 while (tx_desc_get_used(desc) == 0) { 1151 1152 /* Do nothing if transmit is not enabled. */ 1153 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 1154 return; 1155 } 1156 print_gem_tx_desc(desc, q); 1157 1158 /* The real hardware would eat this (and possibly crash). 1159 * For QEMU let's lend a helping hand. 1160 */ 1161 if ((tx_desc_get_buffer(s, desc) == 0) || 1162 (tx_desc_get_length(desc) == 0)) { 1163 DB_PRINT("Invalid TX descriptor @ 0x%x\n", 1164 (unsigned)packet_desc_addr); 1165 break; 1166 } 1167 1168 if (tx_desc_get_length(desc) > sizeof(tx_packet) - 1169 (p - tx_packet)) { 1170 DB_PRINT("TX descriptor @ 0x%" HWADDR_PRIx \ 1171 " too large: size 0x%x space 0x%zx\n", 1172 packet_desc_addr, tx_desc_get_length(desc), 1173 sizeof(tx_packet) - (p - tx_packet)); 1174 break; 1175 } 1176 1177 /* Gather this fragment of the packet from "dma memory" to our 1178 * contig buffer. 1179 */ 1180 address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc), 1181 MEMTXATTRS_UNSPECIFIED, 1182 p, tx_desc_get_length(desc)); 1183 p += tx_desc_get_length(desc); 1184 total_bytes += tx_desc_get_length(desc); 1185 1186 /* Last descriptor for this packet; hand the whole thing off */ 1187 if (tx_desc_get_last(desc)) { 1188 uint32_t desc_first[DESC_MAX_NUM_WORDS]; 1189 hwaddr desc_addr = gem_get_tx_desc_addr(s, q); 1190 1191 /* Modify the 1st descriptor of this packet to be owned by 1192 * the processor. 1193 */ 1194 address_space_read(&s->dma_as, desc_addr, 1195 MEMTXATTRS_UNSPECIFIED, desc_first, 1196 sizeof(desc_first)); 1197 tx_desc_set_used(desc_first); 1198 address_space_write(&s->dma_as, desc_addr, 1199 MEMTXATTRS_UNSPECIFIED, desc_first, 1200 sizeof(desc_first)); 1201 /* Advance the hardware current descriptor past this packet */ 1202 if (tx_desc_get_wrap(desc)) { 1203 s->tx_desc_addr[q] = s->regs[GEM_TXQBASE]; 1204 } else { 1205 s->tx_desc_addr[q] = packet_desc_addr + 1206 4 * gem_get_desc_len(s, false); 1207 } 1208 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); 1209 1210 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 1211 s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]); 1212 1213 /* Update queue interrupt status */ 1214 if (s->num_priority_queues > 1) { 1215 s->regs[GEM_INT_Q1_STATUS + q] |= 1216 GEM_INT_TXCMPL & ~(s->regs[GEM_INT_Q1_MASK + q]); 1217 } 1218 1219 /* Handle interrupt consequences */ 1220 gem_update_int_status(s); 1221 1222 /* Is checksum offload enabled? */ 1223 if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { 1224 net_checksum_calculate(tx_packet, total_bytes); 1225 } 1226 1227 /* Update MAC statistics */ 1228 gem_transmit_updatestats(s, tx_packet, total_bytes); 1229 1230 /* Send the packet somewhere */ 1231 if (s->phy_loop || (s->regs[GEM_NWCTRL] & 1232 GEM_NWCTRL_LOCALLOOP)) { 1233 gem_receive(qemu_get_queue(s->nic), tx_packet, 1234 total_bytes); 1235 } else { 1236 qemu_send_packet(qemu_get_queue(s->nic), tx_packet, 1237 total_bytes); 1238 } 1239 1240 /* Prepare for next packet */ 1241 p = tx_packet; 1242 total_bytes = 0; 1243 } 1244 1245 /* read next descriptor */ 1246 if (tx_desc_get_wrap(desc)) { 1247 tx_desc_set_last(desc); 1248 1249 if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 1250 packet_desc_addr = s->regs[GEM_TBQPH]; 1251 packet_desc_addr <<= 32; 1252 } else { 1253 packet_desc_addr = 0; 1254 } 1255 packet_desc_addr |= s->regs[GEM_TXQBASE]; 1256 } else { 1257 packet_desc_addr += 4 * gem_get_desc_len(s, false); 1258 } 1259 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 1260 address_space_read(&s->dma_as, packet_desc_addr, 1261 MEMTXATTRS_UNSPECIFIED, desc, 1262 sizeof(uint32_t) * gem_get_desc_len(s, false)); 1263 } 1264 1265 if (tx_desc_get_used(desc)) { 1266 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED; 1267 s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]); 1268 gem_update_int_status(s); 1269 } 1270 } 1271 } 1272 1273 static void gem_phy_reset(CadenceGEMState *s) 1274 { 1275 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 1276 s->phy_regs[PHY_REG_CONTROL] = 0x1140; 1277 s->phy_regs[PHY_REG_STATUS] = 0x7969; 1278 s->phy_regs[PHY_REG_PHYID1] = 0x0141; 1279 s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 1280 s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 1281 s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 1282 s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 1283 s->phy_regs[PHY_REG_NEXTP] = 0x2001; 1284 s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 1285 s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 1286 s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 1287 s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 1288 s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 1289 s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; 1290 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 1291 s->phy_regs[PHY_REG_LED] = 0x4100; 1292 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 1293 s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 1294 1295 phy_update_link(s); 1296 } 1297 1298 static void gem_reset(DeviceState *d) 1299 { 1300 int i; 1301 CadenceGEMState *s = CADENCE_GEM(d); 1302 const uint8_t *a; 1303 uint32_t queues_mask = 0; 1304 1305 DB_PRINT("\n"); 1306 1307 /* Set post reset register values */ 1308 memset(&s->regs[0], 0, sizeof(s->regs)); 1309 s->regs[GEM_NWCFG] = 0x00080000; 1310 s->regs[GEM_NWSTATUS] = 0x00000006; 1311 s->regs[GEM_DMACFG] = 0x00020784; 1312 s->regs[GEM_IMR] = 0x07ffffff; 1313 s->regs[GEM_TXPAUSE] = 0x0000ffff; 1314 s->regs[GEM_TXPARTIALSF] = 0x000003ff; 1315 s->regs[GEM_RXPARTIALSF] = 0x000003ff; 1316 s->regs[GEM_MODID] = s->revision; 1317 s->regs[GEM_DESCONF] = 0x02500111; 1318 s->regs[GEM_DESCONF2] = 0x2ab13fff; 1319 s->regs[GEM_DESCONF5] = 0x002f2045; 1320 s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK; 1321 1322 if (s->num_priority_queues > 1) { 1323 queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); 1324 s->regs[GEM_DESCONF6] |= queues_mask; 1325 } 1326 1327 /* Set MAC address */ 1328 a = &s->conf.macaddr.a[0]; 1329 s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); 1330 s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8); 1331 1332 for (i = 0; i < 4; i++) { 1333 s->sar_active[i] = false; 1334 } 1335 1336 gem_phy_reset(s); 1337 1338 gem_update_int_status(s); 1339 } 1340 1341 static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) 1342 { 1343 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 1344 return s->phy_regs[reg_num]; 1345 } 1346 1347 static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 1348 { 1349 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 1350 1351 switch (reg_num) { 1352 case PHY_REG_CONTROL: 1353 if (val & PHY_REG_CONTROL_RST) { 1354 /* Phy reset */ 1355 gem_phy_reset(s); 1356 val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 1357 s->phy_loop = 0; 1358 } 1359 if (val & PHY_REG_CONTROL_ANEG) { 1360 /* Complete autonegotiation immediately */ 1361 val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART); 1362 s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 1363 } 1364 if (val & PHY_REG_CONTROL_LOOP) { 1365 DB_PRINT("PHY placed in loopback\n"); 1366 s->phy_loop = 1; 1367 } else { 1368 s->phy_loop = 0; 1369 } 1370 break; 1371 } 1372 s->phy_regs[reg_num] = val; 1373 } 1374 1375 /* 1376 * gem_read32: 1377 * Read a GEM register. 1378 */ 1379 static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 1380 { 1381 CadenceGEMState *s; 1382 uint32_t retval; 1383 s = (CadenceGEMState *)opaque; 1384 1385 offset >>= 2; 1386 retval = s->regs[offset]; 1387 1388 DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 1389 1390 switch (offset) { 1391 case GEM_ISR: 1392 DB_PRINT("lowering irqs on ISR read\n"); 1393 /* The interrupts get updated at the end of the function. */ 1394 break; 1395 case GEM_PHYMNTNC: 1396 if (retval & GEM_PHYMNTNC_OP_R) { 1397 uint32_t phy_addr, reg_num; 1398 1399 phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1400 if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 1401 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1402 retval &= 0xFFFF0000; 1403 retval |= gem_phy_read(s, reg_num); 1404 } else { 1405 retval |= 0xFFFF; /* No device at this address */ 1406 } 1407 } 1408 break; 1409 } 1410 1411 /* Squash read to clear bits */ 1412 s->regs[offset] &= ~(s->regs_rtc[offset]); 1413 1414 /* Do not provide write only bits */ 1415 retval &= ~(s->regs_wo[offset]); 1416 1417 DB_PRINT("0x%08x\n", retval); 1418 gem_update_int_status(s); 1419 return retval; 1420 } 1421 1422 /* 1423 * gem_write32: 1424 * Write a GEM register. 1425 */ 1426 static void gem_write(void *opaque, hwaddr offset, uint64_t val, 1427 unsigned size) 1428 { 1429 CadenceGEMState *s = (CadenceGEMState *)opaque; 1430 uint32_t readonly; 1431 int i; 1432 1433 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 1434 offset >>= 2; 1435 1436 /* Squash bits which are read only in write value */ 1437 val &= ~(s->regs_ro[offset]); 1438 /* Preserve (only) bits which are read only and wtc in register */ 1439 readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 1440 1441 /* Copy register write to backing store */ 1442 s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1443 1444 /* do w1c */ 1445 s->regs[offset] &= ~(s->regs_w1c[offset] & val); 1446 1447 /* Handle register write side effects */ 1448 switch (offset) { 1449 case GEM_NWCTRL: 1450 if (val & GEM_NWCTRL_RXENA) { 1451 for (i = 0; i < s->num_priority_queues; ++i) { 1452 gem_get_rx_desc(s, i); 1453 } 1454 } 1455 if (val & GEM_NWCTRL_TXSTART) { 1456 gem_transmit(s); 1457 } 1458 if (!(val & GEM_NWCTRL_TXENA)) { 1459 /* Reset to start of Q when transmit disabled. */ 1460 for (i = 0; i < s->num_priority_queues; i++) { 1461 s->tx_desc_addr[i] = s->regs[GEM_TXQBASE]; 1462 } 1463 } 1464 if (gem_can_receive(qemu_get_queue(s->nic))) { 1465 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 1466 } 1467 break; 1468 1469 case GEM_TXSTATUS: 1470 gem_update_int_status(s); 1471 break; 1472 case GEM_RXQBASE: 1473 s->rx_desc_addr[0] = val; 1474 break; 1475 case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR: 1476 s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val; 1477 break; 1478 case GEM_TXQBASE: 1479 s->tx_desc_addr[0] = val; 1480 break; 1481 case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR: 1482 s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val; 1483 break; 1484 case GEM_RXSTATUS: 1485 gem_update_int_status(s); 1486 break; 1487 case GEM_IER: 1488 s->regs[GEM_IMR] &= ~val; 1489 gem_update_int_status(s); 1490 break; 1491 case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE: 1492 s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val; 1493 gem_update_int_status(s); 1494 break; 1495 case GEM_IDR: 1496 s->regs[GEM_IMR] |= val; 1497 gem_update_int_status(s); 1498 break; 1499 case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE: 1500 s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val; 1501 gem_update_int_status(s); 1502 break; 1503 case GEM_SPADDR1LO: 1504 case GEM_SPADDR2LO: 1505 case GEM_SPADDR3LO: 1506 case GEM_SPADDR4LO: 1507 s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false; 1508 break; 1509 case GEM_SPADDR1HI: 1510 case GEM_SPADDR2HI: 1511 case GEM_SPADDR3HI: 1512 case GEM_SPADDR4HI: 1513 s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true; 1514 break; 1515 case GEM_PHYMNTNC: 1516 if (val & GEM_PHYMNTNC_OP_W) { 1517 uint32_t phy_addr, reg_num; 1518 1519 phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1520 if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 1521 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1522 gem_phy_write(s, reg_num, val); 1523 } 1524 } 1525 break; 1526 } 1527 1528 DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 1529 } 1530 1531 static const MemoryRegionOps gem_ops = { 1532 .read = gem_read, 1533 .write = gem_write, 1534 .endianness = DEVICE_LITTLE_ENDIAN, 1535 }; 1536 1537 static void gem_set_link(NetClientState *nc) 1538 { 1539 CadenceGEMState *s = qemu_get_nic_opaque(nc); 1540 1541 DB_PRINT("\n"); 1542 phy_update_link(s); 1543 gem_update_int_status(s); 1544 } 1545 1546 static NetClientInfo net_gem_info = { 1547 .type = NET_CLIENT_DRIVER_NIC, 1548 .size = sizeof(NICState), 1549 .can_receive = gem_can_receive, 1550 .receive = gem_receive, 1551 .link_status_changed = gem_set_link, 1552 }; 1553 1554 static void gem_realize(DeviceState *dev, Error **errp) 1555 { 1556 CadenceGEMState *s = CADENCE_GEM(dev); 1557 int i; 1558 1559 address_space_init(&s->dma_as, 1560 s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); 1561 1562 if (s->num_priority_queues == 0 || 1563 s->num_priority_queues > MAX_PRIORITY_QUEUES) { 1564 error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, 1565 s->num_priority_queues); 1566 return; 1567 } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) { 1568 error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8, 1569 s->num_type1_screeners); 1570 return; 1571 } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) { 1572 error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8, 1573 s->num_type2_screeners); 1574 return; 1575 } 1576 1577 for (i = 0; i < s->num_priority_queues; ++i) { 1578 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 1579 } 1580 1581 qemu_macaddr_default_if_unset(&s->conf.macaddr); 1582 1583 s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1584 object_get_typename(OBJECT(dev)), dev->id, s); 1585 } 1586 1587 static void gem_init(Object *obj) 1588 { 1589 CadenceGEMState *s = CADENCE_GEM(obj); 1590 DeviceState *dev = DEVICE(obj); 1591 1592 DB_PRINT("\n"); 1593 1594 gem_init_register_masks(s); 1595 memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1596 "enet", sizeof(s->regs)); 1597 1598 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 1599 1600 object_property_add_link(obj, "dma", TYPE_MEMORY_REGION, 1601 (Object **)&s->dma_mr, 1602 qdev_prop_allow_set_link_before_realize, 1603 OBJ_PROP_LINK_STRONG); 1604 } 1605 1606 static const VMStateDescription vmstate_cadence_gem = { 1607 .name = "cadence_gem", 1608 .version_id = 4, 1609 .minimum_version_id = 4, 1610 .fields = (VMStateField[]) { 1611 VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), 1612 VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), 1613 VMSTATE_UINT8(phy_loop, CadenceGEMState), 1614 VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState, 1615 MAX_PRIORITY_QUEUES), 1616 VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState, 1617 MAX_PRIORITY_QUEUES), 1618 VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), 1619 VMSTATE_END_OF_LIST(), 1620 } 1621 }; 1622 1623 static Property gem_properties[] = { 1624 DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), 1625 DEFINE_PROP_UINT32("revision", CadenceGEMState, revision, 1626 GEM_MODID_VALUE), 1627 DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, 1628 num_priority_queues, 1), 1629 DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, 1630 num_type1_screeners, 4), 1631 DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState, 1632 num_type2_screeners, 4), 1633 DEFINE_PROP_END_OF_LIST(), 1634 }; 1635 1636 static void gem_class_init(ObjectClass *klass, void *data) 1637 { 1638 DeviceClass *dc = DEVICE_CLASS(klass); 1639 1640 dc->realize = gem_realize; 1641 device_class_set_props(dc, gem_properties); 1642 dc->vmsd = &vmstate_cadence_gem; 1643 dc->reset = gem_reset; 1644 } 1645 1646 static const TypeInfo gem_info = { 1647 .name = TYPE_CADENCE_GEM, 1648 .parent = TYPE_SYS_BUS_DEVICE, 1649 .instance_size = sizeof(CadenceGEMState), 1650 .instance_init = gem_init, 1651 .class_init = gem_class_init, 1652 }; 1653 1654 static void gem_register_types(void) 1655 { 1656 type_register_static(&gem_info); 1657 } 1658 1659 type_init(gem_register_types) 1660