1 /* 2 * QEMU Cadence GEM emulation 3 * 4 * Copyright (c) 2011 Xilinx, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include <zlib.h> /* For crc32 */ 27 28 #include "hw/net/cadence_gem.h" 29 #include "qapi/error.h" 30 #include "qemu/log.h" 31 #include "sysemu/dma.h" 32 #include "net/checksum.h" 33 34 #ifdef CADENCE_GEM_ERR_DEBUG 35 #define DB_PRINT(...) do { \ 36 fprintf(stderr, ": %s: ", __func__); \ 37 fprintf(stderr, ## __VA_ARGS__); \ 38 } while (0) 39 #else 40 #define DB_PRINT(...) 41 #endif 42 43 #define GEM_NWCTRL (0x00000000/4) /* Network Control reg */ 44 #define GEM_NWCFG (0x00000004/4) /* Network Config reg */ 45 #define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */ 46 #define GEM_USERIO (0x0000000C/4) /* User IO reg */ 47 #define GEM_DMACFG (0x00000010/4) /* DMA Control reg */ 48 #define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */ 49 #define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */ 50 #define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */ 51 #define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */ 52 #define GEM_ISR (0x00000024/4) /* Interrupt Status reg */ 53 #define GEM_IER (0x00000028/4) /* Interrupt Enable reg */ 54 #define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */ 55 #define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */ 56 #define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintenance reg */ 57 #define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */ 58 #define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */ 59 #define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */ 60 #define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */ 61 #define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */ 62 #define GEM_HASHHI (0x00000084/4) /* Hash High address reg */ 63 #define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */ 64 #define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */ 65 #define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */ 66 #define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */ 67 #define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */ 68 #define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */ 69 #define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */ 70 #define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */ 71 #define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */ 72 #define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */ 73 #define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */ 74 #define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */ 75 #define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */ 76 #define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */ 77 #define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */ 78 #define GEM_MODID (0x000000FC/4) /* Module ID reg */ 79 #define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */ 80 #define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */ 81 #define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */ 82 #define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */ 83 #define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */ 84 #define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */ 85 #define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */ 86 #define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */ 87 #define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */ 88 #define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */ 89 #define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */ 90 #define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */ 91 #define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */ 92 #define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */ 93 #define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */ 94 #define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */ 95 #define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */ 96 #define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */ 97 #define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */ 98 #define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */ 99 #define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */ 100 #define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */ 101 #define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */ 102 #define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */ 103 #define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */ 104 #define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */ 105 #define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */ 106 #define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */ 107 #define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */ 108 #define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */ 109 #define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */ 110 #define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */ 111 #define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */ 112 #define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */ 113 #define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */ 114 #define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */ 115 #define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */ 116 #define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */ 117 #define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */ 118 #define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */ 119 #define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */ 120 #define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */ 121 #define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */ 122 #define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */ 123 #define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */ 124 125 #define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */ 126 #define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */ 127 #define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */ 128 #define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */ 129 #define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */ 130 #define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */ 131 #define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */ 132 #define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */ 133 #define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */ 134 #define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */ 135 #define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */ 136 #define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */ 137 138 /* Design Configuration Registers */ 139 #define GEM_DESCONF (0x00000280/4) 140 #define GEM_DESCONF2 (0x00000284/4) 141 #define GEM_DESCONF3 (0x00000288/4) 142 #define GEM_DESCONF4 (0x0000028C/4) 143 #define GEM_DESCONF5 (0x00000290/4) 144 #define GEM_DESCONF6 (0x00000294/4) 145 #define GEM_DESCONF6_64B_MASK (1U << 23) 146 #define GEM_DESCONF7 (0x00000298/4) 147 148 #define GEM_INT_Q1_STATUS (0x00000400 / 4) 149 #define GEM_INT_Q1_MASK (0x00000640 / 4) 150 151 #define GEM_TRANSMIT_Q1_PTR (0x00000440 / 4) 152 #define GEM_TRANSMIT_Q7_PTR (GEM_TRANSMIT_Q1_PTR + 6) 153 154 #define GEM_RECEIVE_Q1_PTR (0x00000480 / 4) 155 #define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6) 156 157 #define GEM_TBQPH (0x000004C8 / 4) 158 #define GEM_RBQPH (0x000004D4 / 4) 159 160 #define GEM_INT_Q1_ENABLE (0x00000600 / 4) 161 #define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6) 162 163 #define GEM_INT_Q1_DISABLE (0x00000620 / 4) 164 #define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6) 165 166 #define GEM_INT_Q1_MASK (0x00000640 / 4) 167 #define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6) 168 169 #define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500 / 4) 170 171 #define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29) 172 #define GEM_ST1R_DSTC_ENABLE (1 << 28) 173 #define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12) 174 #define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1) 175 #define GEM_ST1R_DSTC_MATCH_SHIFT (4) 176 #define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1) 177 #define GEM_ST1R_QUEUE_SHIFT (0) 178 #define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1) 179 180 #define GEM_SCREENING_TYPE2_REGISTER_0 (0x00000540 / 4) 181 182 #define GEM_ST2R_COMPARE_A_ENABLE (1 << 18) 183 #define GEM_ST2R_COMPARE_A_SHIFT (13) 184 #define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1) 185 #define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12) 186 #define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9) 187 #define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \ 188 + 1) 189 #define GEM_ST2R_QUEUE_SHIFT (0) 190 #define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1) 191 192 #define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 (0x000006e0 / 4) 193 #define GEM_TYPE2_COMPARE_0_WORD_0 (0x00000700 / 4) 194 195 #define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7) 196 #define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1) 197 #define GEM_T2CW1_OFFSET_VALUE_SHIFT (0) 198 #define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1) 199 200 /*****************************************/ 201 #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ 202 #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */ 203 #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */ 204 #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */ 205 206 #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ 207 #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */ 208 #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ 209 #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ 210 #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ 211 #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ 212 #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ 213 #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ 214 215 #define GEM_DMACFG_ADDR_64B (1U << 30) 216 #define GEM_DMACFG_TX_BD_EXT (1U << 29) 217 #define GEM_DMACFG_RX_BD_EXT (1U << 28) 218 #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ 219 #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ 220 #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 221 #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ 222 223 #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 224 #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 225 226 #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 227 #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 228 229 /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 230 #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 231 #define GEM_INT_TXUSED 0x00000008 232 #define GEM_INT_RXUSED 0x00000004 233 #define GEM_INT_RXCMPL 0x00000002 234 235 #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 236 #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 237 #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 238 #define GEM_PHYMNTNC_ADDR_SHFT 23 239 #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 240 #define GEM_PHYMNTNC_REG_SHIFT 18 241 242 /* Marvell PHY definitions */ 243 #define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */ 244 245 #define PHY_REG_CONTROL 0 246 #define PHY_REG_STATUS 1 247 #define PHY_REG_PHYID1 2 248 #define PHY_REG_PHYID2 3 249 #define PHY_REG_ANEGADV 4 250 #define PHY_REG_LINKPABIL 5 251 #define PHY_REG_ANEGEXP 6 252 #define PHY_REG_NEXTP 7 253 #define PHY_REG_LINKPNEXTP 8 254 #define PHY_REG_100BTCTRL 9 255 #define PHY_REG_1000BTSTAT 10 256 #define PHY_REG_EXTSTAT 15 257 #define PHY_REG_PHYSPCFC_CTL 16 258 #define PHY_REG_PHYSPCFC_ST 17 259 #define PHY_REG_INT_EN 18 260 #define PHY_REG_INT_ST 19 261 #define PHY_REG_EXT_PHYSPCFC_CTL 20 262 #define PHY_REG_RXERR 21 263 #define PHY_REG_EACD 22 264 #define PHY_REG_LED 24 265 #define PHY_REG_LED_OVRD 25 266 #define PHY_REG_EXT_PHYSPCFC_CTL2 26 267 #define PHY_REG_EXT_PHYSPCFC_ST 27 268 #define PHY_REG_CABLE_DIAG 28 269 270 #define PHY_REG_CONTROL_RST 0x8000 271 #define PHY_REG_CONTROL_LOOP 0x4000 272 #define PHY_REG_CONTROL_ANEG 0x1000 273 274 #define PHY_REG_STATUS_LINK 0x0004 275 #define PHY_REG_STATUS_ANEGCMPL 0x0020 276 277 #define PHY_REG_INT_ST_ANEGCMPL 0x0800 278 #define PHY_REG_INT_ST_LINKC 0x0400 279 #define PHY_REG_INT_ST_ENERGY 0x0010 280 281 /***********************************************************************/ 282 #define GEM_RX_REJECT (-1) 283 #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 284 #define GEM_RX_BROADCAST_ACCEPT (-3) 285 #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 286 #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 287 288 #define GEM_RX_SAR_ACCEPT 0 289 290 /***********************************************************************/ 291 292 #define DESC_1_USED 0x80000000 293 #define DESC_1_LENGTH 0x00001FFF 294 295 #define DESC_1_TX_WRAP 0x40000000 296 #define DESC_1_TX_LAST 0x00008000 297 298 #define DESC_0_RX_WRAP 0x00000002 299 #define DESC_0_RX_OWNERSHIP 0x00000001 300 301 #define R_DESC_1_RX_SAR_SHIFT 25 302 #define R_DESC_1_RX_SAR_LENGTH 2 303 #define R_DESC_1_RX_SAR_MATCH (1 << 27) 304 #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 305 #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 306 #define R_DESC_1_RX_BROADCAST (1 << 31) 307 308 #define DESC_1_RX_SOF 0x00004000 309 #define DESC_1_RX_EOF 0x00008000 310 311 #define GEM_MODID_VALUE 0x00020118 312 313 static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 314 { 315 uint64_t ret = desc[0]; 316 317 if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 318 ret |= (uint64_t)desc[2] << 32; 319 } 320 return ret; 321 } 322 323 static inline unsigned tx_desc_get_used(uint32_t *desc) 324 { 325 return (desc[1] & DESC_1_USED) ? 1 : 0; 326 } 327 328 static inline void tx_desc_set_used(uint32_t *desc) 329 { 330 desc[1] |= DESC_1_USED; 331 } 332 333 static inline unsigned tx_desc_get_wrap(uint32_t *desc) 334 { 335 return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 336 } 337 338 static inline unsigned tx_desc_get_last(uint32_t *desc) 339 { 340 return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 341 } 342 343 static inline void tx_desc_set_last(uint32_t *desc) 344 { 345 desc[1] |= DESC_1_TX_LAST; 346 } 347 348 static inline unsigned tx_desc_get_length(uint32_t *desc) 349 { 350 return desc[1] & DESC_1_LENGTH; 351 } 352 353 static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) 354 { 355 DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); 356 DB_PRINT("bufaddr: 0x%08x\n", *desc); 357 DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 358 DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 359 DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 360 DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 361 } 362 363 static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 364 { 365 uint64_t ret = desc[0] & ~0x3UL; 366 367 if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 368 ret |= (uint64_t)desc[2] << 32; 369 } 370 return ret; 371 } 372 373 static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) 374 { 375 int ret = 2; 376 377 if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 378 ret += 2; 379 } 380 if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT 381 : GEM_DMACFG_TX_BD_EXT)) { 382 ret += 2; 383 } 384 385 assert(ret <= DESC_MAX_NUM_WORDS); 386 return ret; 387 } 388 389 static inline unsigned rx_desc_get_wrap(uint32_t *desc) 390 { 391 return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 392 } 393 394 static inline unsigned rx_desc_get_ownership(uint32_t *desc) 395 { 396 return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 397 } 398 399 static inline void rx_desc_set_ownership(uint32_t *desc) 400 { 401 desc[0] |= DESC_0_RX_OWNERSHIP; 402 } 403 404 static inline void rx_desc_set_sof(uint32_t *desc) 405 { 406 desc[1] |= DESC_1_RX_SOF; 407 } 408 409 static inline void rx_desc_set_eof(uint32_t *desc) 410 { 411 desc[1] |= DESC_1_RX_EOF; 412 } 413 414 static inline void rx_desc_set_length(uint32_t *desc, unsigned len) 415 { 416 desc[1] &= ~DESC_1_LENGTH; 417 desc[1] |= len; 418 } 419 420 static inline void rx_desc_set_broadcast(uint32_t *desc) 421 { 422 desc[1] |= R_DESC_1_RX_BROADCAST; 423 } 424 425 static inline void rx_desc_set_unicast_hash(uint32_t *desc) 426 { 427 desc[1] |= R_DESC_1_RX_UNICAST_HASH; 428 } 429 430 static inline void rx_desc_set_multicast_hash(uint32_t *desc) 431 { 432 desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 433 } 434 435 static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) 436 { 437 desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 438 sar_idx); 439 desc[1] |= R_DESC_1_RX_SAR_MATCH; 440 } 441 442 /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 443 static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 444 445 /* 446 * gem_init_register_masks: 447 * One time initialization. 448 * Set masks to identify which register bits have magical clear properties 449 */ 450 static void gem_init_register_masks(CadenceGEMState *s) 451 { 452 /* Mask of register bits which are read only */ 453 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 454 s->regs_ro[GEM_NWCTRL] = 0xFFF80000; 455 s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF; 456 s->regs_ro[GEM_DMACFG] = 0x8E00F000; 457 s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08; 458 s->regs_ro[GEM_RXQBASE] = 0x00000003; 459 s->regs_ro[GEM_TXQBASE] = 0x00000003; 460 s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0; 461 s->regs_ro[GEM_ISR] = 0xFFFFFFFF; 462 s->regs_ro[GEM_IMR] = 0xFFFFFFFF; 463 s->regs_ro[GEM_MODID] = 0xFFFFFFFF; 464 465 /* Mask of register bits which are clear on read */ 466 memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 467 s->regs_rtc[GEM_ISR] = 0xFFFFFFFF; 468 469 /* Mask of register bits which are write 1 to clear */ 470 memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 471 s->regs_w1c[GEM_TXSTATUS] = 0x000001F7; 472 s->regs_w1c[GEM_RXSTATUS] = 0x0000000F; 473 474 /* Mask of register bits which are write only */ 475 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 476 s->regs_wo[GEM_NWCTRL] = 0x00073E60; 477 s->regs_wo[GEM_IER] = 0x07FFFFFF; 478 s->regs_wo[GEM_IDR] = 0x07FFFFFF; 479 } 480 481 /* 482 * phy_update_link: 483 * Make the emulated PHY link state match the QEMU "interface" state. 484 */ 485 static void phy_update_link(CadenceGEMState *s) 486 { 487 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 488 489 /* Autonegotiation status mirrors link status. */ 490 if (qemu_get_queue(s->nic)->link_down) { 491 s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 492 PHY_REG_STATUS_LINK); 493 s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 494 } else { 495 s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 496 PHY_REG_STATUS_LINK); 497 s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 498 PHY_REG_INT_ST_ANEGCMPL | 499 PHY_REG_INT_ST_ENERGY); 500 } 501 } 502 503 static int gem_can_receive(NetClientState *nc) 504 { 505 CadenceGEMState *s; 506 int i; 507 508 s = qemu_get_nic_opaque(nc); 509 510 /* Do nothing if receive is not enabled. */ 511 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) { 512 if (s->can_rx_state != 1) { 513 s->can_rx_state = 1; 514 DB_PRINT("can't receive - no enable\n"); 515 } 516 return 0; 517 } 518 519 for (i = 0; i < s->num_priority_queues; i++) { 520 if (rx_desc_get_ownership(s->rx_desc[i]) != 1) { 521 break; 522 } 523 }; 524 525 if (i == s->num_priority_queues) { 526 if (s->can_rx_state != 2) { 527 s->can_rx_state = 2; 528 DB_PRINT("can't receive - all the buffer descriptors are busy\n"); 529 } 530 return 0; 531 } 532 533 if (s->can_rx_state != 0) { 534 s->can_rx_state = 0; 535 DB_PRINT("can receive\n"); 536 } 537 return 1; 538 } 539 540 /* 541 * gem_update_int_status: 542 * Raise or lower interrupt based on current status. 543 */ 544 static void gem_update_int_status(CadenceGEMState *s) 545 { 546 int i; 547 548 if (!s->regs[GEM_ISR]) { 549 /* ISR isn't set, clear all the interrupts */ 550 for (i = 0; i < s->num_priority_queues; ++i) { 551 qemu_set_irq(s->irq[i], 0); 552 } 553 return; 554 } 555 556 /* If we get here we know s->regs[GEM_ISR] is set, so we don't need to 557 * check it again. 558 */ 559 if (s->num_priority_queues == 1) { 560 /* No priority queues, just trigger the interrupt */ 561 DB_PRINT("asserting int.\n"); 562 qemu_set_irq(s->irq[0], 1); 563 return; 564 } 565 566 for (i = 0; i < s->num_priority_queues; ++i) { 567 if (s->regs[GEM_INT_Q1_STATUS + i]) { 568 DB_PRINT("asserting int. (q=%d)\n", i); 569 qemu_set_irq(s->irq[i], 1); 570 } 571 } 572 } 573 574 /* 575 * gem_receive_updatestats: 576 * Increment receive statistics. 577 */ 578 static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, 579 unsigned bytes) 580 { 581 uint64_t octets; 582 583 /* Total octets (bytes) received */ 584 octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) | 585 s->regs[GEM_OCTRXHI]; 586 octets += bytes; 587 s->regs[GEM_OCTRXLO] = octets >> 32; 588 s->regs[GEM_OCTRXHI] = octets; 589 590 /* Error-free Frames received */ 591 s->regs[GEM_RXCNT]++; 592 593 /* Error-free Broadcast Frames counter */ 594 if (!memcmp(packet, broadcast_addr, 6)) { 595 s->regs[GEM_RXBROADCNT]++; 596 } 597 598 /* Error-free Multicast Frames counter */ 599 if (packet[0] == 0x01) { 600 s->regs[GEM_RXMULTICNT]++; 601 } 602 603 if (bytes <= 64) { 604 s->regs[GEM_RX64CNT]++; 605 } else if (bytes <= 127) { 606 s->regs[GEM_RX65CNT]++; 607 } else if (bytes <= 255) { 608 s->regs[GEM_RX128CNT]++; 609 } else if (bytes <= 511) { 610 s->regs[GEM_RX256CNT]++; 611 } else if (bytes <= 1023) { 612 s->regs[GEM_RX512CNT]++; 613 } else if (bytes <= 1518) { 614 s->regs[GEM_RX1024CNT]++; 615 } else { 616 s->regs[GEM_RX1519CNT]++; 617 } 618 } 619 620 /* 621 * Get the MAC Address bit from the specified position 622 */ 623 static unsigned get_bit(const uint8_t *mac, unsigned bit) 624 { 625 unsigned byte; 626 627 byte = mac[bit / 8]; 628 byte >>= (bit & 0x7); 629 byte &= 1; 630 631 return byte; 632 } 633 634 /* 635 * Calculate a GEM MAC Address hash index 636 */ 637 static unsigned calc_mac_hash(const uint8_t *mac) 638 { 639 int index_bit, mac_bit; 640 unsigned hash_index; 641 642 hash_index = 0; 643 mac_bit = 5; 644 for (index_bit = 5; index_bit >= 0; index_bit--) { 645 hash_index |= (get_bit(mac, mac_bit) ^ 646 get_bit(mac, mac_bit + 6) ^ 647 get_bit(mac, mac_bit + 12) ^ 648 get_bit(mac, mac_bit + 18) ^ 649 get_bit(mac, mac_bit + 24) ^ 650 get_bit(mac, mac_bit + 30) ^ 651 get_bit(mac, mac_bit + 36) ^ 652 get_bit(mac, mac_bit + 42)) << index_bit; 653 mac_bit--; 654 } 655 656 return hash_index; 657 } 658 659 /* 660 * gem_mac_address_filter: 661 * Accept or reject this destination address? 662 * Returns: 663 * GEM_RX_REJECT: reject 664 * >= 0: Specific address accept (which matched SAR is returned) 665 * others for various other modes of accept: 666 * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 667 * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 668 */ 669 static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) 670 { 671 uint8_t *gem_spaddr; 672 int i; 673 674 /* Promiscuous mode? */ 675 if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) { 676 return GEM_RX_PROMISCUOUS_ACCEPT; 677 } 678 679 if (!memcmp(packet, broadcast_addr, 6)) { 680 /* Reject broadcast packets? */ 681 if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) { 682 return GEM_RX_REJECT; 683 } 684 return GEM_RX_BROADCAST_ACCEPT; 685 } 686 687 /* Accept packets -w- hash match? */ 688 if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) || 689 (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) { 690 unsigned hash_index; 691 692 hash_index = calc_mac_hash(packet); 693 if (hash_index < 32) { 694 if (s->regs[GEM_HASHLO] & (1<<hash_index)) { 695 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 696 GEM_RX_UNICAST_HASH_ACCEPT; 697 } 698 } else { 699 hash_index -= 32; 700 if (s->regs[GEM_HASHHI] & (1<<hash_index)) { 701 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 702 GEM_RX_UNICAST_HASH_ACCEPT; 703 } 704 } 705 } 706 707 /* Check all 4 specific addresses */ 708 gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]); 709 for (i = 3; i >= 0; i--) { 710 if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 711 return GEM_RX_SAR_ACCEPT + i; 712 } 713 } 714 715 /* No address match; reject the packet */ 716 return GEM_RX_REJECT; 717 } 718 719 /* Figure out which queue the received data should be sent to */ 720 static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, 721 unsigned rxbufsize) 722 { 723 uint32_t reg; 724 bool matched, mismatched; 725 int i, j; 726 727 for (i = 0; i < s->num_type1_screeners; i++) { 728 reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i]; 729 matched = false; 730 mismatched = false; 731 732 /* Screening is based on UDP Port */ 733 if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) { 734 uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23]; 735 if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT, 736 GEM_ST1R_UDP_PORT_MATCH_WIDTH)) { 737 matched = true; 738 } else { 739 mismatched = true; 740 } 741 } 742 743 /* Screening is based on DS/TC */ 744 if (reg & GEM_ST1R_DSTC_ENABLE) { 745 uint8_t dscp = rxbuf_ptr[14 + 1]; 746 if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT, 747 GEM_ST1R_DSTC_MATCH_WIDTH)) { 748 matched = true; 749 } else { 750 mismatched = true; 751 } 752 } 753 754 if (matched && !mismatched) { 755 return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH); 756 } 757 } 758 759 for (i = 0; i < s->num_type2_screeners; i++) { 760 reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i]; 761 matched = false; 762 mismatched = false; 763 764 if (reg & GEM_ST2R_ETHERTYPE_ENABLE) { 765 uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; 766 int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT, 767 GEM_ST2R_ETHERTYPE_INDEX_WIDTH); 768 769 if (et_idx > s->num_type2_screeners) { 770 qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " 771 "register index: %d\n", et_idx); 772 } 773 if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 + 774 et_idx]) { 775 matched = true; 776 } else { 777 mismatched = true; 778 } 779 } 780 781 /* Compare A, B, C */ 782 for (j = 0; j < 3; j++) { 783 uint32_t cr0, cr1, mask; 784 uint16_t rx_cmp; 785 int offset; 786 int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6, 787 GEM_ST2R_COMPARE_WIDTH); 788 789 if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) { 790 continue; 791 } 792 if (cr_idx > s->num_type2_screeners) { 793 qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare " 794 "register index: %d\n", cr_idx); 795 } 796 797 cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; 798 cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1]; 799 offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT, 800 GEM_T2CW1_OFFSET_VALUE_WIDTH); 801 802 switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT, 803 GEM_T2CW1_COMPARE_OFFSET_WIDTH)) { 804 case 3: /* Skip UDP header */ 805 qemu_log_mask(LOG_UNIMP, "TCP compare offsets" 806 "unimplemented - assuming UDP\n"); 807 offset += 8; 808 /* Fallthrough */ 809 case 2: /* skip the IP header */ 810 offset += 20; 811 /* Fallthrough */ 812 case 1: /* Count from after the ethertype */ 813 offset += 14; 814 break; 815 case 0: 816 /* Offset from start of frame */ 817 break; 818 } 819 820 rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; 821 mask = extract32(cr0, 0, 16); 822 823 if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) { 824 matched = true; 825 } else { 826 mismatched = true; 827 } 828 } 829 830 if (matched && !mismatched) { 831 return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH); 832 } 833 } 834 835 /* We made it here, assume it's queue 0 */ 836 return 0; 837 } 838 839 static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) 840 { 841 hwaddr desc_addr = 0; 842 843 if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 844 desc_addr = s->regs[tx ? GEM_TBQPH : GEM_RBQPH]; 845 } 846 desc_addr <<= 32; 847 desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; 848 return desc_addr; 849 } 850 851 static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q) 852 { 853 return gem_get_desc_addr(s, true, q); 854 } 855 856 static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q) 857 { 858 return gem_get_desc_addr(s, false, q); 859 } 860 861 static void gem_get_rx_desc(CadenceGEMState *s, int q) 862 { 863 hwaddr desc_addr = gem_get_rx_desc_addr(s, q); 864 865 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr); 866 867 /* read current descriptor */ 868 address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 869 (uint8_t *)s->rx_desc[q], 870 sizeof(uint32_t) * gem_get_desc_len(s, true)); 871 872 /* Descriptor owned by software ? */ 873 if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { 874 DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); 875 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 876 s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]); 877 /* Handle interrupt consequences */ 878 gem_update_int_status(s); 879 } 880 } 881 882 /* 883 * gem_receive: 884 * Fit a packet handed to us by QEMU into the receive descriptor ring. 885 */ 886 static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 887 { 888 CadenceGEMState *s; 889 unsigned rxbufsize, bytes_to_copy; 890 unsigned rxbuf_offset; 891 uint8_t rxbuf[2048]; 892 uint8_t *rxbuf_ptr; 893 bool first_desc = true; 894 int maf; 895 int q = 0; 896 897 s = qemu_get_nic_opaque(nc); 898 899 /* Is this destination MAC address "for us" ? */ 900 maf = gem_mac_address_filter(s, buf); 901 if (maf == GEM_RX_REJECT) { 902 return -1; 903 } 904 905 /* Discard packets with receive length error enabled ? */ 906 if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) { 907 unsigned type_len; 908 909 /* Fish the ethertype / length field out of the RX packet */ 910 type_len = buf[12] << 8 | buf[13]; 911 /* It is a length field, not an ethertype */ 912 if (type_len < 0x600) { 913 if (size < type_len) { 914 /* discard */ 915 return -1; 916 } 917 } 918 } 919 920 /* 921 * Determine configured receive buffer offset (probably 0) 922 */ 923 rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> 924 GEM_NWCFG_BUFF_OFST_S; 925 926 /* The configure size of each receive buffer. Determines how many 927 * buffers needed to hold this packet. 928 */ 929 rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> 930 GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; 931 bytes_to_copy = size; 932 933 /* Hardware allows a zero value here but warns against it. To avoid QEMU 934 * indefinite loops we enforce a minimum value here 935 */ 936 if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) { 937 rxbufsize = GEM_DMACFG_RBUFSZ_MUL; 938 } 939 940 /* Pad to minimum length. Assume FCS field is stripped, logic 941 * below will increment it to the real minimum of 64 when 942 * not FCS stripping 943 */ 944 if (size < 60) { 945 size = 60; 946 } 947 948 /* Strip of FCS field ? (usually yes) */ 949 if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) { 950 rxbuf_ptr = (void *)buf; 951 } else { 952 unsigned crc_val; 953 954 if (size > sizeof(rxbuf) - sizeof(crc_val)) { 955 size = sizeof(rxbuf) - sizeof(crc_val); 956 } 957 bytes_to_copy = size; 958 /* The application wants the FCS field, which QEMU does not provide. 959 * We must try and calculate one. 960 */ 961 962 memcpy(rxbuf, buf, size); 963 memset(rxbuf + size, 0, sizeof(rxbuf) - size); 964 rxbuf_ptr = rxbuf; 965 crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60))); 966 memcpy(rxbuf + size, &crc_val, sizeof(crc_val)); 967 968 bytes_to_copy += 4; 969 size += 4; 970 } 971 972 DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size); 973 974 /* Find which queue we are targeting */ 975 q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); 976 977 while (bytes_to_copy) { 978 hwaddr desc_addr; 979 980 /* Do nothing if receive is not enabled. */ 981 if (!gem_can_receive(nc)) { 982 return -1; 983 } 984 985 DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy, rxbufsize), 986 rx_desc_get_buffer(s->rx_desc[q])); 987 988 /* Copy packet data to emulated DMA buffer */ 989 address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) + 990 rxbuf_offset, 991 MEMTXATTRS_UNSPECIFIED, rxbuf_ptr, 992 MIN(bytes_to_copy, rxbufsize)); 993 rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 994 bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 995 996 /* Update the descriptor. */ 997 if (first_desc) { 998 rx_desc_set_sof(s->rx_desc[q]); 999 first_desc = false; 1000 } 1001 if (bytes_to_copy == 0) { 1002 rx_desc_set_eof(s->rx_desc[q]); 1003 rx_desc_set_length(s->rx_desc[q], size); 1004 } 1005 rx_desc_set_ownership(s->rx_desc[q]); 1006 1007 switch (maf) { 1008 case GEM_RX_PROMISCUOUS_ACCEPT: 1009 break; 1010 case GEM_RX_BROADCAST_ACCEPT: 1011 rx_desc_set_broadcast(s->rx_desc[q]); 1012 break; 1013 case GEM_RX_UNICAST_HASH_ACCEPT: 1014 rx_desc_set_unicast_hash(s->rx_desc[q]); 1015 break; 1016 case GEM_RX_MULTICAST_HASH_ACCEPT: 1017 rx_desc_set_multicast_hash(s->rx_desc[q]); 1018 break; 1019 case GEM_RX_REJECT: 1020 abort(); 1021 default: /* SAR */ 1022 rx_desc_set_sar(s->rx_desc[q], maf); 1023 } 1024 1025 /* Descriptor write-back. */ 1026 desc_addr = gem_get_rx_desc_addr(s, q); 1027 address_space_write(&s->dma_as, desc_addr, 1028 MEMTXATTRS_UNSPECIFIED, 1029 (uint8_t *)s->rx_desc[q], 1030 sizeof(uint32_t) * gem_get_desc_len(s, true)); 1031 1032 /* Next descriptor */ 1033 if (rx_desc_get_wrap(s->rx_desc[q])) { 1034 DB_PRINT("wrapping RX descriptor list\n"); 1035 s->rx_desc_addr[q] = s->regs[GEM_RXQBASE]; 1036 } else { 1037 DB_PRINT("incrementing RX descriptor list\n"); 1038 s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true); 1039 } 1040 1041 gem_get_rx_desc(s, q); 1042 } 1043 1044 /* Count it */ 1045 gem_receive_updatestats(s, buf, size); 1046 1047 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 1048 s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]); 1049 1050 /* Handle interrupt consequences */ 1051 gem_update_int_status(s); 1052 1053 return size; 1054 } 1055 1056 /* 1057 * gem_transmit_updatestats: 1058 * Increment transmit statistics. 1059 */ 1060 static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, 1061 unsigned bytes) 1062 { 1063 uint64_t octets; 1064 1065 /* Total octets (bytes) transmitted */ 1066 octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) | 1067 s->regs[GEM_OCTTXHI]; 1068 octets += bytes; 1069 s->regs[GEM_OCTTXLO] = octets >> 32; 1070 s->regs[GEM_OCTTXHI] = octets; 1071 1072 /* Error-free Frames transmitted */ 1073 s->regs[GEM_TXCNT]++; 1074 1075 /* Error-free Broadcast Frames counter */ 1076 if (!memcmp(packet, broadcast_addr, 6)) { 1077 s->regs[GEM_TXBCNT]++; 1078 } 1079 1080 /* Error-free Multicast Frames counter */ 1081 if (packet[0] == 0x01) { 1082 s->regs[GEM_TXMCNT]++; 1083 } 1084 1085 if (bytes <= 64) { 1086 s->regs[GEM_TX64CNT]++; 1087 } else if (bytes <= 127) { 1088 s->regs[GEM_TX65CNT]++; 1089 } else if (bytes <= 255) { 1090 s->regs[GEM_TX128CNT]++; 1091 } else if (bytes <= 511) { 1092 s->regs[GEM_TX256CNT]++; 1093 } else if (bytes <= 1023) { 1094 s->regs[GEM_TX512CNT]++; 1095 } else if (bytes <= 1518) { 1096 s->regs[GEM_TX1024CNT]++; 1097 } else { 1098 s->regs[GEM_TX1519CNT]++; 1099 } 1100 } 1101 1102 /* 1103 * gem_transmit: 1104 * Fish packets out of the descriptor ring and feed them to QEMU 1105 */ 1106 static void gem_transmit(CadenceGEMState *s) 1107 { 1108 uint32_t desc[DESC_MAX_NUM_WORDS]; 1109 hwaddr packet_desc_addr; 1110 uint8_t tx_packet[2048]; 1111 uint8_t *p; 1112 unsigned total_bytes; 1113 int q = 0; 1114 1115 /* Do nothing if transmit is not enabled. */ 1116 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 1117 return; 1118 } 1119 1120 DB_PRINT("\n"); 1121 1122 /* The packet we will hand off to QEMU. 1123 * Packets scattered across multiple descriptors are gathered to this 1124 * one contiguous buffer first. 1125 */ 1126 p = tx_packet; 1127 total_bytes = 0; 1128 1129 for (q = s->num_priority_queues - 1; q >= 0; q--) { 1130 /* read current descriptor */ 1131 packet_desc_addr = gem_get_tx_desc_addr(s, q); 1132 1133 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 1134 address_space_read(&s->dma_as, packet_desc_addr, 1135 MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, 1136 sizeof(uint32_t) * gem_get_desc_len(s, false)); 1137 /* Handle all descriptors owned by hardware */ 1138 while (tx_desc_get_used(desc) == 0) { 1139 1140 /* Do nothing if transmit is not enabled. */ 1141 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 1142 return; 1143 } 1144 print_gem_tx_desc(desc, q); 1145 1146 /* The real hardware would eat this (and possibly crash). 1147 * For QEMU let's lend a helping hand. 1148 */ 1149 if ((tx_desc_get_buffer(s, desc) == 0) || 1150 (tx_desc_get_length(desc) == 0)) { 1151 DB_PRINT("Invalid TX descriptor @ 0x%x\n", 1152 (unsigned)packet_desc_addr); 1153 break; 1154 } 1155 1156 if (tx_desc_get_length(desc) > sizeof(tx_packet) - 1157 (p - tx_packet)) { 1158 DB_PRINT("TX descriptor @ 0x%x too large: size 0x%x space " \ 1159 "0x%x\n", (unsigned)packet_desc_addr, 1160 (unsigned)tx_desc_get_length(desc), 1161 sizeof(tx_packet) - (p - tx_packet)); 1162 break; 1163 } 1164 1165 /* Gather this fragment of the packet from "dma memory" to our 1166 * contig buffer. 1167 */ 1168 address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc), 1169 MEMTXATTRS_UNSPECIFIED, 1170 p, tx_desc_get_length(desc)); 1171 p += tx_desc_get_length(desc); 1172 total_bytes += tx_desc_get_length(desc); 1173 1174 /* Last descriptor for this packet; hand the whole thing off */ 1175 if (tx_desc_get_last(desc)) { 1176 uint32_t desc_first[DESC_MAX_NUM_WORDS]; 1177 hwaddr desc_addr = gem_get_tx_desc_addr(s, q); 1178 1179 /* Modify the 1st descriptor of this packet to be owned by 1180 * the processor. 1181 */ 1182 address_space_read(&s->dma_as, desc_addr, 1183 MEMTXATTRS_UNSPECIFIED, 1184 (uint8_t *)desc_first, 1185 sizeof(desc_first)); 1186 tx_desc_set_used(desc_first); 1187 address_space_write(&s->dma_as, desc_addr, 1188 MEMTXATTRS_UNSPECIFIED, 1189 (uint8_t *)desc_first, 1190 sizeof(desc_first)); 1191 /* Advance the hardware current descriptor past this packet */ 1192 if (tx_desc_get_wrap(desc)) { 1193 s->tx_desc_addr[q] = s->regs[GEM_TXQBASE]; 1194 } else { 1195 s->tx_desc_addr[q] = packet_desc_addr + 1196 4 * gem_get_desc_len(s, false); 1197 } 1198 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); 1199 1200 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 1201 s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]); 1202 1203 /* Update queue interrupt status */ 1204 if (s->num_priority_queues > 1) { 1205 s->regs[GEM_INT_Q1_STATUS + q] |= 1206 GEM_INT_TXCMPL & ~(s->regs[GEM_INT_Q1_MASK + q]); 1207 } 1208 1209 /* Handle interrupt consequences */ 1210 gem_update_int_status(s); 1211 1212 /* Is checksum offload enabled? */ 1213 if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { 1214 net_checksum_calculate(tx_packet, total_bytes); 1215 } 1216 1217 /* Update MAC statistics */ 1218 gem_transmit_updatestats(s, tx_packet, total_bytes); 1219 1220 /* Send the packet somewhere */ 1221 if (s->phy_loop || (s->regs[GEM_NWCTRL] & 1222 GEM_NWCTRL_LOCALLOOP)) { 1223 gem_receive(qemu_get_queue(s->nic), tx_packet, 1224 total_bytes); 1225 } else { 1226 qemu_send_packet(qemu_get_queue(s->nic), tx_packet, 1227 total_bytes); 1228 } 1229 1230 /* Prepare for next packet */ 1231 p = tx_packet; 1232 total_bytes = 0; 1233 } 1234 1235 /* read next descriptor */ 1236 if (tx_desc_get_wrap(desc)) { 1237 tx_desc_set_last(desc); 1238 packet_desc_addr = s->regs[GEM_TXQBASE]; 1239 } else { 1240 packet_desc_addr += 4 * gem_get_desc_len(s, false); 1241 } 1242 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 1243 address_space_read(&s->dma_as, packet_desc_addr, 1244 MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, 1245 sizeof(uint32_t) * gem_get_desc_len(s, false)); 1246 } 1247 1248 if (tx_desc_get_used(desc)) { 1249 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED; 1250 s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]); 1251 gem_update_int_status(s); 1252 } 1253 } 1254 } 1255 1256 static void gem_phy_reset(CadenceGEMState *s) 1257 { 1258 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 1259 s->phy_regs[PHY_REG_CONTROL] = 0x1140; 1260 s->phy_regs[PHY_REG_STATUS] = 0x7969; 1261 s->phy_regs[PHY_REG_PHYID1] = 0x0141; 1262 s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 1263 s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 1264 s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 1265 s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 1266 s->phy_regs[PHY_REG_NEXTP] = 0x2001; 1267 s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 1268 s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 1269 s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 1270 s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 1271 s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 1272 s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; 1273 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 1274 s->phy_regs[PHY_REG_LED] = 0x4100; 1275 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 1276 s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 1277 1278 phy_update_link(s); 1279 } 1280 1281 static void gem_reset(DeviceState *d) 1282 { 1283 int i; 1284 CadenceGEMState *s = CADENCE_GEM(d); 1285 const uint8_t *a; 1286 uint32_t queues_mask = 0; 1287 1288 DB_PRINT("\n"); 1289 1290 /* Set post reset register values */ 1291 memset(&s->regs[0], 0, sizeof(s->regs)); 1292 s->regs[GEM_NWCFG] = 0x00080000; 1293 s->regs[GEM_NWSTATUS] = 0x00000006; 1294 s->regs[GEM_DMACFG] = 0x00020784; 1295 s->regs[GEM_IMR] = 0x07ffffff; 1296 s->regs[GEM_TXPAUSE] = 0x0000ffff; 1297 s->regs[GEM_TXPARTIALSF] = 0x000003ff; 1298 s->regs[GEM_RXPARTIALSF] = 0x000003ff; 1299 s->regs[GEM_MODID] = s->revision; 1300 s->regs[GEM_DESCONF] = 0x02500111; 1301 s->regs[GEM_DESCONF2] = 0x2ab13fff; 1302 s->regs[GEM_DESCONF5] = 0x002f2045; 1303 s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK; 1304 1305 if (s->num_priority_queues > 1) { 1306 queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); 1307 s->regs[GEM_DESCONF6] |= queues_mask; 1308 } 1309 1310 /* Set MAC address */ 1311 a = &s->conf.macaddr.a[0]; 1312 s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); 1313 s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8); 1314 1315 for (i = 0; i < 4; i++) { 1316 s->sar_active[i] = false; 1317 } 1318 1319 gem_phy_reset(s); 1320 1321 gem_update_int_status(s); 1322 } 1323 1324 static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) 1325 { 1326 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 1327 return s->phy_regs[reg_num]; 1328 } 1329 1330 static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 1331 { 1332 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 1333 1334 switch (reg_num) { 1335 case PHY_REG_CONTROL: 1336 if (val & PHY_REG_CONTROL_RST) { 1337 /* Phy reset */ 1338 gem_phy_reset(s); 1339 val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 1340 s->phy_loop = 0; 1341 } 1342 if (val & PHY_REG_CONTROL_ANEG) { 1343 /* Complete autonegotiation immediately */ 1344 val &= ~PHY_REG_CONTROL_ANEG; 1345 s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 1346 } 1347 if (val & PHY_REG_CONTROL_LOOP) { 1348 DB_PRINT("PHY placed in loopback\n"); 1349 s->phy_loop = 1; 1350 } else { 1351 s->phy_loop = 0; 1352 } 1353 break; 1354 } 1355 s->phy_regs[reg_num] = val; 1356 } 1357 1358 /* 1359 * gem_read32: 1360 * Read a GEM register. 1361 */ 1362 static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 1363 { 1364 CadenceGEMState *s; 1365 uint32_t retval; 1366 s = (CadenceGEMState *)opaque; 1367 1368 offset >>= 2; 1369 retval = s->regs[offset]; 1370 1371 DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 1372 1373 switch (offset) { 1374 case GEM_ISR: 1375 DB_PRINT("lowering irqs on ISR read\n"); 1376 /* The interrupts get updated at the end of the function. */ 1377 break; 1378 case GEM_PHYMNTNC: 1379 if (retval & GEM_PHYMNTNC_OP_R) { 1380 uint32_t phy_addr, reg_num; 1381 1382 phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1383 if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 1384 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1385 retval &= 0xFFFF0000; 1386 retval |= gem_phy_read(s, reg_num); 1387 } else { 1388 retval |= 0xFFFF; /* No device at this address */ 1389 } 1390 } 1391 break; 1392 } 1393 1394 /* Squash read to clear bits */ 1395 s->regs[offset] &= ~(s->regs_rtc[offset]); 1396 1397 /* Do not provide write only bits */ 1398 retval &= ~(s->regs_wo[offset]); 1399 1400 DB_PRINT("0x%08x\n", retval); 1401 gem_update_int_status(s); 1402 return retval; 1403 } 1404 1405 /* 1406 * gem_write32: 1407 * Write a GEM register. 1408 */ 1409 static void gem_write(void *opaque, hwaddr offset, uint64_t val, 1410 unsigned size) 1411 { 1412 CadenceGEMState *s = (CadenceGEMState *)opaque; 1413 uint32_t readonly; 1414 int i; 1415 1416 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 1417 offset >>= 2; 1418 1419 /* Squash bits which are read only in write value */ 1420 val &= ~(s->regs_ro[offset]); 1421 /* Preserve (only) bits which are read only and wtc in register */ 1422 readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 1423 1424 /* Copy register write to backing store */ 1425 s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1426 1427 /* do w1c */ 1428 s->regs[offset] &= ~(s->regs_w1c[offset] & val); 1429 1430 /* Handle register write side effects */ 1431 switch (offset) { 1432 case GEM_NWCTRL: 1433 if (val & GEM_NWCTRL_RXENA) { 1434 for (i = 0; i < s->num_priority_queues; ++i) { 1435 gem_get_rx_desc(s, i); 1436 } 1437 } 1438 if (val & GEM_NWCTRL_TXSTART) { 1439 gem_transmit(s); 1440 } 1441 if (!(val & GEM_NWCTRL_TXENA)) { 1442 /* Reset to start of Q when transmit disabled. */ 1443 for (i = 0; i < s->num_priority_queues; i++) { 1444 s->tx_desc_addr[i] = s->regs[GEM_TXQBASE]; 1445 } 1446 } 1447 if (gem_can_receive(qemu_get_queue(s->nic))) { 1448 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 1449 } 1450 break; 1451 1452 case GEM_TXSTATUS: 1453 gem_update_int_status(s); 1454 break; 1455 case GEM_RXQBASE: 1456 s->rx_desc_addr[0] = val; 1457 break; 1458 case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR: 1459 s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val; 1460 break; 1461 case GEM_TXQBASE: 1462 s->tx_desc_addr[0] = val; 1463 break; 1464 case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR: 1465 s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val; 1466 break; 1467 case GEM_RXSTATUS: 1468 gem_update_int_status(s); 1469 break; 1470 case GEM_IER: 1471 s->regs[GEM_IMR] &= ~val; 1472 gem_update_int_status(s); 1473 break; 1474 case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE: 1475 s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val; 1476 gem_update_int_status(s); 1477 break; 1478 case GEM_IDR: 1479 s->regs[GEM_IMR] |= val; 1480 gem_update_int_status(s); 1481 break; 1482 case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE: 1483 s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val; 1484 gem_update_int_status(s); 1485 break; 1486 case GEM_SPADDR1LO: 1487 case GEM_SPADDR2LO: 1488 case GEM_SPADDR3LO: 1489 case GEM_SPADDR4LO: 1490 s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false; 1491 break; 1492 case GEM_SPADDR1HI: 1493 case GEM_SPADDR2HI: 1494 case GEM_SPADDR3HI: 1495 case GEM_SPADDR4HI: 1496 s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true; 1497 break; 1498 case GEM_PHYMNTNC: 1499 if (val & GEM_PHYMNTNC_OP_W) { 1500 uint32_t phy_addr, reg_num; 1501 1502 phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1503 if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 1504 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1505 gem_phy_write(s, reg_num, val); 1506 } 1507 } 1508 break; 1509 } 1510 1511 DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 1512 } 1513 1514 static const MemoryRegionOps gem_ops = { 1515 .read = gem_read, 1516 .write = gem_write, 1517 .endianness = DEVICE_LITTLE_ENDIAN, 1518 }; 1519 1520 static void gem_set_link(NetClientState *nc) 1521 { 1522 CadenceGEMState *s = qemu_get_nic_opaque(nc); 1523 1524 DB_PRINT("\n"); 1525 phy_update_link(s); 1526 gem_update_int_status(s); 1527 } 1528 1529 static NetClientInfo net_gem_info = { 1530 .type = NET_CLIENT_DRIVER_NIC, 1531 .size = sizeof(NICState), 1532 .can_receive = gem_can_receive, 1533 .receive = gem_receive, 1534 .link_status_changed = gem_set_link, 1535 }; 1536 1537 static void gem_realize(DeviceState *dev, Error **errp) 1538 { 1539 CadenceGEMState *s = CADENCE_GEM(dev); 1540 int i; 1541 1542 address_space_init(&s->dma_as, 1543 s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); 1544 1545 if (s->num_priority_queues == 0 || 1546 s->num_priority_queues > MAX_PRIORITY_QUEUES) { 1547 error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, 1548 s->num_priority_queues); 1549 return; 1550 } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) { 1551 error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8, 1552 s->num_type1_screeners); 1553 return; 1554 } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) { 1555 error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8, 1556 s->num_type2_screeners); 1557 return; 1558 } 1559 1560 for (i = 0; i < s->num_priority_queues; ++i) { 1561 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 1562 } 1563 1564 qemu_macaddr_default_if_unset(&s->conf.macaddr); 1565 1566 s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1567 object_get_typename(OBJECT(dev)), dev->id, s); 1568 } 1569 1570 static void gem_init(Object *obj) 1571 { 1572 CadenceGEMState *s = CADENCE_GEM(obj); 1573 DeviceState *dev = DEVICE(obj); 1574 1575 DB_PRINT("\n"); 1576 1577 gem_init_register_masks(s); 1578 memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1579 "enet", sizeof(s->regs)); 1580 1581 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 1582 1583 object_property_add_link(obj, "dma", TYPE_MEMORY_REGION, 1584 (Object **)&s->dma_mr, 1585 qdev_prop_allow_set_link_before_realize, 1586 OBJ_PROP_LINK_STRONG, 1587 &error_abort); 1588 } 1589 1590 static const VMStateDescription vmstate_cadence_gem = { 1591 .name = "cadence_gem", 1592 .version_id = 4, 1593 .minimum_version_id = 4, 1594 .fields = (VMStateField[]) { 1595 VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), 1596 VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), 1597 VMSTATE_UINT8(phy_loop, CadenceGEMState), 1598 VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState, 1599 MAX_PRIORITY_QUEUES), 1600 VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState, 1601 MAX_PRIORITY_QUEUES), 1602 VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), 1603 VMSTATE_END_OF_LIST(), 1604 } 1605 }; 1606 1607 static Property gem_properties[] = { 1608 DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), 1609 DEFINE_PROP_UINT32("revision", CadenceGEMState, revision, 1610 GEM_MODID_VALUE), 1611 DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, 1612 num_priority_queues, 1), 1613 DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, 1614 num_type1_screeners, 4), 1615 DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState, 1616 num_type2_screeners, 4), 1617 DEFINE_PROP_END_OF_LIST(), 1618 }; 1619 1620 static void gem_class_init(ObjectClass *klass, void *data) 1621 { 1622 DeviceClass *dc = DEVICE_CLASS(klass); 1623 1624 dc->realize = gem_realize; 1625 dc->props = gem_properties; 1626 dc->vmsd = &vmstate_cadence_gem; 1627 dc->reset = gem_reset; 1628 } 1629 1630 static const TypeInfo gem_info = { 1631 .name = TYPE_CADENCE_GEM, 1632 .parent = TYPE_SYS_BUS_DEVICE, 1633 .instance_size = sizeof(CadenceGEMState), 1634 .instance_init = gem_init, 1635 .class_init = gem_class_init, 1636 }; 1637 1638 static void gem_register_types(void) 1639 { 1640 type_register_static(&gem_info); 1641 } 1642 1643 type_init(gem_register_types) 1644