1 /* 2 * Emulation of Allwinner EMAC Fast Ethernet controller and 3 * Realtek RTL8201CP PHY 4 * 5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 6 * 7 * This model is based on reverse-engineering of Linux kernel driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 #include "hw/sysbus.h" 20 #include "net/net.h" 21 #include "qemu/fifo8.h" 22 #include "hw/net/allwinner_emac.h" 23 #include <zlib.h> 24 25 static uint8_t padding[60]; 26 27 static void mii_set_link(RTL8201CPState *mii, bool link_ok) 28 { 29 if (link_ok) { 30 mii->bmsr |= MII_BMSR_LINK_ST | MII_BMSR_AN_COMP; 31 mii->anlpar |= MII_ANAR_TXFD | MII_ANAR_10FD | MII_ANAR_10 | 32 MII_ANAR_CSMACD; 33 } else { 34 mii->bmsr &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); 35 mii->anlpar = MII_ANAR_TX; 36 } 37 } 38 39 static void mii_reset(RTL8201CPState *mii, bool link_ok) 40 { 41 mii->bmcr = MII_BMCR_FD | MII_BMCR_AUTOEN | MII_BMCR_SPEED; 42 mii->bmsr = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD | 43 MII_BMSR_10T_HD | MII_BMSR_MFPS | MII_BMSR_AUTONEG; 44 mii->anar = MII_ANAR_TXFD | MII_ANAR_TX | MII_ANAR_10FD | MII_ANAR_10 | 45 MII_ANAR_CSMACD; 46 mii->anlpar = MII_ANAR_TX; 47 48 mii_set_link(mii, link_ok); 49 } 50 51 static uint16_t RTL8201CP_mdio_read(AwEmacState *s, uint8_t addr, uint8_t reg) 52 { 53 RTL8201CPState *mii = &s->mii; 54 uint16_t ret = 0xffff; 55 56 if (addr == s->phy_addr) { 57 switch (reg) { 58 case MII_BMCR: 59 return mii->bmcr; 60 case MII_BMSR: 61 return mii->bmsr; 62 case MII_PHYID1: 63 return RTL8201CP_PHYID1; 64 case MII_PHYID2: 65 return RTL8201CP_PHYID2; 66 case MII_ANAR: 67 return mii->anar; 68 case MII_ANLPAR: 69 return mii->anlpar; 70 case MII_ANER: 71 case MII_NSR: 72 case MII_LBREMR: 73 case MII_REC: 74 case MII_SNRDR: 75 case MII_TEST: 76 qemu_log_mask(LOG_UNIMP, 77 "allwinner_emac: read from unimpl. mii reg 0x%x\n", 78 reg); 79 return 0; 80 default: 81 qemu_log_mask(LOG_GUEST_ERROR, 82 "allwinner_emac: read from invalid mii reg 0x%x\n", 83 reg); 84 return 0; 85 } 86 } 87 return ret; 88 } 89 90 static void RTL8201CP_mdio_write(AwEmacState *s, uint8_t addr, uint8_t reg, 91 uint16_t value) 92 { 93 RTL8201CPState *mii = &s->mii; 94 NetClientState *nc; 95 96 if (addr == s->phy_addr) { 97 switch (reg) { 98 case MII_BMCR: 99 if (value & MII_BMCR_RESET) { 100 nc = qemu_get_queue(s->nic); 101 mii_reset(mii, !nc->link_down); 102 } else { 103 mii->bmcr = value; 104 } 105 break; 106 case MII_ANAR: 107 mii->anar = value; 108 break; 109 case MII_BMSR: 110 case MII_PHYID1: 111 case MII_PHYID2: 112 case MII_ANLPAR: 113 case MII_ANER: 114 qemu_log_mask(LOG_GUEST_ERROR, 115 "allwinner_emac: write to read-only mii reg 0x%x\n", 116 reg); 117 break; 118 case MII_NSR: 119 case MII_LBREMR: 120 case MII_REC: 121 case MII_SNRDR: 122 case MII_TEST: 123 qemu_log_mask(LOG_UNIMP, 124 "allwinner_emac: write to unimpl. mii reg 0x%x\n", 125 reg); 126 break; 127 default: 128 qemu_log_mask(LOG_GUEST_ERROR, 129 "allwinner_emac: write to invalid mii reg 0x%x\n", 130 reg); 131 } 132 } 133 } 134 135 static void aw_emac_update_irq(AwEmacState *s) 136 { 137 qemu_set_irq(s->irq, (s->int_sta & s->int_ctl) != 0); 138 } 139 140 static void aw_emac_tx_reset(AwEmacState *s, int chan) 141 { 142 fifo8_reset(&s->tx_fifo[chan]); 143 s->tx_length[chan] = 0; 144 } 145 146 static void aw_emac_rx_reset(AwEmacState *s) 147 { 148 fifo8_reset(&s->rx_fifo); 149 s->rx_num_packets = 0; 150 s->rx_packet_size = 0; 151 s->rx_packet_pos = 0; 152 } 153 154 static void fifo8_push_word(Fifo8 *fifo, uint32_t val) 155 { 156 fifo8_push(fifo, val); 157 fifo8_push(fifo, val >> 8); 158 fifo8_push(fifo, val >> 16); 159 fifo8_push(fifo, val >> 24); 160 } 161 162 static uint32_t fifo8_pop_word(Fifo8 *fifo) 163 { 164 uint32_t ret; 165 166 ret = fifo8_pop(fifo); 167 ret |= fifo8_pop(fifo) << 8; 168 ret |= fifo8_pop(fifo) << 16; 169 ret |= fifo8_pop(fifo) << 24; 170 171 return ret; 172 } 173 174 static int aw_emac_can_receive(NetClientState *nc) 175 { 176 AwEmacState *s = qemu_get_nic_opaque(nc); 177 178 /* 179 * To avoid packet drops, allow reception only when there is space 180 * for a full frame: 1522 + 8 (rx headers) + 2 (padding). 181 */ 182 return (s->ctl & EMAC_CTL_RX_EN) && (fifo8_num_free(&s->rx_fifo) >= 1532); 183 } 184 185 static ssize_t aw_emac_receive(NetClientState *nc, const uint8_t *buf, 186 size_t size) 187 { 188 AwEmacState *s = qemu_get_nic_opaque(nc); 189 Fifo8 *fifo = &s->rx_fifo; 190 size_t padded_size, total_size; 191 uint32_t crc; 192 193 padded_size = size > 60 ? size : 60; 194 total_size = QEMU_ALIGN_UP(RX_HDR_SIZE + padded_size + CRC_SIZE, 4); 195 196 if (!(s->ctl & EMAC_CTL_RX_EN) || (fifo8_num_free(fifo) < total_size)) { 197 return -1; 198 } 199 200 fifo8_push_word(fifo, EMAC_UNDOCUMENTED_MAGIC); 201 fifo8_push_word(fifo, EMAC_RX_HEADER(padded_size + CRC_SIZE, 202 EMAC_RX_IO_DATA_STATUS_OK)); 203 fifo8_push_all(fifo, buf, size); 204 crc = crc32(~0, buf, size); 205 206 if (padded_size != size) { 207 fifo8_push_all(fifo, padding, padded_size - size); 208 crc = crc32(crc, padding, padded_size - size); 209 } 210 211 fifo8_push_word(fifo, crc); 212 fifo8_push_all(fifo, padding, QEMU_ALIGN_UP(padded_size, 4) - padded_size); 213 s->rx_num_packets++; 214 215 s->int_sta |= EMAC_INT_RX; 216 aw_emac_update_irq(s); 217 218 return size; 219 } 220 221 static void aw_emac_cleanup(NetClientState *nc) 222 { 223 AwEmacState *s = qemu_get_nic_opaque(nc); 224 225 s->nic = NULL; 226 } 227 228 static void aw_emac_reset(DeviceState *dev) 229 { 230 AwEmacState *s = AW_EMAC(dev); 231 NetClientState *nc = qemu_get_queue(s->nic); 232 233 s->ctl = 0; 234 s->tx_mode = 0; 235 s->int_ctl = 0; 236 s->int_sta = 0; 237 s->tx_channel = 0; 238 s->phy_target = 0; 239 240 aw_emac_tx_reset(s, 0); 241 aw_emac_tx_reset(s, 1); 242 aw_emac_rx_reset(s); 243 244 mii_reset(&s->mii, !nc->link_down); 245 } 246 247 static uint64_t aw_emac_read(void *opaque, hwaddr offset, unsigned size) 248 { 249 AwEmacState *s = opaque; 250 Fifo8 *fifo = &s->rx_fifo; 251 NetClientState *nc; 252 uint64_t ret; 253 254 switch (offset) { 255 case EMAC_CTL_REG: 256 return s->ctl; 257 case EMAC_TX_MODE_REG: 258 return s->tx_mode; 259 case EMAC_TX_INS_REG: 260 return s->tx_channel; 261 case EMAC_RX_CTL_REG: 262 return s->rx_ctl; 263 case EMAC_RX_IO_DATA_REG: 264 if (!s->rx_num_packets) { 265 qemu_log_mask(LOG_GUEST_ERROR, 266 "Read IO data register when no packet available"); 267 return 0; 268 } 269 270 ret = fifo8_pop_word(fifo); 271 272 switch (s->rx_packet_pos) { 273 case 0: /* Word is magic header */ 274 s->rx_packet_pos += 4; 275 break; 276 case 4: /* Word is rx info header */ 277 s->rx_packet_pos += 4; 278 s->rx_packet_size = QEMU_ALIGN_UP(extract32(ret, 0, 16), 4); 279 break; 280 default: /* Word is packet data */ 281 s->rx_packet_pos += 4; 282 s->rx_packet_size -= 4; 283 284 if (!s->rx_packet_size) { 285 s->rx_packet_pos = 0; 286 s->rx_num_packets--; 287 nc = qemu_get_queue(s->nic); 288 if (aw_emac_can_receive(nc)) { 289 qemu_flush_queued_packets(nc); 290 } 291 } 292 } 293 return ret; 294 case EMAC_RX_FBC_REG: 295 return s->rx_num_packets; 296 case EMAC_INT_CTL_REG: 297 return s->int_ctl; 298 case EMAC_INT_STA_REG: 299 return s->int_sta; 300 case EMAC_MAC_MRDD_REG: 301 return RTL8201CP_mdio_read(s, 302 extract32(s->phy_target, PHY_ADDR_SHIFT, 8), 303 extract32(s->phy_target, PHY_REG_SHIFT, 8)); 304 default: 305 qemu_log_mask(LOG_UNIMP, 306 "allwinner_emac: read access to unknown register 0x" 307 TARGET_FMT_plx "\n", offset); 308 ret = 0; 309 } 310 311 return ret; 312 } 313 314 static void aw_emac_write(void *opaque, hwaddr offset, uint64_t value, 315 unsigned size) 316 { 317 AwEmacState *s = opaque; 318 Fifo8 *fifo; 319 NetClientState *nc = qemu_get_queue(s->nic); 320 int chan; 321 322 switch (offset) { 323 case EMAC_CTL_REG: 324 if (value & EMAC_CTL_RESET) { 325 aw_emac_reset(DEVICE(s)); 326 value &= ~EMAC_CTL_RESET; 327 } 328 s->ctl = value; 329 if (aw_emac_can_receive(nc)) { 330 qemu_flush_queued_packets(nc); 331 } 332 break; 333 case EMAC_TX_MODE_REG: 334 s->tx_mode = value; 335 break; 336 case EMAC_TX_CTL0_REG: 337 case EMAC_TX_CTL1_REG: 338 chan = (offset == EMAC_TX_CTL0_REG ? 0 : 1); 339 if ((value & 1) && (s->ctl & EMAC_CTL_TX_EN)) { 340 uint32_t len, ret; 341 const uint8_t *data; 342 343 fifo = &s->tx_fifo[chan]; 344 len = s->tx_length[chan]; 345 346 if (len > fifo8_num_used(fifo)) { 347 len = fifo8_num_used(fifo); 348 qemu_log_mask(LOG_GUEST_ERROR, 349 "allwinner_emac: TX length > fifo data length\n"); 350 } 351 if (len > 0) { 352 data = fifo8_pop_buf(fifo, len, &ret); 353 qemu_send_packet(nc, data, ret); 354 aw_emac_tx_reset(s, chan); 355 /* Raise TX interrupt */ 356 s->int_sta |= EMAC_INT_TX_CHAN(chan); 357 aw_emac_update_irq(s); 358 } 359 } 360 break; 361 case EMAC_TX_INS_REG: 362 s->tx_channel = value < NUM_TX_FIFOS ? value : 0; 363 break; 364 case EMAC_TX_PL0_REG: 365 case EMAC_TX_PL1_REG: 366 chan = (offset == EMAC_TX_PL0_REG ? 0 : 1); 367 if (value > TX_FIFO_SIZE) { 368 qemu_log_mask(LOG_GUEST_ERROR, 369 "allwinner_emac: invalid TX frame length %d\n", 370 (int)value); 371 value = TX_FIFO_SIZE; 372 } 373 s->tx_length[chan] = value; 374 break; 375 case EMAC_TX_IO_DATA_REG: 376 fifo = &s->tx_fifo[s->tx_channel]; 377 if (fifo8_num_free(fifo) < 4) { 378 qemu_log_mask(LOG_GUEST_ERROR, 379 "allwinner_emac: TX data overruns fifo\n"); 380 break; 381 } 382 fifo8_push_word(fifo, value); 383 break; 384 case EMAC_RX_CTL_REG: 385 s->rx_ctl = value; 386 break; 387 case EMAC_RX_FBC_REG: 388 if (value == 0) { 389 aw_emac_rx_reset(s); 390 } 391 break; 392 case EMAC_INT_CTL_REG: 393 s->int_ctl = value; 394 aw_emac_update_irq(s); 395 break; 396 case EMAC_INT_STA_REG: 397 s->int_sta &= ~value; 398 aw_emac_update_irq(s); 399 break; 400 case EMAC_MAC_MADR_REG: 401 s->phy_target = value; 402 break; 403 case EMAC_MAC_MWTD_REG: 404 RTL8201CP_mdio_write(s, extract32(s->phy_target, PHY_ADDR_SHIFT, 8), 405 extract32(s->phy_target, PHY_REG_SHIFT, 8), value); 406 break; 407 default: 408 qemu_log_mask(LOG_UNIMP, 409 "allwinner_emac: write access to unknown register 0x" 410 TARGET_FMT_plx "\n", offset); 411 } 412 } 413 414 static void aw_emac_set_link(NetClientState *nc) 415 { 416 AwEmacState *s = qemu_get_nic_opaque(nc); 417 418 mii_set_link(&s->mii, !nc->link_down); 419 } 420 421 static const MemoryRegionOps aw_emac_mem_ops = { 422 .read = aw_emac_read, 423 .write = aw_emac_write, 424 .endianness = DEVICE_NATIVE_ENDIAN, 425 .valid = { 426 .min_access_size = 4, 427 .max_access_size = 4, 428 }, 429 }; 430 431 static NetClientInfo net_aw_emac_info = { 432 .type = NET_CLIENT_OPTIONS_KIND_NIC, 433 .size = sizeof(NICState), 434 .can_receive = aw_emac_can_receive, 435 .receive = aw_emac_receive, 436 .cleanup = aw_emac_cleanup, 437 .link_status_changed = aw_emac_set_link, 438 }; 439 440 static void aw_emac_init(Object *obj) 441 { 442 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 443 AwEmacState *s = AW_EMAC(obj); 444 445 memory_region_init_io(&s->iomem, OBJECT(s), &aw_emac_mem_ops, s, 446 "aw_emac", 0x1000); 447 sysbus_init_mmio(sbd, &s->iomem); 448 sysbus_init_irq(sbd, &s->irq); 449 } 450 451 static void aw_emac_realize(DeviceState *dev, Error **errp) 452 { 453 AwEmacState *s = AW_EMAC(dev); 454 455 qemu_macaddr_default_if_unset(&s->conf.macaddr); 456 s->nic = qemu_new_nic(&net_aw_emac_info, &s->conf, 457 object_get_typename(OBJECT(dev)), dev->id, s); 458 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 459 460 fifo8_create(&s->rx_fifo, RX_FIFO_SIZE); 461 fifo8_create(&s->tx_fifo[0], TX_FIFO_SIZE); 462 fifo8_create(&s->tx_fifo[1], TX_FIFO_SIZE); 463 } 464 465 static Property aw_emac_properties[] = { 466 DEFINE_NIC_PROPERTIES(AwEmacState, conf), 467 DEFINE_PROP_UINT8("phy-addr", AwEmacState, phy_addr, 0), 468 DEFINE_PROP_END_OF_LIST(), 469 }; 470 471 static const VMStateDescription vmstate_mii = { 472 .name = "rtl8201cp", 473 .version_id = 1, 474 .minimum_version_id = 1, 475 .fields = (VMStateField[]) { 476 VMSTATE_UINT16(bmcr, RTL8201CPState), 477 VMSTATE_UINT16(bmsr, RTL8201CPState), 478 VMSTATE_UINT16(anar, RTL8201CPState), 479 VMSTATE_UINT16(anlpar, RTL8201CPState), 480 VMSTATE_END_OF_LIST() 481 } 482 }; 483 484 static int aw_emac_post_load(void *opaque, int version_id) 485 { 486 AwEmacState *s = opaque; 487 488 aw_emac_set_link(qemu_get_queue(s->nic)); 489 490 return 0; 491 } 492 493 static const VMStateDescription vmstate_aw_emac = { 494 .name = "allwinner_emac", 495 .version_id = 1, 496 .minimum_version_id = 1, 497 .post_load = aw_emac_post_load, 498 .fields = (VMStateField[]) { 499 VMSTATE_STRUCT(mii, AwEmacState, 1, vmstate_mii, RTL8201CPState), 500 VMSTATE_UINT32(ctl, AwEmacState), 501 VMSTATE_UINT32(tx_mode, AwEmacState), 502 VMSTATE_UINT32(rx_ctl, AwEmacState), 503 VMSTATE_UINT32(int_ctl, AwEmacState), 504 VMSTATE_UINT32(int_sta, AwEmacState), 505 VMSTATE_UINT32(phy_target, AwEmacState), 506 VMSTATE_FIFO8(rx_fifo, AwEmacState), 507 VMSTATE_UINT32(rx_num_packets, AwEmacState), 508 VMSTATE_UINT32(rx_packet_size, AwEmacState), 509 VMSTATE_UINT32(rx_packet_pos, AwEmacState), 510 VMSTATE_STRUCT_ARRAY(tx_fifo, AwEmacState, NUM_TX_FIFOS, 1, 511 vmstate_fifo8, Fifo8), 512 VMSTATE_UINT32_ARRAY(tx_length, AwEmacState, NUM_TX_FIFOS), 513 VMSTATE_UINT32(tx_channel, AwEmacState), 514 VMSTATE_END_OF_LIST() 515 } 516 }; 517 518 static void aw_emac_class_init(ObjectClass *klass, void *data) 519 { 520 DeviceClass *dc = DEVICE_CLASS(klass); 521 522 dc->realize = aw_emac_realize; 523 dc->props = aw_emac_properties; 524 dc->reset = aw_emac_reset; 525 dc->vmsd = &vmstate_aw_emac; 526 } 527 528 static const TypeInfo aw_emac_info = { 529 .name = TYPE_AW_EMAC, 530 .parent = TYPE_SYS_BUS_DEVICE, 531 .instance_size = sizeof(AwEmacState), 532 .instance_init = aw_emac_init, 533 .class_init = aw_emac_class_init, 534 }; 535 536 static void aw_emac_register_types(void) 537 { 538 type_register_static(&aw_emac_info); 539 } 540 541 type_init(aw_emac_register_types) 542