1 /* 2 * Emulation of Allwinner EMAC Fast Ethernet controller and 3 * Realtek RTL8201CP PHY 4 * 5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 6 * 7 * This model is based on reverse-engineering of Linux kernel driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 #include "hw/sysbus.h" 20 #include "net/net.h" 21 #include "qemu/fifo8.h" 22 #include "hw/net/allwinner_emac.h" 23 #include <zlib.h> 24 25 static uint8_t padding[60]; 26 27 static void mii_set_link(RTL8201CPState *mii, bool link_ok) 28 { 29 if (link_ok) { 30 mii->bmsr |= MII_BMSR_LINK_ST | MII_BMSR_AN_COMP; 31 mii->anlpar |= MII_ANAR_TXFD | MII_ANAR_10FD | MII_ANAR_10 | 32 MII_ANAR_CSMACD; 33 } else { 34 mii->bmsr &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); 35 mii->anlpar = MII_ANAR_TX; 36 } 37 } 38 39 static void mii_reset(RTL8201CPState *mii, bool link_ok) 40 { 41 mii->bmcr = MII_BMCR_FD | MII_BMCR_AUTOEN | MII_BMCR_SPEED; 42 mii->bmsr = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD | 43 MII_BMSR_10T_HD | MII_BMSR_MFPS | MII_BMSR_AUTONEG; 44 mii->anar = MII_ANAR_TXFD | MII_ANAR_TX | MII_ANAR_10FD | MII_ANAR_10 | 45 MII_ANAR_CSMACD; 46 mii->anlpar = MII_ANAR_TX; 47 48 mii_set_link(mii, link_ok); 49 } 50 51 static uint16_t RTL8201CP_mdio_read(AwEmacState *s, uint8_t addr, uint8_t reg) 52 { 53 RTL8201CPState *mii = &s->mii; 54 uint16_t ret = 0xffff; 55 56 if (addr == s->phy_addr) { 57 switch (reg) { 58 case MII_BMCR: 59 return mii->bmcr; 60 case MII_BMSR: 61 return mii->bmsr; 62 case MII_PHYID1: 63 return RTL8201CP_PHYID1; 64 case MII_PHYID2: 65 return RTL8201CP_PHYID2; 66 case MII_ANAR: 67 return mii->anar; 68 case MII_ANLPAR: 69 return mii->anlpar; 70 case MII_ANER: 71 case MII_NSR: 72 case MII_LBREMR: 73 case MII_REC: 74 case MII_SNRDR: 75 case MII_TEST: 76 qemu_log_mask(LOG_UNIMP, 77 "allwinner_emac: read from unimpl. mii reg 0x%x\n", 78 reg); 79 return 0; 80 default: 81 qemu_log_mask(LOG_GUEST_ERROR, 82 "allwinner_emac: read from invalid mii reg 0x%x\n", 83 reg); 84 return 0; 85 } 86 } 87 return ret; 88 } 89 90 static void RTL8201CP_mdio_write(AwEmacState *s, uint8_t addr, uint8_t reg, 91 uint16_t value) 92 { 93 RTL8201CPState *mii = &s->mii; 94 NetClientState *nc; 95 96 if (addr == s->phy_addr) { 97 switch (reg) { 98 case MII_BMCR: 99 if (value & MII_BMCR_RESET) { 100 nc = qemu_get_queue(s->nic); 101 mii_reset(mii, !nc->link_down); 102 } else { 103 mii->bmcr = value; 104 } 105 break; 106 case MII_ANAR: 107 mii->anar = value; 108 break; 109 case MII_BMSR: 110 case MII_PHYID1: 111 case MII_PHYID2: 112 case MII_ANLPAR: 113 case MII_ANER: 114 qemu_log_mask(LOG_GUEST_ERROR, 115 "allwinner_emac: write to read-only mii reg 0x%x\n", 116 reg); 117 break; 118 case MII_NSR: 119 case MII_LBREMR: 120 case MII_REC: 121 case MII_SNRDR: 122 case MII_TEST: 123 qemu_log_mask(LOG_UNIMP, 124 "allwinner_emac: write to unimpl. mii reg 0x%x\n", 125 reg); 126 break; 127 default: 128 qemu_log_mask(LOG_GUEST_ERROR, 129 "allwinner_emac: write to invalid mii reg 0x%x\n", 130 reg); 131 } 132 } 133 } 134 135 static void aw_emac_update_irq(AwEmacState *s) 136 { 137 qemu_set_irq(s->irq, (s->int_sta & s->int_ctl) != 0); 138 } 139 140 static void aw_emac_tx_reset(AwEmacState *s, int chan) 141 { 142 fifo8_reset(&s->tx_fifo[chan]); 143 s->tx_length[chan] = 0; 144 } 145 146 static void aw_emac_rx_reset(AwEmacState *s) 147 { 148 fifo8_reset(&s->rx_fifo); 149 s->rx_num_packets = 0; 150 s->rx_packet_size = 0; 151 s->rx_packet_pos = 0; 152 } 153 154 static void fifo8_push_word(Fifo8 *fifo, uint32_t val) 155 { 156 fifo8_push(fifo, val); 157 fifo8_push(fifo, val >> 8); 158 fifo8_push(fifo, val >> 16); 159 fifo8_push(fifo, val >> 24); 160 } 161 162 static uint32_t fifo8_pop_word(Fifo8 *fifo) 163 { 164 uint32_t ret; 165 166 ret = fifo8_pop(fifo); 167 ret |= fifo8_pop(fifo) << 8; 168 ret |= fifo8_pop(fifo) << 16; 169 ret |= fifo8_pop(fifo) << 24; 170 171 return ret; 172 } 173 174 static int aw_emac_can_receive(NetClientState *nc) 175 { 176 AwEmacState *s = qemu_get_nic_opaque(nc); 177 178 /* 179 * To avoid packet drops, allow reception only when there is space 180 * for a full frame: 1522 + 8 (rx headers) + 2 (padding). 181 */ 182 return (s->ctl & EMAC_CTL_RX_EN) && (fifo8_num_free(&s->rx_fifo) >= 1532); 183 } 184 185 static ssize_t aw_emac_receive(NetClientState *nc, const uint8_t *buf, 186 size_t size) 187 { 188 AwEmacState *s = qemu_get_nic_opaque(nc); 189 Fifo8 *fifo = &s->rx_fifo; 190 size_t padded_size, total_size; 191 uint32_t crc; 192 193 padded_size = size > 60 ? size : 60; 194 total_size = QEMU_ALIGN_UP(RX_HDR_SIZE + padded_size + CRC_SIZE, 4); 195 196 if (!(s->ctl & EMAC_CTL_RX_EN) || (fifo8_num_free(fifo) < total_size)) { 197 return -1; 198 } 199 200 fifo8_push_word(fifo, EMAC_UNDOCUMENTED_MAGIC); 201 fifo8_push_word(fifo, EMAC_RX_HEADER(padded_size + CRC_SIZE, 202 EMAC_RX_IO_DATA_STATUS_OK)); 203 fifo8_push_all(fifo, buf, size); 204 crc = crc32(~0, buf, size); 205 206 if (padded_size != size) { 207 fifo8_push_all(fifo, padding, padded_size - size); 208 crc = crc32(crc, padding, padded_size - size); 209 } 210 211 fifo8_push_word(fifo, crc); 212 fifo8_push_all(fifo, padding, QEMU_ALIGN_UP(padded_size, 4) - padded_size); 213 s->rx_num_packets++; 214 215 s->int_sta |= EMAC_INT_RX; 216 aw_emac_update_irq(s); 217 218 return size; 219 } 220 221 static void aw_emac_reset(DeviceState *dev) 222 { 223 AwEmacState *s = AW_EMAC(dev); 224 NetClientState *nc = qemu_get_queue(s->nic); 225 226 s->ctl = 0; 227 s->tx_mode = 0; 228 s->int_ctl = 0; 229 s->int_sta = 0; 230 s->tx_channel = 0; 231 s->phy_target = 0; 232 233 aw_emac_tx_reset(s, 0); 234 aw_emac_tx_reset(s, 1); 235 aw_emac_rx_reset(s); 236 237 mii_reset(&s->mii, !nc->link_down); 238 } 239 240 static uint64_t aw_emac_read(void *opaque, hwaddr offset, unsigned size) 241 { 242 AwEmacState *s = opaque; 243 Fifo8 *fifo = &s->rx_fifo; 244 NetClientState *nc; 245 uint64_t ret; 246 247 switch (offset) { 248 case EMAC_CTL_REG: 249 return s->ctl; 250 case EMAC_TX_MODE_REG: 251 return s->tx_mode; 252 case EMAC_TX_INS_REG: 253 return s->tx_channel; 254 case EMAC_RX_CTL_REG: 255 return s->rx_ctl; 256 case EMAC_RX_IO_DATA_REG: 257 if (!s->rx_num_packets) { 258 qemu_log_mask(LOG_GUEST_ERROR, 259 "Read IO data register when no packet available"); 260 return 0; 261 } 262 263 ret = fifo8_pop_word(fifo); 264 265 switch (s->rx_packet_pos) { 266 case 0: /* Word is magic header */ 267 s->rx_packet_pos += 4; 268 break; 269 case 4: /* Word is rx info header */ 270 s->rx_packet_pos += 4; 271 s->rx_packet_size = QEMU_ALIGN_UP(extract32(ret, 0, 16), 4); 272 break; 273 default: /* Word is packet data */ 274 s->rx_packet_pos += 4; 275 s->rx_packet_size -= 4; 276 277 if (!s->rx_packet_size) { 278 s->rx_packet_pos = 0; 279 s->rx_num_packets--; 280 nc = qemu_get_queue(s->nic); 281 if (aw_emac_can_receive(nc)) { 282 qemu_flush_queued_packets(nc); 283 } 284 } 285 } 286 return ret; 287 case EMAC_RX_FBC_REG: 288 return s->rx_num_packets; 289 case EMAC_INT_CTL_REG: 290 return s->int_ctl; 291 case EMAC_INT_STA_REG: 292 return s->int_sta; 293 case EMAC_MAC_MRDD_REG: 294 return RTL8201CP_mdio_read(s, 295 extract32(s->phy_target, PHY_ADDR_SHIFT, 8), 296 extract32(s->phy_target, PHY_REG_SHIFT, 8)); 297 default: 298 qemu_log_mask(LOG_UNIMP, 299 "allwinner_emac: read access to unknown register 0x" 300 TARGET_FMT_plx "\n", offset); 301 ret = 0; 302 } 303 304 return ret; 305 } 306 307 static void aw_emac_write(void *opaque, hwaddr offset, uint64_t value, 308 unsigned size) 309 { 310 AwEmacState *s = opaque; 311 Fifo8 *fifo; 312 NetClientState *nc = qemu_get_queue(s->nic); 313 int chan; 314 315 switch (offset) { 316 case EMAC_CTL_REG: 317 if (value & EMAC_CTL_RESET) { 318 aw_emac_reset(DEVICE(s)); 319 value &= ~EMAC_CTL_RESET; 320 } 321 s->ctl = value; 322 if (aw_emac_can_receive(nc)) { 323 qemu_flush_queued_packets(nc); 324 } 325 break; 326 case EMAC_TX_MODE_REG: 327 s->tx_mode = value; 328 break; 329 case EMAC_TX_CTL0_REG: 330 case EMAC_TX_CTL1_REG: 331 chan = (offset == EMAC_TX_CTL0_REG ? 0 : 1); 332 if ((value & 1) && (s->ctl & EMAC_CTL_TX_EN)) { 333 uint32_t len, ret; 334 const uint8_t *data; 335 336 fifo = &s->tx_fifo[chan]; 337 len = s->tx_length[chan]; 338 339 if (len > fifo8_num_used(fifo)) { 340 len = fifo8_num_used(fifo); 341 qemu_log_mask(LOG_GUEST_ERROR, 342 "allwinner_emac: TX length > fifo data length\n"); 343 } 344 if (len > 0) { 345 data = fifo8_pop_buf(fifo, len, &ret); 346 qemu_send_packet(nc, data, ret); 347 aw_emac_tx_reset(s, chan); 348 /* Raise TX interrupt */ 349 s->int_sta |= EMAC_INT_TX_CHAN(chan); 350 aw_emac_update_irq(s); 351 } 352 } 353 break; 354 case EMAC_TX_INS_REG: 355 s->tx_channel = value < NUM_TX_FIFOS ? value : 0; 356 break; 357 case EMAC_TX_PL0_REG: 358 case EMAC_TX_PL1_REG: 359 chan = (offset == EMAC_TX_PL0_REG ? 0 : 1); 360 if (value > TX_FIFO_SIZE) { 361 qemu_log_mask(LOG_GUEST_ERROR, 362 "allwinner_emac: invalid TX frame length %d\n", 363 (int)value); 364 value = TX_FIFO_SIZE; 365 } 366 s->tx_length[chan] = value; 367 break; 368 case EMAC_TX_IO_DATA_REG: 369 fifo = &s->tx_fifo[s->tx_channel]; 370 if (fifo8_num_free(fifo) < 4) { 371 qemu_log_mask(LOG_GUEST_ERROR, 372 "allwinner_emac: TX data overruns fifo\n"); 373 break; 374 } 375 fifo8_push_word(fifo, value); 376 break; 377 case EMAC_RX_CTL_REG: 378 s->rx_ctl = value; 379 break; 380 case EMAC_RX_FBC_REG: 381 if (value == 0) { 382 aw_emac_rx_reset(s); 383 } 384 break; 385 case EMAC_INT_CTL_REG: 386 s->int_ctl = value; 387 aw_emac_update_irq(s); 388 break; 389 case EMAC_INT_STA_REG: 390 s->int_sta &= ~value; 391 aw_emac_update_irq(s); 392 break; 393 case EMAC_MAC_MADR_REG: 394 s->phy_target = value; 395 break; 396 case EMAC_MAC_MWTD_REG: 397 RTL8201CP_mdio_write(s, extract32(s->phy_target, PHY_ADDR_SHIFT, 8), 398 extract32(s->phy_target, PHY_REG_SHIFT, 8), value); 399 break; 400 default: 401 qemu_log_mask(LOG_UNIMP, 402 "allwinner_emac: write access to unknown register 0x" 403 TARGET_FMT_plx "\n", offset); 404 } 405 } 406 407 static void aw_emac_set_link(NetClientState *nc) 408 { 409 AwEmacState *s = qemu_get_nic_opaque(nc); 410 411 mii_set_link(&s->mii, !nc->link_down); 412 } 413 414 static const MemoryRegionOps aw_emac_mem_ops = { 415 .read = aw_emac_read, 416 .write = aw_emac_write, 417 .endianness = DEVICE_NATIVE_ENDIAN, 418 .valid = { 419 .min_access_size = 4, 420 .max_access_size = 4, 421 }, 422 }; 423 424 static NetClientInfo net_aw_emac_info = { 425 .type = NET_CLIENT_OPTIONS_KIND_NIC, 426 .size = sizeof(NICState), 427 .can_receive = aw_emac_can_receive, 428 .receive = aw_emac_receive, 429 .link_status_changed = aw_emac_set_link, 430 }; 431 432 static void aw_emac_init(Object *obj) 433 { 434 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 435 AwEmacState *s = AW_EMAC(obj); 436 437 memory_region_init_io(&s->iomem, OBJECT(s), &aw_emac_mem_ops, s, 438 "aw_emac", 0x1000); 439 sysbus_init_mmio(sbd, &s->iomem); 440 sysbus_init_irq(sbd, &s->irq); 441 } 442 443 static void aw_emac_realize(DeviceState *dev, Error **errp) 444 { 445 AwEmacState *s = AW_EMAC(dev); 446 447 qemu_macaddr_default_if_unset(&s->conf.macaddr); 448 s->nic = qemu_new_nic(&net_aw_emac_info, &s->conf, 449 object_get_typename(OBJECT(dev)), dev->id, s); 450 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 451 452 fifo8_create(&s->rx_fifo, RX_FIFO_SIZE); 453 fifo8_create(&s->tx_fifo[0], TX_FIFO_SIZE); 454 fifo8_create(&s->tx_fifo[1], TX_FIFO_SIZE); 455 } 456 457 static Property aw_emac_properties[] = { 458 DEFINE_NIC_PROPERTIES(AwEmacState, conf), 459 DEFINE_PROP_UINT8("phy-addr", AwEmacState, phy_addr, 0), 460 DEFINE_PROP_END_OF_LIST(), 461 }; 462 463 static const VMStateDescription vmstate_mii = { 464 .name = "rtl8201cp", 465 .version_id = 1, 466 .minimum_version_id = 1, 467 .fields = (VMStateField[]) { 468 VMSTATE_UINT16(bmcr, RTL8201CPState), 469 VMSTATE_UINT16(bmsr, RTL8201CPState), 470 VMSTATE_UINT16(anar, RTL8201CPState), 471 VMSTATE_UINT16(anlpar, RTL8201CPState), 472 VMSTATE_END_OF_LIST() 473 } 474 }; 475 476 static int aw_emac_post_load(void *opaque, int version_id) 477 { 478 AwEmacState *s = opaque; 479 480 aw_emac_set_link(qemu_get_queue(s->nic)); 481 482 return 0; 483 } 484 485 static const VMStateDescription vmstate_aw_emac = { 486 .name = "allwinner_emac", 487 .version_id = 1, 488 .minimum_version_id = 1, 489 .post_load = aw_emac_post_load, 490 .fields = (VMStateField[]) { 491 VMSTATE_STRUCT(mii, AwEmacState, 1, vmstate_mii, RTL8201CPState), 492 VMSTATE_UINT32(ctl, AwEmacState), 493 VMSTATE_UINT32(tx_mode, AwEmacState), 494 VMSTATE_UINT32(rx_ctl, AwEmacState), 495 VMSTATE_UINT32(int_ctl, AwEmacState), 496 VMSTATE_UINT32(int_sta, AwEmacState), 497 VMSTATE_UINT32(phy_target, AwEmacState), 498 VMSTATE_FIFO8(rx_fifo, AwEmacState), 499 VMSTATE_UINT32(rx_num_packets, AwEmacState), 500 VMSTATE_UINT32(rx_packet_size, AwEmacState), 501 VMSTATE_UINT32(rx_packet_pos, AwEmacState), 502 VMSTATE_STRUCT_ARRAY(tx_fifo, AwEmacState, NUM_TX_FIFOS, 1, 503 vmstate_fifo8, Fifo8), 504 VMSTATE_UINT32_ARRAY(tx_length, AwEmacState, NUM_TX_FIFOS), 505 VMSTATE_UINT32(tx_channel, AwEmacState), 506 VMSTATE_END_OF_LIST() 507 } 508 }; 509 510 static void aw_emac_class_init(ObjectClass *klass, void *data) 511 { 512 DeviceClass *dc = DEVICE_CLASS(klass); 513 514 dc->realize = aw_emac_realize; 515 dc->props = aw_emac_properties; 516 dc->reset = aw_emac_reset; 517 dc->vmsd = &vmstate_aw_emac; 518 } 519 520 static const TypeInfo aw_emac_info = { 521 .name = TYPE_AW_EMAC, 522 .parent = TYPE_SYS_BUS_DEVICE, 523 .instance_size = sizeof(AwEmacState), 524 .instance_init = aw_emac_init, 525 .class_init = aw_emac_class_init, 526 }; 527 528 static void aw_emac_register_types(void) 529 { 530 type_register_static(&aw_emac_info); 531 } 532 533 type_init(aw_emac_register_types) 534