1 /* 2 * QEMU model of the Clock-Reset-LPD (CRL). 3 * 4 * Copyright (c) 2022 Advanced Micro Devices, Inc. 5 * SPDX-License-Identifier: GPL-2.0-or-later 6 * 7 * Written by Edgar E. Iglesias <edgar.iglesias@amd.com> 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "qemu/log.h" 13 #include "qemu/bitops.h" 14 #include "migration/vmstate.h" 15 #include "hw/qdev-properties.h" 16 #include "hw/sysbus.h" 17 #include "hw/irq.h" 18 #include "hw/register.h" 19 #include "hw/resettable.h" 20 21 #include "target/arm/arm-powerctl.h" 22 #include "target/arm/multiprocessing.h" 23 #include "hw/misc/xlnx-versal-crl.h" 24 25 #ifndef XLNX_VERSAL_CRL_ERR_DEBUG 26 #define XLNX_VERSAL_CRL_ERR_DEBUG 0 27 #endif 28 29 static void crl_update_irq(XlnxVersalCRL *s) 30 { 31 bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK]; 32 qemu_set_irq(s->irq, pending); 33 } 34 35 static void crl_status_postw(RegisterInfo *reg, uint64_t val64) 36 { 37 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); 38 crl_update_irq(s); 39 } 40 41 static uint64_t crl_enable_prew(RegisterInfo *reg, uint64_t val64) 42 { 43 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); 44 uint32_t val = val64; 45 46 s->regs[R_IR_MASK] &= ~val; 47 crl_update_irq(s); 48 return 0; 49 } 50 51 static uint64_t crl_disable_prew(RegisterInfo *reg, uint64_t val64) 52 { 53 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); 54 uint32_t val = val64; 55 56 s->regs[R_IR_MASK] |= val; 57 crl_update_irq(s); 58 return 0; 59 } 60 61 static void crl_reset_dev(XlnxVersalCRL *s, DeviceState *dev, 62 bool rst_old, bool rst_new) 63 { 64 device_cold_reset(dev); 65 } 66 67 static void crl_reset_cpu(XlnxVersalCRL *s, ARMCPU *armcpu, 68 bool rst_old, bool rst_new) 69 { 70 if (rst_new) { 71 arm_set_cpu_off(arm_cpu_mp_affinity(armcpu)); 72 } else { 73 arm_set_cpu_on_and_reset(arm_cpu_mp_affinity(armcpu)); 74 } 75 } 76 77 #define REGFIELD_RESET(type, s, reg, f, new_val, dev) { \ 78 bool old_f = ARRAY_FIELD_EX32((s)->regs, reg, f); \ 79 bool new_f = FIELD_EX32(new_val, reg, f); \ 80 \ 81 /* Detect edges. */ \ 82 if (dev && old_f != new_f) { \ 83 crl_reset_ ## type(s, dev, old_f, new_f); \ 84 } \ 85 } 86 87 static uint64_t crl_rst_r5_prew(RegisterInfo *reg, uint64_t val64) 88 { 89 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); 90 91 REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU0, val64, s->cfg.cpu_r5[0]); 92 REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU1, val64, s->cfg.cpu_r5[1]); 93 return val64; 94 } 95 96 static uint64_t crl_rst_adma_prew(RegisterInfo *reg, uint64_t val64) 97 { 98 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); 99 int i; 100 101 /* A single register fans out to all ADMA reset inputs. */ 102 for (i = 0; i < ARRAY_SIZE(s->cfg.adma); i++) { 103 REGFIELD_RESET(dev, s, RST_ADMA, RESET, val64, s->cfg.adma[i]); 104 } 105 return val64; 106 } 107 108 static uint64_t crl_rst_uart0_prew(RegisterInfo *reg, uint64_t val64) 109 { 110 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); 111 112 REGFIELD_RESET(dev, s, RST_UART0, RESET, val64, s->cfg.uart[0]); 113 return val64; 114 } 115 116 static uint64_t crl_rst_uart1_prew(RegisterInfo *reg, uint64_t val64) 117 { 118 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); 119 120 REGFIELD_RESET(dev, s, RST_UART1, RESET, val64, s->cfg.uart[1]); 121 return val64; 122 } 123 124 static uint64_t crl_rst_gem0_prew(RegisterInfo *reg, uint64_t val64) 125 { 126 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); 127 128 REGFIELD_RESET(dev, s, RST_GEM0, RESET, val64, s->cfg.gem[0]); 129 return val64; 130 } 131 132 static uint64_t crl_rst_gem1_prew(RegisterInfo *reg, uint64_t val64) 133 { 134 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); 135 136 REGFIELD_RESET(dev, s, RST_GEM1, RESET, val64, s->cfg.gem[1]); 137 return val64; 138 } 139 140 static uint64_t crl_rst_usb_prew(RegisterInfo *reg, uint64_t val64) 141 { 142 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); 143 144 REGFIELD_RESET(dev, s, RST_USB0, RESET, val64, s->cfg.usb); 145 return val64; 146 } 147 148 static const RegisterAccessInfo crl_regs_info[] = { 149 { .name = "ERR_CTRL", .addr = A_ERR_CTRL, 150 },{ .name = "IR_STATUS", .addr = A_IR_STATUS, 151 .w1c = 0x1, 152 .post_write = crl_status_postw, 153 },{ .name = "IR_MASK", .addr = A_IR_MASK, 154 .reset = 0x1, 155 .ro = 0x1, 156 },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE, 157 .pre_write = crl_enable_prew, 158 },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE, 159 .pre_write = crl_disable_prew, 160 },{ .name = "WPROT", .addr = A_WPROT, 161 },{ .name = "PLL_CLK_OTHER_DMN", .addr = A_PLL_CLK_OTHER_DMN, 162 .reset = 0x1, 163 .rsvd = 0xe, 164 },{ .name = "RPLL_CTRL", .addr = A_RPLL_CTRL, 165 .reset = 0x24809, 166 .rsvd = 0xf88c00f6, 167 },{ .name = "RPLL_CFG", .addr = A_RPLL_CFG, 168 .reset = 0x2000000, 169 .rsvd = 0x1801210, 170 },{ .name = "RPLL_FRAC_CFG", .addr = A_RPLL_FRAC_CFG, 171 .rsvd = 0x7e330000, 172 },{ .name = "PLL_STATUS", .addr = A_PLL_STATUS, 173 .reset = R_PLL_STATUS_RPLL_STABLE_MASK | 174 R_PLL_STATUS_RPLL_LOCK_MASK, 175 .rsvd = 0xfa, 176 .ro = 0x5, 177 },{ .name = "RPLL_TO_XPD_CTRL", .addr = A_RPLL_TO_XPD_CTRL, 178 .reset = 0x2000100, 179 .rsvd = 0xfdfc00ff, 180 },{ .name = "LPD_TOP_SWITCH_CTRL", .addr = A_LPD_TOP_SWITCH_CTRL, 181 .reset = 0x6000300, 182 .rsvd = 0xf9fc00f8, 183 },{ .name = "LPD_LSBUS_CTRL", .addr = A_LPD_LSBUS_CTRL, 184 .reset = 0x2000800, 185 .rsvd = 0xfdfc00f8, 186 },{ .name = "CPU_R5_CTRL", .addr = A_CPU_R5_CTRL, 187 .reset = 0xe000300, 188 .rsvd = 0xe1fc00f8, 189 },{ .name = "IOU_SWITCH_CTRL", .addr = A_IOU_SWITCH_CTRL, 190 .reset = 0x2000500, 191 .rsvd = 0xfdfc00f8, 192 },{ .name = "GEM0_REF_CTRL", .addr = A_GEM0_REF_CTRL, 193 .reset = 0xe000a00, 194 .rsvd = 0xf1fc00f8, 195 },{ .name = "GEM1_REF_CTRL", .addr = A_GEM1_REF_CTRL, 196 .reset = 0xe000a00, 197 .rsvd = 0xf1fc00f8, 198 },{ .name = "GEM_TSU_REF_CTRL", .addr = A_GEM_TSU_REF_CTRL, 199 .reset = 0x300, 200 .rsvd = 0xfdfc00f8, 201 },{ .name = "USB0_BUS_REF_CTRL", .addr = A_USB0_BUS_REF_CTRL, 202 .reset = 0x2001900, 203 .rsvd = 0xfdfc00f8, 204 },{ .name = "UART0_REF_CTRL", .addr = A_UART0_REF_CTRL, 205 .reset = 0xc00, 206 .rsvd = 0xfdfc00f8, 207 },{ .name = "UART1_REF_CTRL", .addr = A_UART1_REF_CTRL, 208 .reset = 0xc00, 209 .rsvd = 0xfdfc00f8, 210 },{ .name = "SPI0_REF_CTRL", .addr = A_SPI0_REF_CTRL, 211 .reset = 0x600, 212 .rsvd = 0xfdfc00f8, 213 },{ .name = "SPI1_REF_CTRL", .addr = A_SPI1_REF_CTRL, 214 .reset = 0x600, 215 .rsvd = 0xfdfc00f8, 216 },{ .name = "CAN0_REF_CTRL", .addr = A_CAN0_REF_CTRL, 217 .reset = 0xc00, 218 .rsvd = 0xfdfc00f8, 219 },{ .name = "CAN1_REF_CTRL", .addr = A_CAN1_REF_CTRL, 220 .reset = 0xc00, 221 .rsvd = 0xfdfc00f8, 222 },{ .name = "I2C0_REF_CTRL", .addr = A_I2C0_REF_CTRL, 223 .reset = 0xc00, 224 .rsvd = 0xfdfc00f8, 225 },{ .name = "I2C1_REF_CTRL", .addr = A_I2C1_REF_CTRL, 226 .reset = 0xc00, 227 .rsvd = 0xfdfc00f8, 228 },{ .name = "DBG_LPD_CTRL", .addr = A_DBG_LPD_CTRL, 229 .reset = 0x300, 230 .rsvd = 0xfdfc00f8, 231 },{ .name = "TIMESTAMP_REF_CTRL", .addr = A_TIMESTAMP_REF_CTRL, 232 .reset = 0x2000c00, 233 .rsvd = 0xfdfc00f8, 234 },{ .name = "CRL_SAFETY_CHK", .addr = A_CRL_SAFETY_CHK, 235 },{ .name = "PSM_REF_CTRL", .addr = A_PSM_REF_CTRL, 236 .reset = 0xf04, 237 .rsvd = 0xfffc00f8, 238 },{ .name = "DBG_TSTMP_CTRL", .addr = A_DBG_TSTMP_CTRL, 239 .reset = 0x300, 240 .rsvd = 0xfdfc00f8, 241 },{ .name = "CPM_TOPSW_REF_CTRL", .addr = A_CPM_TOPSW_REF_CTRL, 242 .reset = 0x300, 243 .rsvd = 0xfdfc00f8, 244 },{ .name = "USB3_DUAL_REF_CTRL", .addr = A_USB3_DUAL_REF_CTRL, 245 .reset = 0x3c00, 246 .rsvd = 0xfdfc00f8, 247 },{ .name = "RST_CPU_R5", .addr = A_RST_CPU_R5, 248 .reset = 0x17, 249 .rsvd = 0x8, 250 .pre_write = crl_rst_r5_prew, 251 },{ .name = "RST_ADMA", .addr = A_RST_ADMA, 252 .reset = 0x1, 253 .pre_write = crl_rst_adma_prew, 254 },{ .name = "RST_GEM0", .addr = A_RST_GEM0, 255 .reset = 0x1, 256 .pre_write = crl_rst_gem0_prew, 257 },{ .name = "RST_GEM1", .addr = A_RST_GEM1, 258 .reset = 0x1, 259 .pre_write = crl_rst_gem1_prew, 260 },{ .name = "RST_SPARE", .addr = A_RST_SPARE, 261 .reset = 0x1, 262 },{ .name = "RST_USB0", .addr = A_RST_USB0, 263 .reset = 0x1, 264 .pre_write = crl_rst_usb_prew, 265 },{ .name = "RST_UART0", .addr = A_RST_UART0, 266 .reset = 0x1, 267 .pre_write = crl_rst_uart0_prew, 268 },{ .name = "RST_UART1", .addr = A_RST_UART1, 269 .reset = 0x1, 270 .pre_write = crl_rst_uart1_prew, 271 },{ .name = "RST_SPI0", .addr = A_RST_SPI0, 272 .reset = 0x1, 273 },{ .name = "RST_SPI1", .addr = A_RST_SPI1, 274 .reset = 0x1, 275 },{ .name = "RST_CAN0", .addr = A_RST_CAN0, 276 .reset = 0x1, 277 },{ .name = "RST_CAN1", .addr = A_RST_CAN1, 278 .reset = 0x1, 279 },{ .name = "RST_I2C0", .addr = A_RST_I2C0, 280 .reset = 0x1, 281 },{ .name = "RST_I2C1", .addr = A_RST_I2C1, 282 .reset = 0x1, 283 },{ .name = "RST_DBG_LPD", .addr = A_RST_DBG_LPD, 284 .reset = 0x33, 285 .rsvd = 0xcc, 286 },{ .name = "RST_GPIO", .addr = A_RST_GPIO, 287 .reset = 0x1, 288 },{ .name = "RST_TTC", .addr = A_RST_TTC, 289 .reset = 0xf, 290 },{ .name = "RST_TIMESTAMP", .addr = A_RST_TIMESTAMP, 291 .reset = 0x1, 292 },{ .name = "RST_SWDT", .addr = A_RST_SWDT, 293 .reset = 0x1, 294 },{ .name = "RST_OCM", .addr = A_RST_OCM, 295 },{ .name = "RST_IPI", .addr = A_RST_IPI, 296 },{ .name = "RST_FPD", .addr = A_RST_FPD, 297 .reset = 0x3, 298 },{ .name = "PSM_RST_MODE", .addr = A_PSM_RST_MODE, 299 .reset = 0x1, 300 .rsvd = 0xf8, 301 } 302 }; 303 304 static void crl_reset_enter(Object *obj, ResetType type) 305 { 306 XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); 307 unsigned int i; 308 309 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { 310 register_reset(&s->regs_info[i]); 311 } 312 } 313 314 static void crl_reset_hold(Object *obj) 315 { 316 XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); 317 318 crl_update_irq(s); 319 } 320 321 static const MemoryRegionOps crl_ops = { 322 .read = register_read_memory, 323 .write = register_write_memory, 324 .endianness = DEVICE_LITTLE_ENDIAN, 325 .valid = { 326 .min_access_size = 4, 327 .max_access_size = 4, 328 }, 329 }; 330 331 static void crl_init(Object *obj) 332 { 333 XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); 334 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 335 int i; 336 337 s->reg_array = 338 register_init_block32(DEVICE(obj), crl_regs_info, 339 ARRAY_SIZE(crl_regs_info), 340 s->regs_info, s->regs, 341 &crl_ops, 342 XLNX_VERSAL_CRL_ERR_DEBUG, 343 CRL_R_MAX * 4); 344 sysbus_init_mmio(sbd, &s->reg_array->mem); 345 sysbus_init_irq(sbd, &s->irq); 346 347 for (i = 0; i < ARRAY_SIZE(s->cfg.cpu_r5); ++i) { 348 object_property_add_link(obj, "cpu_r5[*]", TYPE_ARM_CPU, 349 (Object **)&s->cfg.cpu_r5[i], 350 qdev_prop_allow_set_link_before_realize, 351 OBJ_PROP_LINK_STRONG); 352 } 353 354 for (i = 0; i < ARRAY_SIZE(s->cfg.adma); ++i) { 355 object_property_add_link(obj, "adma[*]", TYPE_DEVICE, 356 (Object **)&s->cfg.adma[i], 357 qdev_prop_allow_set_link_before_realize, 358 OBJ_PROP_LINK_STRONG); 359 } 360 361 for (i = 0; i < ARRAY_SIZE(s->cfg.uart); ++i) { 362 object_property_add_link(obj, "uart[*]", TYPE_DEVICE, 363 (Object **)&s->cfg.uart[i], 364 qdev_prop_allow_set_link_before_realize, 365 OBJ_PROP_LINK_STRONG); 366 } 367 368 for (i = 0; i < ARRAY_SIZE(s->cfg.gem); ++i) { 369 object_property_add_link(obj, "gem[*]", TYPE_DEVICE, 370 (Object **)&s->cfg.gem[i], 371 qdev_prop_allow_set_link_before_realize, 372 OBJ_PROP_LINK_STRONG); 373 } 374 375 object_property_add_link(obj, "usb", TYPE_DEVICE, 376 (Object **)&s->cfg.gem[i], 377 qdev_prop_allow_set_link_before_realize, 378 OBJ_PROP_LINK_STRONG); 379 } 380 381 static void crl_finalize(Object *obj) 382 { 383 XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); 384 register_finalize_block(s->reg_array); 385 } 386 387 static const VMStateDescription vmstate_crl = { 388 .name = TYPE_XLNX_VERSAL_CRL, 389 .version_id = 1, 390 .minimum_version_id = 1, 391 .fields = (const VMStateField[]) { 392 VMSTATE_UINT32_ARRAY(regs, XlnxVersalCRL, CRL_R_MAX), 393 VMSTATE_END_OF_LIST(), 394 } 395 }; 396 397 static void crl_class_init(ObjectClass *klass, void *data) 398 { 399 ResettableClass *rc = RESETTABLE_CLASS(klass); 400 DeviceClass *dc = DEVICE_CLASS(klass); 401 402 dc->vmsd = &vmstate_crl; 403 404 rc->phases.enter = crl_reset_enter; 405 rc->phases.hold = crl_reset_hold; 406 } 407 408 static const TypeInfo crl_info = { 409 .name = TYPE_XLNX_VERSAL_CRL, 410 .parent = TYPE_SYS_BUS_DEVICE, 411 .instance_size = sizeof(XlnxVersalCRL), 412 .class_init = crl_class_init, 413 .instance_init = crl_init, 414 .instance_finalize = crl_finalize, 415 }; 416 417 static void crl_register_types(void) 418 { 419 type_register_static(&crl_info); 420 } 421 422 type_init(crl_register_types) 423