1 /* 2 * ARM TrustZone peripheral protection controller emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "qemu/module.h" 15 #include "qapi/error.h" 16 #include "trace.h" 17 #include "hw/sysbus.h" 18 #include "migration/vmstate.h" 19 #include "hw/registerfields.h" 20 #include "hw/irq.h" 21 #include "hw/misc/tz-ppc.h" 22 23 static void tz_ppc_update_irq(TZPPC *s) 24 { 25 bool level = s->irq_status && s->irq_enable; 26 27 trace_tz_ppc_update_irq(level); 28 qemu_set_irq(s->irq, level); 29 } 30 31 static void tz_ppc_cfg_nonsec(void *opaque, int n, int level) 32 { 33 TZPPC *s = TZ_PPC(opaque); 34 35 assert(n < TZ_NUM_PORTS); 36 trace_tz_ppc_cfg_nonsec(n, level); 37 s->cfg_nonsec[n] = level; 38 } 39 40 static void tz_ppc_cfg_ap(void *opaque, int n, int level) 41 { 42 TZPPC *s = TZ_PPC(opaque); 43 44 assert(n < TZ_NUM_PORTS); 45 trace_tz_ppc_cfg_ap(n, level); 46 s->cfg_ap[n] = level; 47 } 48 49 static void tz_ppc_cfg_sec_resp(void *opaque, int n, int level) 50 { 51 TZPPC *s = TZ_PPC(opaque); 52 53 trace_tz_ppc_cfg_sec_resp(level); 54 s->cfg_sec_resp = level; 55 } 56 57 static void tz_ppc_irq_enable(void *opaque, int n, int level) 58 { 59 TZPPC *s = TZ_PPC(opaque); 60 61 trace_tz_ppc_irq_enable(level); 62 s->irq_enable = level; 63 tz_ppc_update_irq(s); 64 } 65 66 static void tz_ppc_irq_clear(void *opaque, int n, int level) 67 { 68 TZPPC *s = TZ_PPC(opaque); 69 70 trace_tz_ppc_irq_clear(level); 71 72 s->irq_clear = level; 73 if (level) { 74 s->irq_status = false; 75 tz_ppc_update_irq(s); 76 } 77 } 78 79 static bool tz_ppc_check(TZPPC *s, int n, MemTxAttrs attrs) 80 { 81 /* Check whether to allow an access to port n; return true if 82 * the check passes, and false if the transaction must be blocked. 83 * If the latter, the caller must check cfg_sec_resp to determine 84 * whether to abort or RAZ/WI the transaction. 85 * The checks are: 86 * + nonsec_mask suppresses any check of the secure attribute 87 * + otherwise, block if cfg_nonsec is 1 and transaction is secure, 88 * or if cfg_nonsec is 0 and transaction is non-secure 89 * + block if transaction is usermode and cfg_ap is 0 90 */ 91 if ((attrs.secure == s->cfg_nonsec[n] && !(s->nonsec_mask & (1 << n))) || 92 (attrs.user && !s->cfg_ap[n])) { 93 /* Block the transaction. */ 94 if (!s->irq_clear) { 95 /* Note that holding irq_clear high suppresses interrupts */ 96 s->irq_status = true; 97 tz_ppc_update_irq(s); 98 } 99 return false; 100 } 101 return true; 102 } 103 104 static MemTxResult tz_ppc_read(void *opaque, hwaddr addr, uint64_t *pdata, 105 unsigned size, MemTxAttrs attrs) 106 { 107 TZPPCPort *p = opaque; 108 TZPPC *s = p->ppc; 109 int n = p - s->port; 110 AddressSpace *as = &p->downstream_as; 111 uint64_t data; 112 MemTxResult res; 113 114 if (!tz_ppc_check(s, n, attrs)) { 115 trace_tz_ppc_read_blocked(n, addr, attrs.secure, attrs.user); 116 if (s->cfg_sec_resp) { 117 return MEMTX_ERROR; 118 } else { 119 *pdata = 0; 120 return MEMTX_OK; 121 } 122 } 123 124 switch (size) { 125 case 1: 126 data = address_space_ldub(as, addr, attrs, &res); 127 break; 128 case 2: 129 data = address_space_lduw_le(as, addr, attrs, &res); 130 break; 131 case 4: 132 data = address_space_ldl_le(as, addr, attrs, &res); 133 break; 134 case 8: 135 data = address_space_ldq_le(as, addr, attrs, &res); 136 break; 137 default: 138 g_assert_not_reached(); 139 } 140 *pdata = data; 141 return res; 142 } 143 144 static MemTxResult tz_ppc_write(void *opaque, hwaddr addr, uint64_t val, 145 unsigned size, MemTxAttrs attrs) 146 { 147 TZPPCPort *p = opaque; 148 TZPPC *s = p->ppc; 149 AddressSpace *as = &p->downstream_as; 150 int n = p - s->port; 151 MemTxResult res; 152 153 if (!tz_ppc_check(s, n, attrs)) { 154 trace_tz_ppc_write_blocked(n, addr, attrs.secure, attrs.user); 155 if (s->cfg_sec_resp) { 156 return MEMTX_ERROR; 157 } else { 158 return MEMTX_OK; 159 } 160 } 161 162 switch (size) { 163 case 1: 164 address_space_stb(as, addr, val, attrs, &res); 165 break; 166 case 2: 167 address_space_stw_le(as, addr, val, attrs, &res); 168 break; 169 case 4: 170 address_space_stl_le(as, addr, val, attrs, &res); 171 break; 172 case 8: 173 address_space_stq_le(as, addr, val, attrs, &res); 174 break; 175 default: 176 g_assert_not_reached(); 177 } 178 return res; 179 } 180 181 static const MemoryRegionOps tz_ppc_ops = { 182 .read_with_attrs = tz_ppc_read, 183 .write_with_attrs = tz_ppc_write, 184 .endianness = DEVICE_LITTLE_ENDIAN, 185 }; 186 187 static bool tz_ppc_dummy_accepts(void *opaque, hwaddr addr, 188 unsigned size, bool is_write, 189 MemTxAttrs attrs) 190 { 191 /* 192 * Board code should never map the upstream end of an unused port, 193 * so we should never try to make a memory access to it. 194 */ 195 g_assert_not_reached(); 196 } 197 198 static const MemoryRegionOps tz_ppc_dummy_ops = { 199 .valid.accepts = tz_ppc_dummy_accepts, 200 }; 201 202 static void tz_ppc_reset(DeviceState *dev) 203 { 204 TZPPC *s = TZ_PPC(dev); 205 206 trace_tz_ppc_reset(); 207 s->cfg_sec_resp = false; 208 memset(s->cfg_nonsec, 0, sizeof(s->cfg_nonsec)); 209 memset(s->cfg_ap, 0, sizeof(s->cfg_ap)); 210 } 211 212 static void tz_ppc_init(Object *obj) 213 { 214 DeviceState *dev = DEVICE(obj); 215 TZPPC *s = TZ_PPC(obj); 216 217 qdev_init_gpio_in_named(dev, tz_ppc_cfg_nonsec, "cfg_nonsec", TZ_NUM_PORTS); 218 qdev_init_gpio_in_named(dev, tz_ppc_cfg_ap, "cfg_ap", TZ_NUM_PORTS); 219 qdev_init_gpio_in_named(dev, tz_ppc_cfg_sec_resp, "cfg_sec_resp", 1); 220 qdev_init_gpio_in_named(dev, tz_ppc_irq_enable, "irq_enable", 1); 221 qdev_init_gpio_in_named(dev, tz_ppc_irq_clear, "irq_clear", 1); 222 qdev_init_gpio_out_named(dev, &s->irq, "irq", 1); 223 } 224 225 static void tz_ppc_realize(DeviceState *dev, Error **errp) 226 { 227 Object *obj = OBJECT(dev); 228 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 229 TZPPC *s = TZ_PPC(dev); 230 int i; 231 int max_port = 0; 232 233 /* We can't create the upstream end of the port until realize, 234 * as we don't know the size of the MR used as the downstream until then. 235 */ 236 for (i = 0; i < TZ_NUM_PORTS; i++) { 237 if (s->port[i].downstream) { 238 max_port = i; 239 } 240 } 241 242 for (i = 0; i <= max_port; i++) { 243 TZPPCPort *port = &s->port[i]; 244 char *name; 245 uint64_t size; 246 247 if (!port->downstream) { 248 /* 249 * Create dummy sysbus MMIO region so the sysbus region 250 * numbering doesn't get out of sync with the port numbers. 251 * The size is entirely arbitrary. 252 */ 253 name = g_strdup_printf("tz-ppc-dummy-port[%d]", i); 254 memory_region_init_io(&port->upstream, obj, &tz_ppc_dummy_ops, 255 port, name, 0x10000); 256 sysbus_init_mmio(sbd, &port->upstream); 257 g_free(name); 258 continue; 259 } 260 261 name = g_strdup_printf("tz-ppc-port[%d]", i); 262 263 port->ppc = s; 264 address_space_init(&port->downstream_as, port->downstream, name); 265 266 size = memory_region_size(port->downstream); 267 memory_region_init_io(&port->upstream, obj, &tz_ppc_ops, 268 port, name, size); 269 sysbus_init_mmio(sbd, &port->upstream); 270 g_free(name); 271 } 272 } 273 274 static const VMStateDescription tz_ppc_vmstate = { 275 .name = "tz-ppc", 276 .version_id = 1, 277 .minimum_version_id = 1, 278 .fields = (VMStateField[]) { 279 VMSTATE_BOOL_ARRAY(cfg_nonsec, TZPPC, 16), 280 VMSTATE_BOOL_ARRAY(cfg_ap, TZPPC, 16), 281 VMSTATE_BOOL(cfg_sec_resp, TZPPC), 282 VMSTATE_BOOL(irq_enable, TZPPC), 283 VMSTATE_BOOL(irq_clear, TZPPC), 284 VMSTATE_BOOL(irq_status, TZPPC), 285 VMSTATE_END_OF_LIST() 286 } 287 }; 288 289 #define DEFINE_PORT(N) \ 290 DEFINE_PROP_LINK("port[" #N "]", TZPPC, port[N].downstream, \ 291 TYPE_MEMORY_REGION, MemoryRegion *) 292 293 static Property tz_ppc_properties[] = { 294 DEFINE_PROP_UINT32("NONSEC_MASK", TZPPC, nonsec_mask, 0), 295 DEFINE_PORT(0), 296 DEFINE_PORT(1), 297 DEFINE_PORT(2), 298 DEFINE_PORT(3), 299 DEFINE_PORT(4), 300 DEFINE_PORT(5), 301 DEFINE_PORT(6), 302 DEFINE_PORT(7), 303 DEFINE_PORT(8), 304 DEFINE_PORT(9), 305 DEFINE_PORT(10), 306 DEFINE_PORT(11), 307 DEFINE_PORT(12), 308 DEFINE_PORT(13), 309 DEFINE_PORT(14), 310 DEFINE_PORT(15), 311 DEFINE_PROP_END_OF_LIST(), 312 }; 313 314 static void tz_ppc_class_init(ObjectClass *klass, void *data) 315 { 316 DeviceClass *dc = DEVICE_CLASS(klass); 317 318 dc->realize = tz_ppc_realize; 319 dc->vmsd = &tz_ppc_vmstate; 320 dc->reset = tz_ppc_reset; 321 dc->props = tz_ppc_properties; 322 } 323 324 static const TypeInfo tz_ppc_info = { 325 .name = TYPE_TZ_PPC, 326 .parent = TYPE_SYS_BUS_DEVICE, 327 .instance_size = sizeof(TZPPC), 328 .instance_init = tz_ppc_init, 329 .class_init = tz_ppc_class_init, 330 }; 331 332 static void tz_ppc_register_types(void) 333 { 334 type_register_static(&tz_ppc_info); 335 } 336 337 type_init(tz_ppc_register_types); 338