1 /* 2 * ARM TrustZone peripheral protection controller emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "qapi/error.h" 15 #include "trace.h" 16 #include "hw/sysbus.h" 17 #include "hw/registerfields.h" 18 #include "hw/misc/tz-ppc.h" 19 20 static void tz_ppc_update_irq(TZPPC *s) 21 { 22 bool level = s->irq_status && s->irq_enable; 23 24 trace_tz_ppc_update_irq(level); 25 qemu_set_irq(s->irq, level); 26 } 27 28 static void tz_ppc_cfg_nonsec(void *opaque, int n, int level) 29 { 30 TZPPC *s = TZ_PPC(opaque); 31 32 assert(n < TZ_NUM_PORTS); 33 trace_tz_ppc_cfg_nonsec(n, level); 34 s->cfg_nonsec[n] = level; 35 } 36 37 static void tz_ppc_cfg_ap(void *opaque, int n, int level) 38 { 39 TZPPC *s = TZ_PPC(opaque); 40 41 assert(n < TZ_NUM_PORTS); 42 trace_tz_ppc_cfg_ap(n, level); 43 s->cfg_ap[n] = level; 44 } 45 46 static void tz_ppc_cfg_sec_resp(void *opaque, int n, int level) 47 { 48 TZPPC *s = TZ_PPC(opaque); 49 50 trace_tz_ppc_cfg_sec_resp(level); 51 s->cfg_sec_resp = level; 52 } 53 54 static void tz_ppc_irq_enable(void *opaque, int n, int level) 55 { 56 TZPPC *s = TZ_PPC(opaque); 57 58 trace_tz_ppc_irq_enable(level); 59 s->irq_enable = level; 60 tz_ppc_update_irq(s); 61 } 62 63 static void tz_ppc_irq_clear(void *opaque, int n, int level) 64 { 65 TZPPC *s = TZ_PPC(opaque); 66 67 trace_tz_ppc_irq_clear(level); 68 69 s->irq_clear = level; 70 if (level) { 71 s->irq_status = false; 72 tz_ppc_update_irq(s); 73 } 74 } 75 76 static bool tz_ppc_check(TZPPC *s, int n, MemTxAttrs attrs) 77 { 78 /* Check whether to allow an access to port n; return true if 79 * the check passes, and false if the transaction must be blocked. 80 * If the latter, the caller must check cfg_sec_resp to determine 81 * whether to abort or RAZ/WI the transaction. 82 * The checks are: 83 * + nonsec_mask suppresses any check of the secure attribute 84 * + otherwise, block if cfg_nonsec is 1 and transaction is secure, 85 * or if cfg_nonsec is 0 and transaction is non-secure 86 * + block if transaction is usermode and cfg_ap is 0 87 */ 88 if ((attrs.secure == s->cfg_nonsec[n] && !(s->nonsec_mask & (1 << n))) || 89 (attrs.user && !s->cfg_ap[n])) { 90 /* Block the transaction. */ 91 if (!s->irq_clear) { 92 /* Note that holding irq_clear high suppresses interrupts */ 93 s->irq_status = true; 94 tz_ppc_update_irq(s); 95 } 96 return false; 97 } 98 return true; 99 } 100 101 static MemTxResult tz_ppc_read(void *opaque, hwaddr addr, uint64_t *pdata, 102 unsigned size, MemTxAttrs attrs) 103 { 104 TZPPCPort *p = opaque; 105 TZPPC *s = p->ppc; 106 int n = p - s->port; 107 AddressSpace *as = &p->downstream_as; 108 uint64_t data; 109 MemTxResult res; 110 111 if (!tz_ppc_check(s, n, attrs)) { 112 trace_tz_ppc_read_blocked(n, addr, attrs.secure, attrs.user); 113 if (s->cfg_sec_resp) { 114 return MEMTX_ERROR; 115 } else { 116 *pdata = 0; 117 return MEMTX_OK; 118 } 119 } 120 121 switch (size) { 122 case 1: 123 data = address_space_ldub(as, addr, attrs, &res); 124 break; 125 case 2: 126 data = address_space_lduw_le(as, addr, attrs, &res); 127 break; 128 case 4: 129 data = address_space_ldl_le(as, addr, attrs, &res); 130 break; 131 case 8: 132 data = address_space_ldq_le(as, addr, attrs, &res); 133 break; 134 default: 135 g_assert_not_reached(); 136 } 137 *pdata = data; 138 return res; 139 } 140 141 static MemTxResult tz_ppc_write(void *opaque, hwaddr addr, uint64_t val, 142 unsigned size, MemTxAttrs attrs) 143 { 144 TZPPCPort *p = opaque; 145 TZPPC *s = p->ppc; 146 AddressSpace *as = &p->downstream_as; 147 int n = p - s->port; 148 MemTxResult res; 149 150 if (!tz_ppc_check(s, n, attrs)) { 151 trace_tz_ppc_write_blocked(n, addr, attrs.secure, attrs.user); 152 if (s->cfg_sec_resp) { 153 return MEMTX_ERROR; 154 } else { 155 return MEMTX_OK; 156 } 157 } 158 159 switch (size) { 160 case 1: 161 address_space_stb(as, addr, val, attrs, &res); 162 break; 163 case 2: 164 address_space_stw_le(as, addr, val, attrs, &res); 165 break; 166 case 4: 167 address_space_stl_le(as, addr, val, attrs, &res); 168 break; 169 case 8: 170 address_space_stq_le(as, addr, val, attrs, &res); 171 break; 172 default: 173 g_assert_not_reached(); 174 } 175 return res; 176 } 177 178 static const MemoryRegionOps tz_ppc_ops = { 179 .read_with_attrs = tz_ppc_read, 180 .write_with_attrs = tz_ppc_write, 181 .endianness = DEVICE_LITTLE_ENDIAN, 182 }; 183 184 static bool tz_ppc_dummy_accepts(void *opaque, hwaddr addr, 185 unsigned size, bool is_write, 186 MemTxAttrs attrs) 187 { 188 /* 189 * Board code should never map the upstream end of an unused port, 190 * so we should never try to make a memory access to it. 191 */ 192 g_assert_not_reached(); 193 } 194 195 static const MemoryRegionOps tz_ppc_dummy_ops = { 196 .valid.accepts = tz_ppc_dummy_accepts, 197 }; 198 199 static void tz_ppc_reset(DeviceState *dev) 200 { 201 TZPPC *s = TZ_PPC(dev); 202 203 trace_tz_ppc_reset(); 204 s->cfg_sec_resp = false; 205 memset(s->cfg_nonsec, 0, sizeof(s->cfg_nonsec)); 206 memset(s->cfg_ap, 0, sizeof(s->cfg_ap)); 207 } 208 209 static void tz_ppc_init(Object *obj) 210 { 211 DeviceState *dev = DEVICE(obj); 212 TZPPC *s = TZ_PPC(obj); 213 214 qdev_init_gpio_in_named(dev, tz_ppc_cfg_nonsec, "cfg_nonsec", TZ_NUM_PORTS); 215 qdev_init_gpio_in_named(dev, tz_ppc_cfg_ap, "cfg_ap", TZ_NUM_PORTS); 216 qdev_init_gpio_in_named(dev, tz_ppc_cfg_sec_resp, "cfg_sec_resp", 1); 217 qdev_init_gpio_in_named(dev, tz_ppc_irq_enable, "irq_enable", 1); 218 qdev_init_gpio_in_named(dev, tz_ppc_irq_clear, "irq_clear", 1); 219 qdev_init_gpio_out_named(dev, &s->irq, "irq", 1); 220 } 221 222 static void tz_ppc_realize(DeviceState *dev, Error **errp) 223 { 224 Object *obj = OBJECT(dev); 225 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 226 TZPPC *s = TZ_PPC(dev); 227 int i; 228 int max_port = 0; 229 230 /* We can't create the upstream end of the port until realize, 231 * as we don't know the size of the MR used as the downstream until then. 232 */ 233 for (i = 0; i < TZ_NUM_PORTS; i++) { 234 if (s->port[i].downstream) { 235 max_port = i; 236 } 237 } 238 239 for (i = 0; i <= max_port; i++) { 240 TZPPCPort *port = &s->port[i]; 241 char *name; 242 uint64_t size; 243 244 if (!port->downstream) { 245 /* 246 * Create dummy sysbus MMIO region so the sysbus region 247 * numbering doesn't get out of sync with the port numbers. 248 * The size is entirely arbitrary. 249 */ 250 name = g_strdup_printf("tz-ppc-dummy-port[%d]", i); 251 memory_region_init_io(&port->upstream, obj, &tz_ppc_dummy_ops, 252 port, name, 0x10000); 253 sysbus_init_mmio(sbd, &port->upstream); 254 g_free(name); 255 continue; 256 } 257 258 name = g_strdup_printf("tz-ppc-port[%d]", i); 259 260 port->ppc = s; 261 address_space_init(&port->downstream_as, port->downstream, name); 262 263 size = memory_region_size(port->downstream); 264 memory_region_init_io(&port->upstream, obj, &tz_ppc_ops, 265 port, name, size); 266 sysbus_init_mmio(sbd, &port->upstream); 267 g_free(name); 268 } 269 } 270 271 static const VMStateDescription tz_ppc_vmstate = { 272 .name = "tz-ppc", 273 .version_id = 1, 274 .minimum_version_id = 1, 275 .fields = (VMStateField[]) { 276 VMSTATE_BOOL_ARRAY(cfg_nonsec, TZPPC, 16), 277 VMSTATE_BOOL_ARRAY(cfg_ap, TZPPC, 16), 278 VMSTATE_BOOL(cfg_sec_resp, TZPPC), 279 VMSTATE_BOOL(irq_enable, TZPPC), 280 VMSTATE_BOOL(irq_clear, TZPPC), 281 VMSTATE_BOOL(irq_status, TZPPC), 282 VMSTATE_END_OF_LIST() 283 } 284 }; 285 286 #define DEFINE_PORT(N) \ 287 DEFINE_PROP_LINK("port[" #N "]", TZPPC, port[N].downstream, \ 288 TYPE_MEMORY_REGION, MemoryRegion *) 289 290 static Property tz_ppc_properties[] = { 291 DEFINE_PROP_UINT32("NONSEC_MASK", TZPPC, nonsec_mask, 0), 292 DEFINE_PORT(0), 293 DEFINE_PORT(1), 294 DEFINE_PORT(2), 295 DEFINE_PORT(3), 296 DEFINE_PORT(4), 297 DEFINE_PORT(5), 298 DEFINE_PORT(6), 299 DEFINE_PORT(7), 300 DEFINE_PORT(8), 301 DEFINE_PORT(9), 302 DEFINE_PORT(10), 303 DEFINE_PORT(11), 304 DEFINE_PORT(12), 305 DEFINE_PORT(13), 306 DEFINE_PORT(14), 307 DEFINE_PORT(15), 308 DEFINE_PROP_END_OF_LIST(), 309 }; 310 311 static void tz_ppc_class_init(ObjectClass *klass, void *data) 312 { 313 DeviceClass *dc = DEVICE_CLASS(klass); 314 315 dc->realize = tz_ppc_realize; 316 dc->vmsd = &tz_ppc_vmstate; 317 dc->reset = tz_ppc_reset; 318 dc->props = tz_ppc_properties; 319 } 320 321 static const TypeInfo tz_ppc_info = { 322 .name = TYPE_TZ_PPC, 323 .parent = TYPE_SYS_BUS_DEVICE, 324 .instance_size = sizeof(TZPPC), 325 .instance_init = tz_ppc_init, 326 .class_init = tz_ppc_class_init, 327 }; 328 329 static void tz_ppc_register_types(void) 330 { 331 type_register_static(&tz_ppc_info); 332 } 333 334 type_init(tz_ppc_register_types); 335