1# See docs/devel/tracing.rst for syntax documentation. 2 3# allwinner-cpucfg.c 4allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_addr 0x%" PRIx32 5allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 6allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 7 8# allwinner-h3-dramc.c 9allwinner_h3_dramc_rowmirror_disable(void) "Disable row mirror" 10allwinner_h3_dramc_rowmirror_enable(uint64_t addr) "Enable row mirror: addr 0x%" PRIx64 11allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 12allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 13allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 14allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 15allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 16allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 17 18# allwinner-r40-dramc.c 19allwinner_r40_dramc_detect_cells_disable(void) "Disable detect cells" 20allwinner_r40_dramc_detect_cells_enable(void) "Enable detect cells" 21allwinner_r40_dramc_map_rows(uint8_t row_bits, uint8_t bank_bits, uint8_t col_bits) "DRAM layout: row_bits %d, bank_bits %d, col_bits %d" 22allwinner_r40_dramc_offset_to_cell(uint64_t offset, int row, int bank, int col) "offset 0x%" PRIx64 " row %d bank %d col %d" 23allwinner_r40_dramc_detect_cell_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 "" 24allwinner_r40_dramc_detect_cell_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 "" 25allwinner_r40_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 26allwinner_r40_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 27allwinner_r40_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 28allwinner_r40_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 29allwinner_r40_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 30allwinner_r40_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 31 32# allwinner-sid.c 33allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 34allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 35 36# allwinner-sramc.c 37allwinner_sramc_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 38allwinner_sramc_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 39 40# aspeed_ibt.c 41aspeed_ibt_chr_dump_msg(const char *func, const char *buf, uint32_t len) "%s: %s #%d bytes" 42aspeed_ibt_chr_event(bool connected) "connected:%d" 43aspeed_ibt_read(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64 44aspeed_ibt_write(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64 45aspeed_ibt_event(const char* event) "%s" 46 47# avr_power.c 48avr_power_read(uint8_t value) "power_reduc read value:%u" 49avr_power_write(uint8_t value) "power_reduc write value:%u" 50 51# axp2xx 52axp2xx_rx(uint8_t reg, uint8_t data) "Read reg 0x%" PRIx8 " : 0x%" PRIx8 53axp2xx_select(uint8_t reg) "Accessing reg 0x%" PRIx8 54axp2xx_tx(uint8_t reg, uint8_t data) "Write reg 0x%" PRIx8 " : 0x%" PRIx8 55 56# eccmemctl.c 57ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x" 58ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x" 59ecc_mem_writel_mfsr(uint32_t val) "Write memory fault status 0x%08x" 60ecc_mem_writel_vcr(uint32_t val) "Write slot configuration 0x%08x" 61ecc_mem_writel_dr(uint32_t val) "Write diagnostic 0x%08x" 62ecc_mem_writel_ecr0(uint32_t val) "Write event count 1 0x%08x" 63ecc_mem_writel_ecr1(uint32_t val) "Write event count 2 0x%08x" 64ecc_mem_readl_mer(uint32_t ret) "Read memory enable 0x%08x" 65ecc_mem_readl_mdr(uint32_t ret) "Read memory delay 0x%08x" 66ecc_mem_readl_mfsr(uint32_t ret) "Read memory fault status 0x%08x" 67ecc_mem_readl_vcr(uint32_t ret) "Read slot configuration 0x%08x" 68ecc_mem_readl_mfar0(uint32_t ret) "Read memory fault address 0 0x%08x" 69ecc_mem_readl_mfar1(uint32_t ret) "Read memory fault address 1 0x%08x" 70ecc_mem_readl_dr(uint32_t ret) "Read diagnostic 0x%08x" 71ecc_mem_readl_ecr0(uint32_t ret) "Read event count 1 0x%08x" 72ecc_mem_readl_ecr1(uint32_t ret) "Read event count 2 0x%08x" 73ecc_diag_mem_writeb(uint64_t addr, uint32_t val) "Write diagnostic %"PRId64" = 0x%02x" 74ecc_diag_mem_readb(uint64_t addr, uint32_t ret) "Read diagnostic %"PRId64"= 0x%02x" 75 76# empty_slot.c 77empty_slot_write(uint64_t addr, unsigned width, uint64_t value, unsigned size, const char *name) "wr addr:0x%04"PRIx64" data:0x%0*"PRIx64" size %u [%s]" 78 79# slavio_misc.c 80slavio_misc_update_irq_raise(void) "Raise IRQ" 81slavio_misc_update_irq_lower(void) "Lower IRQ" 82slavio_set_power_fail(int power_failing, uint8_t config) "Power fail: %d, config: %d" 83slavio_cfg_mem_writeb(uint32_t val) "Write config 0x%02x" 84slavio_cfg_mem_readb(uint32_t ret) "Read config 0x%02x" 85slavio_diag_mem_writeb(uint32_t val) "Write diag 0x%02x" 86slavio_diag_mem_readb(uint32_t ret) "Read diag 0x%02x" 87slavio_mdm_mem_writeb(uint32_t val) "Write modem control 0x%02x" 88slavio_mdm_mem_readb(uint32_t ret) "Read modem control 0x%02x" 89slavio_aux1_mem_writeb(uint32_t val) "Write aux1 0x%02x" 90slavio_aux1_mem_readb(uint32_t ret) "Read aux1 0x%02x" 91slavio_aux2_mem_writeb(uint32_t val) "Write aux2 0x%02x" 92slavio_aux2_mem_readb(uint32_t ret) "Read aux2 0x%02x" 93apc_mem_writeb(uint32_t val) "Write power management 0x%02x" 94apc_mem_readb(uint32_t ret) "Read power management 0x%02x" 95slavio_sysctrl_mem_writel(uint32_t val) "Write system control 0x%08x" 96slavio_sysctrl_mem_readl(uint32_t ret) "Read system control 0x%08x" 97slavio_led_mem_writew(uint32_t val) "Write diagnostic LED 0x%04x" 98slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED 0x%04x" 99 100# aspeed_scu.c 101aspeed_scu_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 102aspeed_scu_read(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 103 104# mps2-scc.c 105mps2_scc_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 SCC read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 106mps2_scc_write(uint64_t offset, uint64_t data, unsigned size) "MPS2 SCC write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 107mps2_scc_reset(void) "MPS2 SCC: reset" 108mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config write: function %d device %d data 0x%" PRIx32 109mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config read: function %d device %d data 0x%" PRIx32 110 111# mps2-fpgaio.c 112mps2_fpgaio_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 113mps2_fpgaio_write(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 114mps2_fpgaio_reset(void) "MPS2 FPGAIO: reset" 115 116# msf2-sysreg.c 117msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" PRIx64 " data 0x%" PRIx32 " prev 0x%" PRIx32 118msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" PRIx64 " data 0x%08" PRIx32 119msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status register" 120 121# imx7_gpr.c 122imx7_gpr_read(uint64_t offset) "addr 0x%08" PRIx64 123imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" PRIx64 "value 0x%08" PRIx64 124 125# mos6522.c 126mos6522_set_counter(int index, unsigned int val) "T%d.counter=%d" 127mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d counter=0x%"PRIx64 " delta_next=0x%"PRIx64 128mos6522_set_sr_int(void) "set sr_int" 129mos6522_write(uint64_t addr, const char *name, uint64_t val) "reg=0x%"PRIx64 " [%s] val=0x%"PRIx64 130mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=0x%"PRIx64 " [%s] val=0x%x" 131 132# npcm7xx_clk.c 133npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 134npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 135 136# npcm7xx_gcr.c 137npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 138npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 139 140# npcm7xx_mft.c 141npcm7xx_mft_read(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 142npcm7xx_mft_write(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 143npcm7xx_mft_rpm(const char *clock, uint32_t clock_hz, int state, int32_t cnt, uint32_t rpm, uint32_t duty) " fan clk: %s clock_hz: %" PRIu32 ", state: %d, cnt: %" PRIi32 ", rpm: %" PRIu32 ", duty: %" PRIu32 144npcm7xx_mft_capture(const char *name, int irq_level) "%s: level: %d" 145npcm7xx_mft_update_clock(const char *name, uint16_t sel, uint64_t clock_period, uint64_t prescaled_clock_period) "%s: sel: 0x%02" PRIx16 ", period: %" PRIu64 ", prescaled: %" PRIu64 146npcm7xx_mft_set_duty(const char *name, int n, int value) "%s[%d]: %d" 147 148# npcm7xx_rng.c 149npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" 150npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" 151 152# npcm7xx_pwm.c 153npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 154npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 155npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u" 156npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u" 157 158# stm32f4xx_syscfg.c 159stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interrupt: GPIO: %d, Line: %d; Level: %d" 160stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d" 161stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " 162stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" 163 164# stm32f4xx_exti.c 165stm32f4xx_exti_set_irq(int irq, int leve) "Set EXTI: %d to %d" 166stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " 167stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" 168 169# tz-mpc.c 170tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u" 171tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u" 172tz_mpc_mem_blocked_read(uint64_t addr, unsigned size, bool secure) "TZ MPC blocked read: offset 0x%" PRIx64 " size %u secure %d" 173tz_mpc_mem_blocked_write(uint64_t addr, uint64_t data, unsigned size, bool secure) "TZ MPC blocked write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" 174tz_mpc_translate(uint64_t addr, int flags, const char *idx, const char *res) "TZ MPC translate: addr 0x%" PRIx64 " flags 0x%x iommu_idx %s: %s" 175tz_mpc_iommu_notify(uint64_t addr) "TZ MPC iommu: notifying UNMAP/MAP for 0x%" PRIx64 176 177# tz-msc.c 178tz_msc_reset(void) "TZ MSC: reset" 179tz_msc_cfg_nonsec(int level) "TZ MSC: cfg_nonsec = %d" 180tz_msc_cfg_sec_resp(int level) "TZ MSC: cfg_sec_resp = %d" 181tz_msc_irq_clear(int level) "TZ MSC: int_clear = %d" 182tz_msc_update_irq(int level) "TZ MSC: setting irq line to %d" 183tz_msc_access_blocked(uint64_t offset) "TZ MSC: offset 0x%" PRIx64 " access blocked" 184 185# tz-ppc.c 186tz_ppc_reset(void) "TZ PPC: reset" 187tz_ppc_cfg_nonsec(int n, int level) "TZ PPC: cfg_nonsec[%d] = %d" 188tz_ppc_cfg_ap(int n, int level) "TZ PPC: cfg_ap[%d] = %d" 189tz_ppc_cfg_sec_resp(int level) "TZ PPC: cfg_sec_resp = %d" 190tz_ppc_irq_enable(int level) "TZ PPC: int_enable = %d" 191tz_ppc_irq_clear(int level) "TZ PPC: int_clear = %d" 192tz_ppc_update_irq(int level) "TZ PPC: setting irq line to %d" 193tz_ppc_read_blocked(int n, uint64_t offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" PRIx64 " read (secure %d user %d) blocked" 194tz_ppc_write_blocked(int n, uint64_t offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" PRIx64 " write (secure %d user %d) blocked" 195 196# iotkit-secctl.c 197iotkit_secctl_s_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs read: offset 0x%x data 0x%" PRIx64 " size %u" 198iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs write: offset 0x%x data 0x%" PRIx64 " size %u" 199iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u" 200iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u" 201 202# imx6ul_ccm.c 203ccm_entry(void) "" 204ccm_freq(uint32_t freq) "freq = %d" 205ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d" 206ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 207ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 208 209# iotkit-sysinfo.c 210iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 211iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 212 213# iotkit-sysctl.c 214iotkit_sysctl_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysCtl read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 215iotkit_sysctl_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysCtl write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 216iotkit_sysctl_reset(void) "IoTKit SysCtl: reset" 217 218# armsse-cpu-pwrctrl.c 219armsse_cpu_pwrctrl_read(uint64_t offset, uint64_t data, unsigned size) "SSE-300 CPU_PWRCTRL read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 220armsse_cpu_pwrctrl_write(uint64_t offset, uint64_t data, unsigned size) "SSE-300 CPU_PWRCTRL write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 221 222# armsse-cpuid.c 223armsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 224armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 225 226# armsse-mhu.c 227armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 228armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" 229 230# aspeed_xdma.c 231aspeed_xdma_write(uint64_t offset, uint64_t data) "XDMA write: offset 0x%" PRIx64 " data 0x%" PRIx64 232 233# aspeed_i3c.c 234aspeed_i3c_read(uint64_t offset, uint64_t data) "I3C read: offset 0x%" PRIx64 " data 0x%" PRIx64 235aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64 236aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64 237aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64 238 239# aspeed_gfx.c 240aspeed_gfx_read(uint64_t offset, uint64_t data) "read: offset 0x%" PRIx64 " data 0x%" PRIx64 241aspeed_gfx_write(uint64_t offset, uint64_t data) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 242 243# aspeed_pwm.c 244aspeed_pwm_read(uint64_t offset, uint64_t data) "read: offset 0x%" PRIx64 " data 0x%" PRIx64 245aspeed_pwm_write(uint64_t offset, uint64_t data) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 246 247# aspeed_sdmc.c 248aspeed_sdmc_write(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64 249aspeed_sdmc_read(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64 250 251# aspeed_peci.c 252aspeed_peci_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 253aspeed_peci_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 254aspeed_peci_raise_interrupt(uint32_t ctrl, uint32_t status) "ctrl 0x%" PRIx32 " status 0x%" PRIx32 255 256# bcm2835_property.c 257bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbox property tag:0x%08x in_sz:%u out_sz:%zu" 258 259# bcm2835_mbox.c 260bcm2835_mbox_write(unsigned int size, uint64_t addr, uint64_t value) "mbox write sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 261bcm2835_mbox_read(unsigned int size, uint64_t addr, uint64_t value) "mbox read sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 262bcm2835_mbox_irq(unsigned level) "mbox irq:ARM level:%u" 263 264# mac_via.c 265via1_rtc_update_data_out(int count, int value) "count=%d value=0x%02x" 266via1_rtc_update_data_in(int count, int value) "count=%d value=0x%02x" 267via1_rtc_internal_status(int cmd, int alt, int value) "cmd=0x%02x alt=0x%02x value=0x%02x" 268via1_rtc_internal_cmd(int cmd) "cmd=0x%02x" 269via1_rtc_cmd_invalid(int value) "value=0x%02x" 270via1_rtc_internal_time(uint32_t time) "time=0x%08x" 271via1_rtc_internal_set_cmd(int cmd) "cmd=0x%02x" 272via1_rtc_internal_ignore_cmd(int cmd) "cmd=0x%02x" 273via1_rtc_internal_set_alt(int alt, int sector, int offset) "alt=0x%02x sector=%u offset=%u" 274via1_rtc_cmd_seconds_read(int reg, int value) "reg=%d value=0x%02x" 275via1_rtc_cmd_seconds_write(int reg, int value) "reg=%d value=0x%02x" 276via1_rtc_cmd_test_write(int value) "value=0x%02x" 277via1_rtc_cmd_wprotect_write(int value) "value=0x%02x" 278via1_rtc_cmd_pram_read(int addr, int value) "addr=%u value=0x%02x" 279via1_rtc_cmd_pram_write(int addr, int value) "addr=%u value=0x%02x" 280via1_rtc_cmd_pram_sect_read(int sector, int offset, int addr, int value) "sector=%u offset=%u addr=0x%x value=0x%02x" 281via1_rtc_cmd_pram_sect_write(int sector, int offset, int addr, int value) "sector=%u offset=%u addr=0x%x value=0x%02x" 282via1_adb_send(const char *state, uint8_t data, const char *vadbint) "state %s data=0x%02x vADBInt=%s" 283via1_adb_receive(const char *state, uint8_t data, const char *vadbint, int status, int index, int size) "state %s data=0x%02x vADBInt=%s status=0x%x index=%d size=%d" 284via1_adb_poll(uint8_t data, const char *vadbint, int status, int index, int size) "data=0x%02x vADBInt=%s status=0x%x index=%d size=%d" 285via1_auxmode(int mode) "setting auxmode to %d" 286 287# grlib_ahb_apb_pnp.c 288grlib_ahb_pnp_read(uint64_t addr, unsigned size, uint32_t value) "AHB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x" 289grlib_apb_pnp_read(uint64_t addr, unsigned size, uint32_t value) "APB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x" 290 291# led.c 292led_set_intensity(const char *color, const char *desc, uint8_t intensity_percent) "LED desc:'%s' color:%s intensity: %u%%" 293led_change_intensity(const char *color, const char *desc, uint8_t old_intensity_percent, uint8_t new_intensity_percent) "LED desc:'%s' color:%s intensity %u%% -> %u%%" 294 295# pca9552.c 296pca955x_gpio_status(const char *description, const char *buf) "%s GPIOs 0-15 [%s]" 297pca955x_gpio_change(const char *description, unsigned id, unsigned prev_state, unsigned current_state) "%s GPIO id:%u status: %u -> %u" 298 299# bcm2835_cprman.c 300bcm2835_cprman_read(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64 301bcm2835_cprman_write(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64 302bcm2835_cprman_write_invalid_magic(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64 303 304# virt_ctrl.c 305virt_ctrl_read(void *dev, unsigned int addr, unsigned int size, uint64_t value) "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64 306virt_ctrl_write(void *dev, unsigned int addr, unsigned int size, uint64_t value) "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64 307virt_ctrl_reset(void *dev) "ctrl: %p" 308virt_ctrl_realize(void *dev) "ctrl: %p" 309virt_ctrl_instance_init(void *dev) "ctrl: %p" 310 311# lasi.c 312lasi_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64" is %d" 313lasi_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" 314lasi_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" 315