xref: /openbmc/qemu/hw/misc/trace-events (revision ca5aa28e)
1# See docs/devel/tracing.rst for syntax documentation.
2
3# allwinner-cpucfg.c
4allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_addr 0x%" PRIx32
5allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
6allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
7
8# allwinner-h3-dramc.c
9allwinner_h3_dramc_rowmirror_disable(void) "Disable row mirror"
10allwinner_h3_dramc_rowmirror_enable(uint64_t addr) "Enable row mirror: addr 0x%" PRIx64
11allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
12allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
13allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
14allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
15allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
16allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
17
18# allwinner-r40-dramc.c
19allwinner_r40_dramc_detect_cells_disable(void) "Disable detect cells"
20allwinner_r40_dramc_detect_cells_enable(void) "Enable detect cells"
21allwinner_r40_dramc_map_rows(uint8_t row_bits, uint8_t bank_bits, uint8_t col_bits) "DRAM layout: row_bits %d, bank_bits %d, col_bits %d"
22allwinner_r40_dramc_offset_to_cell(uint64_t offset, int row, int bank, int col) "offset 0x%" PRIx64 " row %d bank %d col %d"
23allwinner_r40_dramc_detect_cell_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 ""
24allwinner_r40_dramc_detect_cell_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 ""
25allwinner_r40_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
26allwinner_r40_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
27allwinner_r40_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
28allwinner_r40_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
29allwinner_r40_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
30allwinner_r40_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
31
32# allwinner-sid.c
33allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
34allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
35
36# allwinner-sramc.c
37allwinner_sramc_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64
38allwinner_sramc_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64
39
40# avr_power.c
41avr_power_read(uint8_t value) "power_reduc read value:%u"
42avr_power_write(uint8_t value) "power_reduc write value:%u"
43
44# axp2xx
45axp2xx_rx(uint8_t reg, uint8_t data) "Read reg 0x%" PRIx8 " : 0x%" PRIx8
46axp2xx_select(uint8_t reg) "Accessing reg 0x%" PRIx8
47axp2xx_tx(uint8_t reg, uint8_t data) "Write reg 0x%" PRIx8 " : 0x%" PRIx8
48
49# eccmemctl.c
50ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
51ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"
52ecc_mem_writel_mfsr(uint32_t val) "Write memory fault status 0x%08x"
53ecc_mem_writel_vcr(uint32_t val) "Write slot configuration 0x%08x"
54ecc_mem_writel_dr(uint32_t val) "Write diagnostic 0x%08x"
55ecc_mem_writel_ecr0(uint32_t val) "Write event count 1 0x%08x"
56ecc_mem_writel_ecr1(uint32_t val) "Write event count 2 0x%08x"
57ecc_mem_readl_mer(uint32_t ret) "Read memory enable 0x%08x"
58ecc_mem_readl_mdr(uint32_t ret) "Read memory delay 0x%08x"
59ecc_mem_readl_mfsr(uint32_t ret) "Read memory fault status 0x%08x"
60ecc_mem_readl_vcr(uint32_t ret) "Read slot configuration 0x%08x"
61ecc_mem_readl_mfar0(uint32_t ret) "Read memory fault address 0 0x%08x"
62ecc_mem_readl_mfar1(uint32_t ret) "Read memory fault address 1 0x%08x"
63ecc_mem_readl_dr(uint32_t ret) "Read diagnostic 0x%08x"
64ecc_mem_readl_ecr0(uint32_t ret) "Read event count 1 0x%08x"
65ecc_mem_readl_ecr1(uint32_t ret) "Read event count 2 0x%08x"
66ecc_diag_mem_writeb(uint64_t addr, uint32_t val) "Write diagnostic %"PRId64" = 0x%02x"
67ecc_diag_mem_readb(uint64_t addr, uint32_t ret) "Read diagnostic %"PRId64"= 0x%02x"
68
69# empty_slot.c
70empty_slot_write(uint64_t addr, unsigned width, uint64_t value, unsigned size, const char *name) "wr addr:0x%04"PRIx64" data:0x%0*"PRIx64" size %u [%s]"
71
72# slavio_misc.c
73slavio_misc_update_irq_raise(void) "Raise IRQ"
74slavio_misc_update_irq_lower(void) "Lower IRQ"
75slavio_set_power_fail(int power_failing, uint8_t config) "Power fail: %d, config: %d"
76slavio_cfg_mem_writeb(uint32_t val) "Write config 0x%02x"
77slavio_cfg_mem_readb(uint32_t ret) "Read config 0x%02x"
78slavio_diag_mem_writeb(uint32_t val) "Write diag 0x%02x"
79slavio_diag_mem_readb(uint32_t ret) "Read diag 0x%02x"
80slavio_mdm_mem_writeb(uint32_t val) "Write modem control 0x%02x"
81slavio_mdm_mem_readb(uint32_t ret) "Read modem control 0x%02x"
82slavio_aux1_mem_writeb(uint32_t val) "Write aux1 0x%02x"
83slavio_aux1_mem_readb(uint32_t ret) "Read aux1 0x%02x"
84slavio_aux2_mem_writeb(uint32_t val) "Write aux2 0x%02x"
85slavio_aux2_mem_readb(uint32_t ret) "Read aux2 0x%02x"
86apc_mem_writeb(uint32_t val) "Write power management 0x%02x"
87apc_mem_readb(uint32_t ret) "Read power management 0x%02x"
88slavio_sysctrl_mem_writel(uint32_t val) "Write system control 0x%08x"
89slavio_sysctrl_mem_readl(uint32_t ret) "Read system control 0x%08x"
90slavio_led_mem_writew(uint32_t val) "Write diagnostic LED 0x%04x"
91slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED 0x%04x"
92
93# aspeed_scu.c
94aspeed_scu_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
95aspeed_scu_read(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
96aspeed_ast2700_scu_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
97aspeed_ast2700_scu_read(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
98aspeed_ast2700_scuio_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
99aspeed_ast2700_scuio_read(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
100
101# mps2-scc.c
102mps2_scc_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 SCC read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
103mps2_scc_write(uint64_t offset, uint64_t data, unsigned size) "MPS2 SCC write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
104mps2_scc_reset(void) "MPS2 SCC: reset"
105mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config write: function %d device %d data 0x%" PRIx32
106mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config read: function %d device %d data 0x%" PRIx32
107
108# mps2-fpgaio.c
109mps2_fpgaio_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
110mps2_fpgaio_write(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
111mps2_fpgaio_reset(void) "MPS2 FPGAIO: reset"
112
113# msf2-sysreg.c
114msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" PRIx64 " data 0x%" PRIx32 " prev 0x%" PRIx32
115msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" PRIx64 " data 0x%08" PRIx32
116msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status register"
117
118# imx7_gpr.c
119imx7_gpr_read(uint64_t offset) "addr 0x%08" PRIx64
120imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" PRIx64 "value 0x%08" PRIx64
121
122# imx7_snvs.c
123imx7_snvs_read(uint64_t offset, uint64_t value, unsigned size) "i.MX SNVS read: offset 0x%08" PRIx64 " value 0x%08" PRIx64 " size %u"
124imx7_snvs_write(uint64_t offset, uint64_t value, unsigned size) "i.MX SNVS write: offset 0x%08" PRIx64 " value 0x%08" PRIx64 " size %u"
125
126# mos6522.c
127mos6522_set_counter(int index, unsigned int val) "T%d.counter=%d"
128mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d counter=0x%"PRIx64 " delta_next=0x%"PRIx64
129mos6522_set_sr_int(void) "set sr_int"
130mos6522_write(uint64_t addr, const char *name, uint64_t val) "reg=0x%"PRIx64 " [%s] val=0x%"PRIx64
131mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=0x%"PRIx64 " [%s] val=0x%x"
132
133# npcm7xx_clk.c
134npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
135npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
136
137# npcm7xx_gcr.c
138npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
139npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
140
141# npcm7xx_mft.c
142npcm7xx_mft_read(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16
143npcm7xx_mft_write(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16
144npcm7xx_mft_rpm(const char *clock, uint32_t clock_hz, int state, int32_t cnt, uint32_t rpm, uint32_t duty) " fan clk: %s clock_hz: %" PRIu32 ", state: %d, cnt: %" PRIi32 ", rpm: %" PRIu32 ", duty: %" PRIu32
145npcm7xx_mft_capture(const char *name, int irq_level) "%s: level: %d"
146npcm7xx_mft_update_clock(const char *name, uint16_t sel, uint64_t clock_period, uint64_t prescaled_clock_period) "%s: sel: 0x%02" PRIx16 ", period: %" PRIu64 ", prescaled: %" PRIu64
147npcm7xx_mft_set_duty(const char *name, int n, int value) "%s[%d]: %d"
148
149# npcm7xx_rng.c
150npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
151npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
152
153# npcm7xx_pwm.c
154npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
155npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
156npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u"
157npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u"
158
159# stm32_rcc.c
160stm32_rcc_read(uint64_t addr, uint64_t data) "reg read: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
161stm32_rcc_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
162stm32_rcc_pulse_enable(int line, int level) "Enable: %d to %d"
163stm32_rcc_pulse_reset(int line, int level) "Reset: %d to %d"
164
165# stm32f4xx_syscfg.c
166stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interrupt: GPIO: %d, Line: %d; Level: %d"
167stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
168stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
169stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
170
171# stm32f4xx_exti.c
172stm32f4xx_exti_set_irq(int irq, int level) "Set EXTI: %d to %d"
173stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
174stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
175
176# stm32l4x5_syscfg.c
177stm32l4x5_syscfg_set_irq(int gpio, int line, int level) "irq from GPIO: %d, line: %d, level: %d"
178stm32l4x5_syscfg_forward_exti(int irq) "irq %d forwarded to EXTI"
179stm32l4x5_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
180stm32l4x5_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
181
182# stm32l4x5_exti.c
183stm32l4x5_exti_set_irq(int irq, int level) "Set EXTI: %d to %d"
184stm32l4x5_exti_read(uint64_t addr, uint64_t data) "reg read: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
185stm32l4x5_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
186
187# stm32l4x5_rcc.c
188stm32l4x5_rcc_read(uint64_t addr, uint32_t data) "RCC: Read <0x%" PRIx64 "> -> 0x%" PRIx32
189stm32l4x5_rcc_write(uint64_t addr, uint32_t data) "RCC: Write <0x%" PRIx64 "> <- 0x%" PRIx32
190stm32l4x5_rcc_mux_enable(uint32_t mux_id) "RCC: Mux %d enabled"
191stm32l4x5_rcc_mux_disable(uint32_t mux_id) "RCC: Mux %d disabled"
192stm32l4x5_rcc_mux_set_factor(uint32_t mux_id, uint32_t old_multiplier, uint32_t new_multiplier, uint32_t old_divider, uint32_t new_divider) "RCC: Mux %d factor changed: multiplier (%u -> %u), divider (%u -> %u)"
193stm32l4x5_rcc_mux_set_src(uint32_t mux_id, uint32_t old_src, uint32_t new_src) "RCC: Mux %d source changed: from %u to %u"
194stm32l4x5_rcc_mux_update(uint32_t mux_id, uint32_t src, uint64_t src_freq, uint32_t multiplier, uint32_t divider) "RCC: Mux %d src %d update: src_freq %" PRIu64 " multiplier %" PRIu32 " divider %" PRIu32
195stm32l4x5_rcc_pll_set_vco_multiplier(uint32_t pll_id, uint32_t old_multiplier, uint32_t new_multiplier) "RCC: PLL %u: vco_multiplier changed (%u -> %u)"
196stm32l4x5_rcc_pll_channel_enable(uint32_t pll_id, uint32_t channel_id) "RCC: PLL %u, channel %u enabled"
197stm32l4x5_rcc_pll_channel_disable(uint32_t pll_id, uint32_t channel_id) "RCC: PLL %u, channel %u disabled"
198stm32l4x5_rcc_pll_set_channel_divider(uint32_t pll_id, uint32_t channel_id, uint32_t old_divider, uint32_t new_divider) "RCC: PLL %u, channel %u: divider changed (%u -> %u)"
199stm32l4x5_rcc_pll_update(uint32_t pll_id, uint32_t channel_id, uint64_t vco_freq, uint64_t old_freq, uint64_t new_freq) "RCC: PLL %d channel %d update: vco_freq %" PRIu64 " old_freq %" PRIu64 " new_freq %" PRIu64
200
201# tz-mpc.c
202tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u"
203tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u"
204tz_mpc_mem_blocked_read(uint64_t addr, unsigned size, bool secure) "TZ MPC blocked read: offset 0x%" PRIx64 " size %u secure %d"
205tz_mpc_mem_blocked_write(uint64_t addr, uint64_t data, unsigned size, bool secure) "TZ MPC blocked write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d"
206tz_mpc_translate(uint64_t addr, int flags, const char *idx, const char *res) "TZ MPC translate: addr 0x%" PRIx64 " flags 0x%x iommu_idx %s: %s"
207tz_mpc_iommu_notify(uint64_t addr) "TZ MPC iommu: notifying UNMAP/MAP for 0x%" PRIx64
208
209# tz-msc.c
210tz_msc_reset(void) "TZ MSC: reset"
211tz_msc_cfg_nonsec(int level) "TZ MSC: cfg_nonsec = %d"
212tz_msc_cfg_sec_resp(int level) "TZ MSC: cfg_sec_resp = %d"
213tz_msc_irq_clear(int level) "TZ MSC: int_clear = %d"
214tz_msc_update_irq(int level) "TZ MSC: setting irq line to %d"
215tz_msc_access_blocked(uint64_t offset) "TZ MSC: offset 0x%" PRIx64 " access blocked"
216
217# tz-ppc.c
218tz_ppc_reset(void) "TZ PPC: reset"
219tz_ppc_cfg_nonsec(int n, int level) "TZ PPC: cfg_nonsec[%d] = %d"
220tz_ppc_cfg_ap(int n, int level) "TZ PPC: cfg_ap[%d] = %d"
221tz_ppc_cfg_sec_resp(int level) "TZ PPC: cfg_sec_resp = %d"
222tz_ppc_irq_enable(int level) "TZ PPC: int_enable = %d"
223tz_ppc_irq_clear(int level) "TZ PPC: int_clear = %d"
224tz_ppc_update_irq(int level) "TZ PPC: setting irq line to %d"
225tz_ppc_read_blocked(int n, uint64_t offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" PRIx64 " read (secure %d user %d) blocked"
226tz_ppc_write_blocked(int n, uint64_t offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" PRIx64 " write (secure %d user %d) blocked"
227
228# iotkit-secctl.c
229iotkit_secctl_s_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs read: offset 0x%x data 0x%" PRIx64 " size %u"
230iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs write: offset 0x%x data 0x%" PRIx64 " size %u"
231iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u"
232iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u"
233
234# imx6_ccm.c
235imx6_analog_get_periph_clk(uint32_t freq) "freq = %u Hz"
236imx6_analog_get_pll2_clk(uint32_t freq) "freq = %u Hz"
237imx6_analog_get_pll2_pfd0_clk(uint32_t freq) "freq = %u Hz"
238imx6_analog_get_pll2_pfd2_clk(uint32_t freq) "freq = %u Hz"
239imx6_analog_read(const char *reg, uint32_t value) "reg[%s] => 0x%" PRIx32
240imx6_analog_write(const char *reg, uint32_t value) "reg[%s] <= 0x%" PRIx32
241imx6_ccm_get_ahb_clk(uint32_t freq) "freq = %u Hz"
242imx6_ccm_get_ipg_clk(uint32_t freq) "freq = %u Hz"
243imx6_ccm_get_per_clk(uint32_t freq) "freq = %u Hz"
244imx6_ccm_get_clock_frequency(unsigned clock, uint32_t freq) "(Clock = %d) = %u"
245imx6_ccm_read(const char *reg, uint32_t value) "reg[%s] => 0x%" PRIx32
246imx6_ccm_reset(void) ""
247imx6_ccm_write(const char *reg, uint32_t value) "reg[%s] <= 0x%" PRIx32
248
249# imx6ul_ccm.c
250ccm_entry(void) ""
251ccm_freq(uint32_t freq) "freq = %d"
252ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d"
253ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
254ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
255
256# imx7_src.c
257imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
258imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
259
260# iotkit-sysinfo.c
261iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
262iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
263
264# iotkit-sysctl.c
265iotkit_sysctl_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysCtl read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
266iotkit_sysctl_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysCtl write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
267iotkit_sysctl_reset(void) "IoTKit SysCtl: reset"
268
269# armsse-cpu-pwrctrl.c
270armsse_cpu_pwrctrl_read(uint64_t offset, uint64_t data, unsigned size) "SSE-300 CPU_PWRCTRL read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
271armsse_cpu_pwrctrl_write(uint64_t offset, uint64_t data, unsigned size) "SSE-300 CPU_PWRCTRL write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
272
273# armsse-cpuid.c
274armsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
275armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
276
277# armsse-mhu.c
278armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
279armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
280
281# aspeed_xdma.c
282aspeed_xdma_write(uint64_t offset, uint64_t data) "XDMA write: offset 0x%" PRIx64 " data 0x%" PRIx64
283
284# aspeed_i3c.c
285aspeed_i3c_read(uint64_t offset, uint64_t data) "I3C read: offset 0x%" PRIx64 " data 0x%" PRIx64
286aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64
287aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64
288aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64
289
290# aspeed_sdmc.c
291aspeed_sdmc_write(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64
292aspeed_sdmc_read(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64
293
294# aspeed_peci.c
295aspeed_peci_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64
296aspeed_peci_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64
297aspeed_peci_raise_interrupt(uint32_t ctrl, uint32_t status) "ctrl 0x%" PRIx32 " status 0x%" PRIx32
298
299# bcm2835_property.c
300bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbox property tag:0x%08x in_sz:%u out_sz:%zu"
301
302# bcm2835_mbox.c
303bcm2835_mbox_write(unsigned int size, uint64_t addr, uint64_t value) "mbox write sz:%u addr:0x%"PRIx64" data:0x%"PRIx64
304bcm2835_mbox_read(unsigned int size, uint64_t addr, uint64_t value) "mbox read sz:%u addr:0x%"PRIx64" data:0x%"PRIx64
305bcm2835_mbox_irq(unsigned level) "mbox irq:ARM level:%u"
306
307# mac_via.c
308via1_rtc_update_data_out(int count, int value) "count=%d value=0x%02x"
309via1_rtc_update_data_in(int count, int value) "count=%d value=0x%02x"
310via1_rtc_internal_status(int cmd, int alt, int value) "cmd=0x%02x alt=0x%02x value=0x%02x"
311via1_rtc_internal_cmd(int cmd) "cmd=0x%02x"
312via1_rtc_cmd_invalid(int value) "value=0x%02x"
313via1_rtc_internal_time(uint32_t time) "time=0x%08x"
314via1_rtc_internal_set_cmd(int cmd) "cmd=0x%02x"
315via1_rtc_internal_ignore_cmd(int cmd) "cmd=0x%02x"
316via1_rtc_internal_set_alt(int alt, int sector, int offset) "alt=0x%02x sector=%u offset=%u"
317via1_rtc_cmd_seconds_read(int reg, int value) "reg=%d value=0x%02x"
318via1_rtc_cmd_seconds_write(int reg, int value) "reg=%d value=0x%02x"
319via1_rtc_cmd_test_write(int value) "value=0x%02x"
320via1_rtc_cmd_wprotect_write(int value) "value=0x%02x"
321via1_rtc_cmd_pram_read(int addr, int value) "addr=%u value=0x%02x"
322via1_rtc_cmd_pram_write(int addr, int value) "addr=%u value=0x%02x"
323via1_rtc_cmd_pram_sect_read(int sector, int offset, int addr, int value) "sector=%u offset=%u addr=0x%x value=0x%02x"
324via1_rtc_cmd_pram_sect_write(int sector, int offset, int addr, int value) "sector=%u offset=%u addr=0x%x value=0x%02x"
325via1_adb_send(const char *state, uint8_t data, const char *vadbint) "state %s data=0x%02x vADBInt=%s"
326via1_adb_receive(const char *state, uint8_t data, const char *vadbint, int status, int index, int size) "state %s data=0x%02x vADBInt=%s status=0x%x index=%d size=%d"
327via1_adb_poll(uint8_t data, const char *vadbint, int status, int index, int size) "data=0x%02x vADBInt=%s status=0x%x index=%d size=%d"
328via1_adb_netbsd_enum_hack(void) "using NetBSD enum hack"
329via1_auxmode(int mode) "setting auxmode to %d"
330via1_timer_hack_state(int state) "setting timer_hack_state to %d"
331
332# grlib_ahb_apb_pnp.c
333grlib_ahb_pnp_read(uint64_t addr, unsigned size, uint32_t value) "AHB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x"
334grlib_apb_pnp_read(uint64_t addr, unsigned size, uint32_t value) "APB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x"
335
336# led.c
337led_set_intensity(const char *color, const char *desc, uint8_t intensity_percent) "LED desc:'%s' color:%s intensity: %u%%"
338led_change_intensity(const char *color, const char *desc, uint8_t old_intensity_percent, uint8_t new_intensity_percent) "LED desc:'%s' color:%s intensity %u%% -> %u%%"
339
340# bcm2835_cprman.c
341bcm2835_cprman_read(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64
342bcm2835_cprman_write(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64
343bcm2835_cprman_write_invalid_magic(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64
344
345# virt_ctrl.c
346virt_ctrl_read(void *dev, unsigned int addr, unsigned int size, uint64_t value) "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64
347virt_ctrl_write(void *dev, unsigned int addr, unsigned int size, uint64_t value) "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64
348virt_ctrl_reset(void *dev) "ctrl: %p"
349virt_ctrl_realize(void *dev) "ctrl: %p"
350virt_ctrl_instance_init(void *dev) "ctrl: %p"
351
352# lasi.c
353lasi_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64" is %d"
354lasi_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
355lasi_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
356
357# djmemc.c
358djmemc_read(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u"
359djmemc_write(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u"
360
361# iosb.c
362iosb_read(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u"
363iosb_write(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u"
364
365# aspeed_sli.c
366aspeed_sli_write(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
367aspeed_sli_read(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
368aspeed_sliio_write(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
369aspeed_sliio_read(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
370
371