xref: /openbmc/qemu/hw/misc/trace-events (revision 53c7c924)
1# See docs/devel/tracing.rst for syntax documentation.
2
3# allwinner-cpucfg.c
4allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_addr 0x%" PRIx32
5allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
6allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
7
8# allwinner-h3-dramc.c
9allwinner_h3_dramc_rowmirror_disable(void) "Disable row mirror"
10allwinner_h3_dramc_rowmirror_enable(uint64_t addr) "Enable row mirror: addr 0x%" PRIx64
11allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
12allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
13allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
14allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
15allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
16allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
17
18# allwinner-r40-dramc.c
19allwinner_r40_dramc_detect_cells_disable(void) "Disable detect cells"
20allwinner_r40_dramc_detect_cells_enable(void) "Enable detect cells"
21allwinner_r40_dramc_map_rows(uint8_t row_bits, uint8_t bank_bits, uint8_t col_bits) "DRAM layout: row_bits %d, bank_bits %d, col_bits %d"
22allwinner_r40_dramc_offset_to_cell(uint64_t offset, int row, int bank, int col) "offset 0x%" PRIx64 " row %d bank %d col %d"
23allwinner_r40_dramc_detect_cell_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 ""
24allwinner_r40_dramc_detect_cell_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 ""
25allwinner_r40_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
26allwinner_r40_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
27allwinner_r40_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
28allwinner_r40_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
29allwinner_r40_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
30allwinner_r40_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
31
32# allwinner-sid.c
33allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
34allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
35
36# allwinner-sramc.c
37allwinner_sramc_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64
38allwinner_sramc_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64
39
40# avr_power.c
41avr_power_read(uint8_t value) "power_reduc read value:%u"
42avr_power_write(uint8_t value) "power_reduc write value:%u"
43
44# axp2xx
45axp2xx_rx(uint8_t reg, uint8_t data) "Read reg 0x%" PRIx8 " : 0x%" PRIx8
46axp2xx_select(uint8_t reg) "Accessing reg 0x%" PRIx8
47axp2xx_tx(uint8_t reg, uint8_t data) "Write reg 0x%" PRIx8 " : 0x%" PRIx8
48
49# eccmemctl.c
50ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
51ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"
52ecc_mem_writel_mfsr(uint32_t val) "Write memory fault status 0x%08x"
53ecc_mem_writel_vcr(uint32_t val) "Write slot configuration 0x%08x"
54ecc_mem_writel_dr(uint32_t val) "Write diagnostic 0x%08x"
55ecc_mem_writel_ecr0(uint32_t val) "Write event count 1 0x%08x"
56ecc_mem_writel_ecr1(uint32_t val) "Write event count 2 0x%08x"
57ecc_mem_readl_mer(uint32_t ret) "Read memory enable 0x%08x"
58ecc_mem_readl_mdr(uint32_t ret) "Read memory delay 0x%08x"
59ecc_mem_readl_mfsr(uint32_t ret) "Read memory fault status 0x%08x"
60ecc_mem_readl_vcr(uint32_t ret) "Read slot configuration 0x%08x"
61ecc_mem_readl_mfar0(uint32_t ret) "Read memory fault address 0 0x%08x"
62ecc_mem_readl_mfar1(uint32_t ret) "Read memory fault address 1 0x%08x"
63ecc_mem_readl_dr(uint32_t ret) "Read diagnostic 0x%08x"
64ecc_mem_readl_ecr0(uint32_t ret) "Read event count 1 0x%08x"
65ecc_mem_readl_ecr1(uint32_t ret) "Read event count 2 0x%08x"
66ecc_diag_mem_writeb(uint64_t addr, uint32_t val) "Write diagnostic %"PRId64" = 0x%02x"
67ecc_diag_mem_readb(uint64_t addr, uint32_t ret) "Read diagnostic %"PRId64"= 0x%02x"
68
69# empty_slot.c
70empty_slot_write(uint64_t addr, unsigned width, uint64_t value, unsigned size, const char *name) "wr addr:0x%04"PRIx64" data:0x%0*"PRIx64" size %u [%s]"
71
72# slavio_misc.c
73slavio_misc_update_irq_raise(void) "Raise IRQ"
74slavio_misc_update_irq_lower(void) "Lower IRQ"
75slavio_set_power_fail(int power_failing, uint8_t config) "Power fail: %d, config: %d"
76slavio_cfg_mem_writeb(uint32_t val) "Write config 0x%02x"
77slavio_cfg_mem_readb(uint32_t ret) "Read config 0x%02x"
78slavio_diag_mem_writeb(uint32_t val) "Write diag 0x%02x"
79slavio_diag_mem_readb(uint32_t ret) "Read diag 0x%02x"
80slavio_mdm_mem_writeb(uint32_t val) "Write modem control 0x%02x"
81slavio_mdm_mem_readb(uint32_t ret) "Read modem control 0x%02x"
82slavio_aux1_mem_writeb(uint32_t val) "Write aux1 0x%02x"
83slavio_aux1_mem_readb(uint32_t ret) "Read aux1 0x%02x"
84slavio_aux2_mem_writeb(uint32_t val) "Write aux2 0x%02x"
85slavio_aux2_mem_readb(uint32_t ret) "Read aux2 0x%02x"
86apc_mem_writeb(uint32_t val) "Write power management 0x%02x"
87apc_mem_readb(uint32_t ret) "Read power management 0x%02x"
88slavio_sysctrl_mem_writel(uint32_t val) "Write system control 0x%08x"
89slavio_sysctrl_mem_readl(uint32_t ret) "Read system control 0x%08x"
90slavio_led_mem_writew(uint32_t val) "Write diagnostic LED 0x%04x"
91slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED 0x%04x"
92
93# aspeed_scu.c
94aspeed_scu_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
95aspeed_scu_read(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
96
97# mps2-scc.c
98mps2_scc_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 SCC read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
99mps2_scc_write(uint64_t offset, uint64_t data, unsigned size) "MPS2 SCC write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
100mps2_scc_reset(void) "MPS2 SCC: reset"
101mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config write: function %d device %d data 0x%" PRIx32
102mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config read: function %d device %d data 0x%" PRIx32
103
104# mps2-fpgaio.c
105mps2_fpgaio_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
106mps2_fpgaio_write(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
107mps2_fpgaio_reset(void) "MPS2 FPGAIO: reset"
108
109# msf2-sysreg.c
110msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" PRIx64 " data 0x%" PRIx32 " prev 0x%" PRIx32
111msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" PRIx64 " data 0x%08" PRIx32
112msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status register"
113
114# imx7_gpr.c
115imx7_gpr_read(uint64_t offset) "addr 0x%08" PRIx64
116imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" PRIx64 "value 0x%08" PRIx64
117
118# mos6522.c
119mos6522_set_counter(int index, unsigned int val) "T%d.counter=%d"
120mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d counter=0x%"PRIx64 " delta_next=0x%"PRIx64
121mos6522_set_sr_int(void) "set sr_int"
122mos6522_write(uint64_t addr, const char *name, uint64_t val) "reg=0x%"PRIx64 " [%s] val=0x%"PRIx64
123mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=0x%"PRIx64 " [%s] val=0x%x"
124
125# npcm7xx_clk.c
126npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
127npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
128
129# npcm7xx_gcr.c
130npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
131npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
132
133# npcm7xx_mft.c
134npcm7xx_mft_read(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16
135npcm7xx_mft_write(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16
136npcm7xx_mft_rpm(const char *clock, uint32_t clock_hz, int state, int32_t cnt, uint32_t rpm, uint32_t duty) " fan clk: %s clock_hz: %" PRIu32 ", state: %d, cnt: %" PRIi32 ", rpm: %" PRIu32 ", duty: %" PRIu32
137npcm7xx_mft_capture(const char *name, int irq_level) "%s: level: %d"
138npcm7xx_mft_update_clock(const char *name, uint16_t sel, uint64_t clock_period, uint64_t prescaled_clock_period) "%s: sel: 0x%02" PRIx16 ", period: %" PRIu64 ", prescaled: %" PRIu64
139npcm7xx_mft_set_duty(const char *name, int n, int value) "%s[%d]: %d"
140
141# npcm7xx_rng.c
142npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
143npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
144
145# npcm7xx_pwm.c
146npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
147npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
148npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u"
149npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u"
150
151# stm32f4xx_syscfg.c
152stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interrupt: GPIO: %d, Line: %d; Level: %d"
153stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
154stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
155stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
156
157# stm32f4xx_exti.c
158stm32f4xx_exti_set_irq(int irq, int leve) "Set EXTI: %d to %d"
159stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
160stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
161
162# tz-mpc.c
163tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u"
164tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u"
165tz_mpc_mem_blocked_read(uint64_t addr, unsigned size, bool secure) "TZ MPC blocked read: offset 0x%" PRIx64 " size %u secure %d"
166tz_mpc_mem_blocked_write(uint64_t addr, uint64_t data, unsigned size, bool secure) "TZ MPC blocked write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d"
167tz_mpc_translate(uint64_t addr, int flags, const char *idx, const char *res) "TZ MPC translate: addr 0x%" PRIx64 " flags 0x%x iommu_idx %s: %s"
168tz_mpc_iommu_notify(uint64_t addr) "TZ MPC iommu: notifying UNMAP/MAP for 0x%" PRIx64
169
170# tz-msc.c
171tz_msc_reset(void) "TZ MSC: reset"
172tz_msc_cfg_nonsec(int level) "TZ MSC: cfg_nonsec = %d"
173tz_msc_cfg_sec_resp(int level) "TZ MSC: cfg_sec_resp = %d"
174tz_msc_irq_clear(int level) "TZ MSC: int_clear = %d"
175tz_msc_update_irq(int level) "TZ MSC: setting irq line to %d"
176tz_msc_access_blocked(uint64_t offset) "TZ MSC: offset 0x%" PRIx64 " access blocked"
177
178# tz-ppc.c
179tz_ppc_reset(void) "TZ PPC: reset"
180tz_ppc_cfg_nonsec(int n, int level) "TZ PPC: cfg_nonsec[%d] = %d"
181tz_ppc_cfg_ap(int n, int level) "TZ PPC: cfg_ap[%d] = %d"
182tz_ppc_cfg_sec_resp(int level) "TZ PPC: cfg_sec_resp = %d"
183tz_ppc_irq_enable(int level) "TZ PPC: int_enable = %d"
184tz_ppc_irq_clear(int level) "TZ PPC: int_clear = %d"
185tz_ppc_update_irq(int level) "TZ PPC: setting irq line to %d"
186tz_ppc_read_blocked(int n, uint64_t offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" PRIx64 " read (secure %d user %d) blocked"
187tz_ppc_write_blocked(int n, uint64_t offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" PRIx64 " write (secure %d user %d) blocked"
188
189# iotkit-secctl.c
190iotkit_secctl_s_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs read: offset 0x%x data 0x%" PRIx64 " size %u"
191iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs write: offset 0x%x data 0x%" PRIx64 " size %u"
192iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u"
193iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u"
194
195# imx6ul_ccm.c
196ccm_entry(void) ""
197ccm_freq(uint32_t freq) "freq = %d"
198ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d"
199ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
200ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
201
202# imx7_src.c
203imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
204imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
205
206# iotkit-sysinfo.c
207iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
208iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
209
210# iotkit-sysctl.c
211iotkit_sysctl_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysCtl read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
212iotkit_sysctl_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysCtl write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
213iotkit_sysctl_reset(void) "IoTKit SysCtl: reset"
214
215# armsse-cpu-pwrctrl.c
216armsse_cpu_pwrctrl_read(uint64_t offset, uint64_t data, unsigned size) "SSE-300 CPU_PWRCTRL read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
217armsse_cpu_pwrctrl_write(uint64_t offset, uint64_t data, unsigned size) "SSE-300 CPU_PWRCTRL write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
218
219# armsse-cpuid.c
220armsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
221armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
222
223# armsse-mhu.c
224armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
225armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
226
227# aspeed_xdma.c
228aspeed_xdma_write(uint64_t offset, uint64_t data) "XDMA write: offset 0x%" PRIx64 " data 0x%" PRIx64
229
230# aspeed_i3c.c
231aspeed_i3c_read(uint64_t offset, uint64_t data) "I3C read: offset 0x%" PRIx64 " data 0x%" PRIx64
232aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64
233aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64
234aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64
235
236# aspeed_sdmc.c
237aspeed_sdmc_write(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64
238aspeed_sdmc_read(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64
239
240# aspeed_peci.c
241aspeed_peci_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64
242aspeed_peci_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64
243aspeed_peci_raise_interrupt(uint32_t ctrl, uint32_t status) "ctrl 0x%" PRIx32 " status 0x%" PRIx32
244
245# bcm2835_property.c
246bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbox property tag:0x%08x in_sz:%u out_sz:%zu"
247
248# bcm2835_mbox.c
249bcm2835_mbox_write(unsigned int size, uint64_t addr, uint64_t value) "mbox write sz:%u addr:0x%"PRIx64" data:0x%"PRIx64
250bcm2835_mbox_read(unsigned int size, uint64_t addr, uint64_t value) "mbox read sz:%u addr:0x%"PRIx64" data:0x%"PRIx64
251bcm2835_mbox_irq(unsigned level) "mbox irq:ARM level:%u"
252
253# mac_via.c
254via1_rtc_update_data_out(int count, int value) "count=%d value=0x%02x"
255via1_rtc_update_data_in(int count, int value) "count=%d value=0x%02x"
256via1_rtc_internal_status(int cmd, int alt, int value) "cmd=0x%02x alt=0x%02x value=0x%02x"
257via1_rtc_internal_cmd(int cmd) "cmd=0x%02x"
258via1_rtc_cmd_invalid(int value) "value=0x%02x"
259via1_rtc_internal_time(uint32_t time) "time=0x%08x"
260via1_rtc_internal_set_cmd(int cmd) "cmd=0x%02x"
261via1_rtc_internal_ignore_cmd(int cmd) "cmd=0x%02x"
262via1_rtc_internal_set_alt(int alt, int sector, int offset) "alt=0x%02x sector=%u offset=%u"
263via1_rtc_cmd_seconds_read(int reg, int value) "reg=%d value=0x%02x"
264via1_rtc_cmd_seconds_write(int reg, int value) "reg=%d value=0x%02x"
265via1_rtc_cmd_test_write(int value) "value=0x%02x"
266via1_rtc_cmd_wprotect_write(int value) "value=0x%02x"
267via1_rtc_cmd_pram_read(int addr, int value) "addr=%u value=0x%02x"
268via1_rtc_cmd_pram_write(int addr, int value) "addr=%u value=0x%02x"
269via1_rtc_cmd_pram_sect_read(int sector, int offset, int addr, int value) "sector=%u offset=%u addr=0x%x value=0x%02x"
270via1_rtc_cmd_pram_sect_write(int sector, int offset, int addr, int value) "sector=%u offset=%u addr=0x%x value=0x%02x"
271via1_adb_send(const char *state, uint8_t data, const char *vadbint) "state %s data=0x%02x vADBInt=%s"
272via1_adb_receive(const char *state, uint8_t data, const char *vadbint, int status, int index, int size) "state %s data=0x%02x vADBInt=%s status=0x%x index=%d size=%d"
273via1_adb_poll(uint8_t data, const char *vadbint, int status, int index, int size) "data=0x%02x vADBInt=%s status=0x%x index=%d size=%d"
274via1_auxmode(int mode) "setting auxmode to %d"
275
276# grlib_ahb_apb_pnp.c
277grlib_ahb_pnp_read(uint64_t addr, unsigned size, uint32_t value) "AHB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x"
278grlib_apb_pnp_read(uint64_t addr, unsigned size, uint32_t value) "APB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x"
279
280# led.c
281led_set_intensity(const char *color, const char *desc, uint8_t intensity_percent) "LED desc:'%s' color:%s intensity: %u%%"
282led_change_intensity(const char *color, const char *desc, uint8_t old_intensity_percent, uint8_t new_intensity_percent) "LED desc:'%s' color:%s intensity %u%% -> %u%%"
283
284# pca9552.c
285pca955x_gpio_status(const char *description, const char *buf) "%s GPIOs 0-15 [%s]"
286pca955x_gpio_change(const char *description, unsigned id, unsigned prev_state, unsigned current_state) "%s GPIO id:%u status: %u -> %u"
287
288# bcm2835_cprman.c
289bcm2835_cprman_read(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64
290bcm2835_cprman_write(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64
291bcm2835_cprman_write_invalid_magic(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64
292
293# virt_ctrl.c
294virt_ctrl_read(void *dev, unsigned int addr, unsigned int size, uint64_t value) "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64
295virt_ctrl_write(void *dev, unsigned int addr, unsigned int size, uint64_t value) "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64
296virt_ctrl_reset(void *dev) "ctrl: %p"
297virt_ctrl_realize(void *dev) "ctrl: %p"
298virt_ctrl_instance_init(void *dev) "ctrl: %p"
299
300# lasi.c
301lasi_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64" is %d"
302lasi_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
303lasi_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
304