1 /* 2 * STM32L4x5 SYSCFG (System Configuration Controller) 3 * 4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr> 5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr> 6 * 7 * SPDX-License-Identifier: GPL-2.0-or-later 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * This work is based on the stm32f4xx_syscfg by Alistair Francis. 13 * Original code is licensed under the MIT License: 14 * 15 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 16 */ 17 18 /* 19 * The reference used is the STMicroElectronics RM0351 Reference manual 20 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. 21 * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qemu/log.h" 26 #include "trace.h" 27 #include "hw/irq.h" 28 #include "migration/vmstate.h" 29 #include "hw/misc/stm32l4x5_syscfg.h" 30 31 #define SYSCFG_MEMRMP 0x00 32 #define SYSCFG_CFGR1 0x04 33 #define SYSCFG_EXTICR1 0x08 34 #define SYSCFG_EXTICR2 0x0C 35 #define SYSCFG_EXTICR3 0x10 36 #define SYSCFG_EXTICR4 0x14 37 #define SYSCFG_SCSR 0x18 38 #define SYSCFG_CFGR2 0x1C 39 #define SYSCFG_SWPR 0x20 40 #define SYSCFG_SKR 0x24 41 #define SYSCFG_SWPR2 0x28 42 43 /* 00000000_00000000_00000001_00000111 */ 44 #define ACTIVABLE_BITS_MEMRP 0x00000107 45 46 /* 11111100_11111111_00000001_00000000 */ 47 #define ACTIVABLE_BITS_CFGR1 0xFCFF0100 48 /* 00000000_00000000_00000000_00000001 */ 49 #define FIREWALL_DISABLE_CFGR1 0x00000001 50 51 /* 00000000_00000000_11111111_11111111 */ 52 #define ACTIVABLE_BITS_EXTICR 0x0000FFFF 53 54 /* 00000000_00000000_00000000_00000011 */ 55 /* #define ACTIVABLE_BITS_SCSR 0x00000003 */ 56 57 /* 00000000_00000000_00000000_00001111 */ 58 #define ECC_LOCK_CFGR2 0x0000000F 59 /* 00000000_00000000_00000001_00000000 */ 60 #define SRAM2_PARITY_ERROR_FLAG_CFGR2 0x00000100 61 62 /* 00000000_00000000_00000000_11111111 */ 63 #define ACTIVABLE_BITS_SKR 0x000000FF 64 65 #define NUM_LINES_PER_EXTICR_REG 4 66 67 static void stm32l4x5_syscfg_hold_reset(Object *obj) 68 { 69 Stm32l4x5SyscfgState *s = STM32L4X5_SYSCFG(obj); 70 71 s->memrmp = 0x00000000; 72 s->cfgr1 = 0x7C000001; 73 s->exticr[0] = 0x00000000; 74 s->exticr[1] = 0x00000000; 75 s->exticr[2] = 0x00000000; 76 s->exticr[3] = 0x00000000; 77 s->scsr = 0x00000000; 78 s->cfgr2 = 0x00000000; 79 s->swpr = 0x00000000; 80 s->skr = 0x00000000; 81 s->swpr2 = 0x00000000; 82 } 83 84 static void stm32l4x5_syscfg_set_irq(void *opaque, int irq, int level) 85 { 86 Stm32l4x5SyscfgState *s = opaque; 87 const uint8_t gpio = irq / GPIO_NUM_PINS; 88 const int line = irq % GPIO_NUM_PINS; 89 90 const int exticr_reg = line / NUM_LINES_PER_EXTICR_REG; 91 const int startbit = (line % NUM_LINES_PER_EXTICR_REG) * 4; 92 93 g_assert(gpio < NUM_GPIOS); 94 trace_stm32l4x5_syscfg_set_irq(gpio, line, level); 95 96 if (extract32(s->exticr[exticr_reg], startbit, 4) == gpio) { 97 trace_stm32l4x5_syscfg_forward_exti(line); 98 qemu_set_irq(s->gpio_out[line], level); 99 } 100 } 101 102 static uint64_t stm32l4x5_syscfg_read(void *opaque, hwaddr addr, 103 unsigned int size) 104 { 105 Stm32l4x5SyscfgState *s = opaque; 106 107 trace_stm32l4x5_syscfg_read(addr); 108 109 switch (addr) { 110 case SYSCFG_MEMRMP: 111 return s->memrmp; 112 case SYSCFG_CFGR1: 113 return s->cfgr1; 114 case SYSCFG_EXTICR1...SYSCFG_EXTICR4: 115 return s->exticr[(addr - SYSCFG_EXTICR1) / 4]; 116 case SYSCFG_SCSR: 117 return s->scsr; 118 case SYSCFG_CFGR2: 119 return s->cfgr2; 120 case SYSCFG_SWPR: 121 return s->swpr; 122 case SYSCFG_SKR: 123 return s->skr; 124 case SYSCFG_SWPR2: 125 return s->swpr2; 126 default: 127 qemu_log_mask(LOG_GUEST_ERROR, 128 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr); 129 return 0; 130 } 131 } 132 static void stm32l4x5_syscfg_write(void *opaque, hwaddr addr, 133 uint64_t value, unsigned int size) 134 { 135 Stm32l4x5SyscfgState *s = opaque; 136 137 trace_stm32l4x5_syscfg_write(addr, value); 138 139 switch (addr) { 140 case SYSCFG_MEMRMP: 141 qemu_log_mask(LOG_UNIMP, 142 "%s: Changing the memory mapping isn't supported\n", 143 __func__); 144 s->memrmp = value & ACTIVABLE_BITS_MEMRP; 145 return; 146 case SYSCFG_CFGR1: 147 qemu_log_mask(LOG_UNIMP, 148 "%s: Functions in CFGRx aren't supported\n", 149 __func__); 150 /* bit 0 (firewall dis.) is cleared by software, set only by reset. */ 151 s->cfgr1 = (s->cfgr1 & value & FIREWALL_DISABLE_CFGR1) | 152 (value & ACTIVABLE_BITS_CFGR1); 153 return; 154 case SYSCFG_EXTICR1...SYSCFG_EXTICR4: 155 s->exticr[(addr - SYSCFG_EXTICR1) / 4] = 156 (value & ACTIVABLE_BITS_EXTICR); 157 return; 158 case SYSCFG_SCSR: 159 qemu_log_mask(LOG_UNIMP, 160 "%s: Erasing SRAM2 isn't supported\n", 161 __func__); 162 /* 163 * only non reserved bits are : 164 * bit 0 (write-protected by a passkey), bit 1 (meant to be read) 165 * so it serves no purpose yet to add : 166 * s->scsr = value & 0x3; 167 */ 168 return; 169 case SYSCFG_CFGR2: 170 qemu_log_mask(LOG_UNIMP, 171 "%s: Functions in CFGRx aren't supported\n", 172 __func__); 173 /* bit 8 (SRAM2 PEF) is cleared by software by writing a '1'.*/ 174 /* bits[3:0] (ECC Lock) are set by software, cleared only by reset.*/ 175 s->cfgr2 = (s->cfgr2 | (value & ECC_LOCK_CFGR2)) & 176 ~(value & SRAM2_PARITY_ERROR_FLAG_CFGR2); 177 return; 178 case SYSCFG_SWPR: 179 qemu_log_mask(LOG_UNIMP, 180 "%s: Write protecting SRAM2 isn't supported\n", 181 __func__); 182 /* These bits are set by software and cleared only by reset.*/ 183 s->swpr |= value; 184 return; 185 case SYSCFG_SKR: 186 qemu_log_mask(LOG_UNIMP, 187 "%s: Erasing SRAM2 isn't supported\n", 188 __func__); 189 s->skr = value & ACTIVABLE_BITS_SKR; 190 return; 191 case SYSCFG_SWPR2: 192 qemu_log_mask(LOG_UNIMP, 193 "%s: Write protecting SRAM2 isn't supported\n", 194 __func__); 195 /* These bits are set by software and cleared only by reset.*/ 196 s->swpr2 |= value; 197 return; 198 default: 199 qemu_log_mask(LOG_GUEST_ERROR, 200 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr); 201 } 202 } 203 204 static const MemoryRegionOps stm32l4x5_syscfg_ops = { 205 .read = stm32l4x5_syscfg_read, 206 .write = stm32l4x5_syscfg_write, 207 .endianness = DEVICE_NATIVE_ENDIAN, 208 .impl.min_access_size = 4, 209 .impl.max_access_size = 4, 210 .impl.unaligned = false, 211 .valid.min_access_size = 4, 212 .valid.max_access_size = 4, 213 .valid.unaligned = false, 214 }; 215 216 static void stm32l4x5_syscfg_init(Object *obj) 217 { 218 Stm32l4x5SyscfgState *s = STM32L4X5_SYSCFG(obj); 219 220 memory_region_init_io(&s->mmio, obj, &stm32l4x5_syscfg_ops, s, 221 TYPE_STM32L4X5_SYSCFG, 0x400); 222 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 223 224 qdev_init_gpio_in(DEVICE(obj), stm32l4x5_syscfg_set_irq, 225 GPIO_NUM_PINS * NUM_GPIOS); 226 qdev_init_gpio_out(DEVICE(obj), s->gpio_out, GPIO_NUM_PINS); 227 } 228 229 static const VMStateDescription vmstate_stm32l4x5_syscfg = { 230 .name = TYPE_STM32L4X5_SYSCFG, 231 .version_id = 1, 232 .minimum_version_id = 1, 233 .fields = (VMStateField[]) { 234 VMSTATE_UINT32(memrmp, Stm32l4x5SyscfgState), 235 VMSTATE_UINT32(cfgr1, Stm32l4x5SyscfgState), 236 VMSTATE_UINT32_ARRAY(exticr, Stm32l4x5SyscfgState, 237 SYSCFG_NUM_EXTICR), 238 VMSTATE_UINT32(scsr, Stm32l4x5SyscfgState), 239 VMSTATE_UINT32(cfgr2, Stm32l4x5SyscfgState), 240 VMSTATE_UINT32(swpr, Stm32l4x5SyscfgState), 241 VMSTATE_UINT32(skr, Stm32l4x5SyscfgState), 242 VMSTATE_UINT32(swpr2, Stm32l4x5SyscfgState), 243 VMSTATE_END_OF_LIST() 244 } 245 }; 246 247 static void stm32l4x5_syscfg_class_init(ObjectClass *klass, void *data) 248 { 249 DeviceClass *dc = DEVICE_CLASS(klass); 250 ResettableClass *rc = RESETTABLE_CLASS(klass); 251 252 dc->vmsd = &vmstate_stm32l4x5_syscfg; 253 rc->phases.hold = stm32l4x5_syscfg_hold_reset; 254 } 255 256 static const TypeInfo stm32l4x5_syscfg_info[] = { 257 { 258 .name = TYPE_STM32L4X5_SYSCFG, 259 .parent = TYPE_SYS_BUS_DEVICE, 260 .instance_size = sizeof(Stm32l4x5SyscfgState), 261 .instance_init = stm32l4x5_syscfg_init, 262 .class_init = stm32l4x5_syscfg_class_init, 263 } 264 }; 265 266 DEFINE_TYPES(stm32l4x5_syscfg_info) 267