1 /*
2 * STM32L4X5 RCC (Reset and clock control)
3 *
4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
6 *
7 * SPDX-License-Identifier: GPL-2.0-or-later
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
11 *
12 * The reference used is the STMicroElectronics RM0351 Reference manual
13 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
14 *
15 * Inspired by the BCM2835 CPRMAN clock manager implementation by Luc Michel.
16 */
17
18 #include "qemu/osdep.h"
19 #include "qemu/log.h"
20 #include "qemu/module.h"
21 #include "qemu/timer.h"
22 #include "qapi/error.h"
23 #include "migration/vmstate.h"
24 #include "hw/misc/stm32l4x5_rcc.h"
25 #include "hw/misc/stm32l4x5_rcc_internals.h"
26 #include "hw/clock.h"
27 #include "hw/irq.h"
28 #include "hw/qdev-clock.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-properties-system.h"
31 #include "hw/registerfields.h"
32 #include "trace.h"
33
34 #define HSE_DEFAULT_FRQ 48000000ULL
35 #define HSI_FRQ 16000000ULL
36 #define MSI_DEFAULT_FRQ 4000000ULL
37 #define LSE_FRQ 32768ULL
38 #define LSI_FRQ 32000ULL
39
40 /*
41 * Function to simply acknowledge and propagate changes in a clock mux
42 * frequency.
43 * `bypass_source` allows to bypass the period of the current source and just
44 * consider it equal to 0. This is useful during the hold phase of reset.
45 */
clock_mux_update(RccClockMuxState * mux,bool bypass_source)46 static void clock_mux_update(RccClockMuxState *mux, bool bypass_source)
47 {
48 uint64_t src_freq;
49 Clock *current_source = mux->srcs[mux->src];
50 uint32_t freq_multiplier = 0;
51 bool clk_changed = false;
52
53 /*
54 * To avoid rounding errors, we use the clock period instead of the
55 * frequency.
56 * This means that the multiplier of the mux becomes the divider of
57 * the clock and the divider of the mux becomes the multiplier of the
58 * clock.
59 */
60 if (!bypass_source && mux->enabled && mux->divider) {
61 freq_multiplier = mux->divider;
62 }
63
64 clk_changed |= clock_set_mul_div(mux->out, freq_multiplier, mux->multiplier);
65 clk_changed |= clock_set(mux->out, clock_get(current_source));
66 if (clk_changed) {
67 clock_propagate(mux->out);
68 }
69
70 src_freq = clock_get_hz(current_source);
71 /* TODO: can we simply detect if the config changed so that we reduce log spam ? */
72 trace_stm32l4x5_rcc_mux_update(mux->id, mux->src, src_freq,
73 mux->multiplier, mux->divider);
74 }
75
clock_mux_src_update(void * opaque,ClockEvent event)76 static void clock_mux_src_update(void *opaque, ClockEvent event)
77 {
78 RccClockMuxState **backref = opaque;
79 RccClockMuxState *s = *backref;
80 /*
81 * The backref value is equal to:
82 * s->backref + (sizeof(RccClockMuxState *) * update_src).
83 * By subtracting we can get back the index of the updated clock.
84 */
85 const uint32_t update_src = backref - s->backref;
86 /* Only update if the clock that was updated is the current source */
87 if (update_src == s->src) {
88 clock_mux_update(s, false);
89 }
90 }
91
clock_mux_init(Object * obj)92 static void clock_mux_init(Object *obj)
93 {
94 RccClockMuxState *s = RCC_CLOCK_MUX(obj);
95 size_t i;
96
97 for (i = 0; i < RCC_NUM_CLOCK_MUX_SRC; i++) {
98 char *name = g_strdup_printf("srcs[%zu]", i);
99 s->backref[i] = s;
100 s->srcs[i] = qdev_init_clock_in(DEVICE(s), name,
101 clock_mux_src_update,
102 &s->backref[i],
103 ClockUpdate);
104 g_free(name);
105 }
106
107 s->out = qdev_init_clock_out(DEVICE(s), "out");
108 }
109
clock_mux_reset_enter(Object * obj,ResetType type)110 static void clock_mux_reset_enter(Object *obj, ResetType type)
111 {
112 RccClockMuxState *s = RCC_CLOCK_MUX(obj);
113 set_clock_mux_init_info(s, s->id);
114 }
115
clock_mux_reset_hold(Object * obj,ResetType type)116 static void clock_mux_reset_hold(Object *obj, ResetType type)
117 {
118 RccClockMuxState *s = RCC_CLOCK_MUX(obj);
119 clock_mux_update(s, true);
120 }
121
clock_mux_reset_exit(Object * obj,ResetType type)122 static void clock_mux_reset_exit(Object *obj, ResetType type)
123 {
124 RccClockMuxState *s = RCC_CLOCK_MUX(obj);
125 clock_mux_update(s, false);
126 }
127
128 static const VMStateDescription clock_mux_vmstate = {
129 .name = TYPE_RCC_CLOCK_MUX,
130 .version_id = 1,
131 .minimum_version_id = 1,
132 .fields = (VMStateField[]) {
133 VMSTATE_UINT32(id, RccClockMuxState),
134 VMSTATE_ARRAY_CLOCK(srcs, RccClockMuxState,
135 RCC_NUM_CLOCK_MUX_SRC),
136 VMSTATE_BOOL(enabled, RccClockMuxState),
137 VMSTATE_UINT32(src, RccClockMuxState),
138 VMSTATE_UINT32(multiplier, RccClockMuxState),
139 VMSTATE_UINT32(divider, RccClockMuxState),
140 VMSTATE_END_OF_LIST()
141 }
142 };
143
clock_mux_class_init(ObjectClass * klass,void * data)144 static void clock_mux_class_init(ObjectClass *klass, void *data)
145 {
146 DeviceClass *dc = DEVICE_CLASS(klass);
147 ResettableClass *rc = RESETTABLE_CLASS(klass);
148
149 rc->phases.enter = clock_mux_reset_enter;
150 rc->phases.hold = clock_mux_reset_hold;
151 rc->phases.exit = clock_mux_reset_exit;
152 dc->vmsd = &clock_mux_vmstate;
153 }
154
clock_mux_set_enable(RccClockMuxState * mux,bool enabled)155 static void clock_mux_set_enable(RccClockMuxState *mux, bool enabled)
156 {
157 if (mux->enabled == enabled) {
158 return;
159 }
160
161 if (enabled) {
162 trace_stm32l4x5_rcc_mux_enable(mux->id);
163 } else {
164 trace_stm32l4x5_rcc_mux_disable(mux->id);
165 }
166
167 mux->enabled = enabled;
168 clock_mux_update(mux, false);
169 }
170
clock_mux_set_factor(RccClockMuxState * mux,uint32_t multiplier,uint32_t divider)171 static void clock_mux_set_factor(RccClockMuxState *mux,
172 uint32_t multiplier, uint32_t divider)
173 {
174 if (mux->multiplier == multiplier && mux->divider == divider) {
175 return;
176 }
177 trace_stm32l4x5_rcc_mux_set_factor(mux->id,
178 mux->multiplier, multiplier, mux->divider, divider);
179
180 mux->multiplier = multiplier;
181 mux->divider = divider;
182 clock_mux_update(mux, false);
183 }
184
clock_mux_set_source(RccClockMuxState * mux,RccClockMuxSource src)185 static void clock_mux_set_source(RccClockMuxState *mux, RccClockMuxSource src)
186 {
187 if (mux->src == src) {
188 return;
189 }
190
191 trace_stm32l4x5_rcc_mux_set_src(mux->id, mux->src, src);
192 mux->src = src;
193 clock_mux_update(mux, false);
194 }
195
196 /*
197 * Acknowledge and propagate changes in a PLL frequency.
198 * `bypass_source` allows to bypass the period of the current source and just
199 * consider it equal to 0. This is useful during the hold phase of reset.
200 */
pll_update(RccPllState * pll,bool bypass_source)201 static void pll_update(RccPllState *pll, bool bypass_source)
202 {
203 uint64_t vco_freq, old_channel_freq, channel_freq;
204 int i;
205
206 /* The common PLLM factor is handled by the PLL mux */
207 vco_freq = muldiv64(clock_get_hz(pll->in), pll->vco_multiplier, 1);
208
209 for (i = 0; i < RCC_NUM_CHANNEL_PLL_OUT; i++) {
210 if (!pll->channel_exists[i]) {
211 continue;
212 }
213
214 old_channel_freq = clock_get_hz(pll->channels[i]);
215 if (bypass_source ||
216 !pll->enabled ||
217 !pll->channel_enabled[i] ||
218 !pll->channel_divider[i]) {
219 channel_freq = 0;
220 } else {
221 channel_freq = muldiv64(vco_freq,
222 1,
223 pll->channel_divider[i]);
224 }
225
226 /* No change, early continue to avoid log spam and useless propagation */
227 if (old_channel_freq == channel_freq) {
228 continue;
229 }
230
231 clock_update_hz(pll->channels[i], channel_freq);
232 trace_stm32l4x5_rcc_pll_update(pll->id, i, vco_freq,
233 old_channel_freq, channel_freq);
234 }
235 }
236
pll_src_update(void * opaque,ClockEvent event)237 static void pll_src_update(void *opaque, ClockEvent event)
238 {
239 RccPllState *s = opaque;
240 pll_update(s, false);
241 }
242
pll_init(Object * obj)243 static void pll_init(Object *obj)
244 {
245 RccPllState *s = RCC_PLL(obj);
246 size_t i;
247
248 s->in = qdev_init_clock_in(DEVICE(s), "in",
249 pll_src_update, s, ClockUpdate);
250
251 const char *names[] = {
252 "out-p", "out-q", "out-r",
253 };
254
255 for (i = 0; i < RCC_NUM_CHANNEL_PLL_OUT; i++) {
256 s->channels[i] = qdev_init_clock_out(DEVICE(s), names[i]);
257 }
258 }
259
pll_reset_enter(Object * obj,ResetType type)260 static void pll_reset_enter(Object *obj, ResetType type)
261 {
262 RccPllState *s = RCC_PLL(obj);
263 set_pll_init_info(s, s->id);
264 }
265
pll_reset_hold(Object * obj,ResetType type)266 static void pll_reset_hold(Object *obj, ResetType type)
267 {
268 RccPllState *s = RCC_PLL(obj);
269 pll_update(s, true);
270 }
271
pll_reset_exit(Object * obj,ResetType type)272 static void pll_reset_exit(Object *obj, ResetType type)
273 {
274 RccPllState *s = RCC_PLL(obj);
275 pll_update(s, false);
276 }
277
278 static const VMStateDescription pll_vmstate = {
279 .name = TYPE_RCC_PLL,
280 .version_id = 1,
281 .minimum_version_id = 1,
282 .fields = (VMStateField[]) {
283 VMSTATE_UINT32(id, RccPllState),
284 VMSTATE_CLOCK(in, RccPllState),
285 VMSTATE_ARRAY_CLOCK(channels, RccPllState,
286 RCC_NUM_CHANNEL_PLL_OUT),
287 VMSTATE_BOOL(enabled, RccPllState),
288 VMSTATE_UINT32(vco_multiplier, RccPllState),
289 VMSTATE_BOOL_ARRAY(channel_enabled, RccPllState, RCC_NUM_CHANNEL_PLL_OUT),
290 VMSTATE_BOOL_ARRAY(channel_exists, RccPllState, RCC_NUM_CHANNEL_PLL_OUT),
291 VMSTATE_UINT32_ARRAY(channel_divider, RccPllState, RCC_NUM_CHANNEL_PLL_OUT),
292 VMSTATE_END_OF_LIST()
293 }
294 };
295
pll_class_init(ObjectClass * klass,void * data)296 static void pll_class_init(ObjectClass *klass, void *data)
297 {
298 DeviceClass *dc = DEVICE_CLASS(klass);
299 ResettableClass *rc = RESETTABLE_CLASS(klass);
300
301 rc->phases.enter = pll_reset_enter;
302 rc->phases.hold = pll_reset_hold;
303 rc->phases.exit = pll_reset_exit;
304 dc->vmsd = &pll_vmstate;
305 }
306
pll_set_vco_multiplier(RccPllState * pll,uint32_t vco_multiplier)307 static void pll_set_vco_multiplier(RccPllState *pll, uint32_t vco_multiplier)
308 {
309 if (pll->vco_multiplier == vco_multiplier) {
310 return;
311 }
312
313 if (vco_multiplier < 8 || vco_multiplier > 86) {
314 qemu_log_mask(LOG_GUEST_ERROR,
315 "%s: VCO multiplier is out of bound (%u) for PLL %u\n",
316 __func__, vco_multiplier, pll->id);
317 return;
318 }
319
320 trace_stm32l4x5_rcc_pll_set_vco_multiplier(pll->id,
321 pll->vco_multiplier, vco_multiplier);
322
323 pll->vco_multiplier = vco_multiplier;
324 pll_update(pll, false);
325 }
326
pll_set_enable(RccPllState * pll,bool enabled)327 static void pll_set_enable(RccPllState *pll, bool enabled)
328 {
329 if (pll->enabled == enabled) {
330 return;
331 }
332
333 pll->enabled = enabled;
334 pll_update(pll, false);
335 }
336
pll_set_channel_enable(RccPllState * pll,PllCommonChannels channel,bool enabled)337 static void pll_set_channel_enable(RccPllState *pll,
338 PllCommonChannels channel,
339 bool enabled)
340 {
341 if (pll->channel_enabled[channel] == enabled) {
342 return;
343 }
344
345 if (enabled) {
346 trace_stm32l4x5_rcc_pll_channel_enable(pll->id, channel);
347 } else {
348 trace_stm32l4x5_rcc_pll_channel_disable(pll->id, channel);
349 }
350
351 pll->channel_enabled[channel] = enabled;
352 pll_update(pll, false);
353 }
354
pll_set_channel_divider(RccPllState * pll,PllCommonChannels channel,uint32_t divider)355 static void pll_set_channel_divider(RccPllState *pll,
356 PllCommonChannels channel,
357 uint32_t divider)
358 {
359 if (pll->channel_divider[channel] == divider) {
360 return;
361 }
362
363 trace_stm32l4x5_rcc_pll_set_channel_divider(pll->id,
364 channel, pll->channel_divider[channel], divider);
365
366 pll->channel_divider[channel] = divider;
367 pll_update(pll, false);
368 }
369
rcc_update_irq(Stm32l4x5RccState * s)370 static void rcc_update_irq(Stm32l4x5RccState *s)
371 {
372 /*
373 * TODO: Handle LSECSSF and CSSF flags when the CSS is implemented.
374 */
375 if (s->cifr & CIFR_IRQ_MASK) {
376 qemu_irq_raise(s->irq);
377 } else {
378 qemu_irq_lower(s->irq);
379 }
380 }
381
rcc_update_msi(Stm32l4x5RccState * s,uint32_t previous_value)382 static void rcc_update_msi(Stm32l4x5RccState *s, uint32_t previous_value)
383 {
384 uint32_t val;
385
386 static const uint32_t msirange[] = {
387 100000, 200000, 400000, 800000, 1000000, 2000000,
388 4000000, 8000000, 16000000, 24000000, 32000000, 48000000
389 };
390 /* MSIRANGE and MSIRGSEL */
391 val = extract32(s->cr, R_CR_MSIRGSEL_SHIFT, R_CR_MSIRGSEL_LENGTH);
392 if (val) {
393 /* MSIRGSEL is set, use the MSIRANGE field */
394 val = extract32(s->cr, R_CR_MSIRANGE_SHIFT, R_CR_MSIRANGE_LENGTH);
395 } else {
396 /* MSIRGSEL is not set, use the MSISRANGE field */
397 val = extract32(s->csr, R_CSR_MSISRANGE_SHIFT, R_CSR_MSISRANGE_LENGTH);
398 }
399
400 if (val < ARRAY_SIZE(msirange)) {
401 clock_update_hz(s->msi_rc, msirange[val]);
402 } else {
403 /*
404 * There is a hardware write protection if the value is out of bound.
405 * Restore the previous value.
406 */
407 s->cr = (s->cr & ~R_CSR_MSISRANGE_MASK) |
408 (previous_value & R_CSR_MSISRANGE_MASK);
409 }
410 }
411
412 /*
413 * TODO: Add write-protection for all registers:
414 * DONE: CR
415 */
416
rcc_update_cr_register(Stm32l4x5RccState * s,uint32_t previous_value)417 static void rcc_update_cr_register(Stm32l4x5RccState *s, uint32_t previous_value)
418 {
419 int val;
420 const RccClockMuxSource current_pll_src =
421 CLOCK_MUX_INIT_INFO[RCC_CLOCK_MUX_PLL_INPUT].src_mapping[
422 s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT].src];
423
424 /* PLLSAI2ON and update PLLSAI2RDY */
425 val = FIELD_EX32(s->cr, CR, PLLSAI2ON);
426 pll_set_enable(&s->plls[RCC_PLL_PLLSAI2], val);
427 s->cr = (s->cr & ~R_CR_PLLSAI2RDY_MASK) |
428 (val << R_CR_PLLSAI2RDY_SHIFT);
429 if (s->cier & R_CIER_PLLSAI2RDYIE_MASK) {
430 s->cifr |= R_CIFR_PLLSAI2RDYF_MASK;
431 }
432
433 /* PLLSAI1ON and update PLLSAI1RDY */
434 val = FIELD_EX32(s->cr, CR, PLLSAI1ON);
435 pll_set_enable(&s->plls[RCC_PLL_PLLSAI1], val);
436 s->cr = (s->cr & ~R_CR_PLLSAI1RDY_MASK) |
437 (val << R_CR_PLLSAI1RDY_SHIFT);
438 if (s->cier & R_CIER_PLLSAI1RDYIE_MASK) {
439 s->cifr |= R_CIFR_PLLSAI1RDYF_MASK;
440 }
441
442 /*
443 * PLLON and update PLLRDY
444 * PLLON cannot be reset if the PLL clock is used as the system clock.
445 */
446 val = FIELD_EX32(s->cr, CR, PLLON);
447 if (FIELD_EX32(s->cfgr, CFGR, SWS) != 0b11) {
448 pll_set_enable(&s->plls[RCC_PLL_PLL], val);
449 s->cr = (s->cr & ~R_CR_PLLRDY_MASK) |
450 (val << R_CR_PLLRDY_SHIFT);
451 if (s->cier & R_CIER_PLLRDYIE_MASK) {
452 s->cifr |= R_CIFR_PLLRDYF_MASK;
453 }
454 } else {
455 s->cr |= R_CR_PLLON_MASK;
456 }
457
458 /* CSSON: TODO */
459 /* HSEBYP: TODO */
460
461 /*
462 * HSEON and update HSERDY.
463 * HSEON cannot be reset if the HSE oscillator is used directly or
464 * indirectly as the system clock.
465 */
466 val = FIELD_EX32(s->cr, CR, HSEON);
467 if (FIELD_EX32(s->cfgr, CFGR, SWS) != 0b10 &&
468 current_pll_src != RCC_CLOCK_MUX_SRC_HSE) {
469 s->cr = (s->cr & ~R_CR_HSERDY_MASK) |
470 (val << R_CR_HSERDY_SHIFT);
471 if (val) {
472 clock_update_hz(s->hse, s->hse_frequency);
473 if (s->cier & R_CIER_HSERDYIE_MASK) {
474 s->cifr |= R_CIFR_HSERDYF_MASK;
475 }
476 } else {
477 clock_update(s->hse, 0);
478 }
479 } else {
480 s->cr |= R_CR_HSEON_MASK;
481 }
482
483 /* HSIAFS: TODO*/
484 /* HSIKERON: TODO*/
485
486 /*
487 * HSION and update HSIRDY
488 * HSION is set by hardware if the HSI16 is used directly
489 * or indirectly as system clock.
490 */
491 if (FIELD_EX32(s->cfgr, CFGR, SWS) == 0b01 ||
492 current_pll_src == RCC_CLOCK_MUX_SRC_HSI) {
493 s->cr |= (R_CR_HSION_MASK | R_CR_HSIRDY_MASK);
494 clock_update_hz(s->hsi16_rc, HSI_FRQ);
495 if (s->cier & R_CIER_HSIRDYIE_MASK) {
496 s->cifr |= R_CIFR_HSIRDYF_MASK;
497 }
498 } else {
499 val = FIELD_EX32(s->cr, CR, HSION);
500 if (val) {
501 clock_update_hz(s->hsi16_rc, HSI_FRQ);
502 s->cr |= R_CR_HSIRDY_MASK;
503 if (s->cier & R_CIER_HSIRDYIE_MASK) {
504 s->cifr |= R_CIFR_HSIRDYF_MASK;
505 }
506 } else {
507 clock_update(s->hsi16_rc, 0);
508 s->cr &= ~R_CR_HSIRDY_MASK;
509 }
510 }
511
512 /* MSIPLLEN: TODO */
513
514 /*
515 * MSION and update MSIRDY
516 * Set by hardware when used directly or indirectly as system clock.
517 */
518 if (FIELD_EX32(s->cfgr, CFGR, SWS) == 0b00 ||
519 current_pll_src == RCC_CLOCK_MUX_SRC_MSI) {
520 s->cr |= (R_CR_MSION_MASK | R_CR_MSIRDY_MASK);
521 if (!(previous_value & R_CR_MSION_MASK) && (s->cier & R_CIER_MSIRDYIE_MASK)) {
522 s->cifr |= R_CIFR_MSIRDYF_MASK;
523 }
524 rcc_update_msi(s, previous_value);
525 } else {
526 val = FIELD_EX32(s->cr, CR, MSION);
527 if (val) {
528 s->cr |= R_CR_MSIRDY_MASK;
529 rcc_update_msi(s, previous_value);
530 if (s->cier & R_CIER_MSIRDYIE_MASK) {
531 s->cifr |= R_CIFR_MSIRDYF_MASK;
532 }
533 } else {
534 s->cr &= ~R_CR_MSIRDY_MASK;
535 clock_update(s->msi_rc, 0);
536 }
537 }
538 rcc_update_irq(s);
539 }
540
rcc_update_cfgr_register(Stm32l4x5RccState * s)541 static void rcc_update_cfgr_register(Stm32l4x5RccState *s)
542 {
543 uint32_t val;
544 /* MCOPRE */
545 val = FIELD_EX32(s->cfgr, CFGR, MCOPRE);
546 if (val > 0b100) {
547 qemu_log_mask(LOG_GUEST_ERROR,
548 "%s: Invalid MCOPRE value: 0x%"PRIx32"\n",
549 __func__, val);
550 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], false);
551 } else {
552 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_MCO],
553 1, 1 << val);
554 }
555
556 /* MCOSEL */
557 val = FIELD_EX32(s->cfgr, CFGR, MCOSEL);
558 if (val > 0b111) {
559 qemu_log_mask(LOG_GUEST_ERROR,
560 "%s: Invalid MCOSEL value: 0x%"PRIx32"\n",
561 __func__, val);
562 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], false);
563 } else {
564 if (val == 0) {
565 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], false);
566 } else {
567 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], true);
568 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_MCO],
569 val - 1);
570 }
571 }
572
573 /* STOPWUCK */
574 /* TODO */
575
576 /* PPRE2 */
577 val = FIELD_EX32(s->cfgr, CFGR, PPRE2);
578 if (val < 0b100) {
579 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PCLK2],
580 1, 1);
581 } else {
582 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PCLK2],
583 1, 1 << (val - 0b11));
584 }
585
586 /* PPRE1 */
587 val = FIELD_EX32(s->cfgr, CFGR, PPRE1);
588 if (val < 0b100) {
589 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PCLK1],
590 1, 1);
591 } else {
592 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PCLK1],
593 1, 1 << (val - 0b11));
594 }
595
596 /* HPRE */
597 val = FIELD_EX32(s->cfgr, CFGR, HPRE);
598 if (val < 0b1000) {
599 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_HCLK],
600 1, 1);
601 } else {
602 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_HCLK],
603 1, 1 << (val - 0b111));
604 }
605
606 /* Update SWS */
607 val = FIELD_EX32(s->cfgr, CFGR, SW);
608 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_SYSCLK],
609 val);
610 s->cfgr &= ~R_CFGR_SWS_MASK;
611 s->cfgr |= val << R_CFGR_SWS_SHIFT;
612 }
613
rcc_update_ahb1enr(Stm32l4x5RccState * s)614 static void rcc_update_ahb1enr(Stm32l4x5RccState *s)
615 {
616 #define AHB1ENR_SET_ENABLE(_peripheral_name) \
617 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \
618 FIELD_EX32(s->ahb1enr, AHB1ENR, _peripheral_name##EN))
619
620 /* DMA2DEN: reserved for STM32L475xx */
621 AHB1ENR_SET_ENABLE(TSC);
622 AHB1ENR_SET_ENABLE(CRC);
623 AHB1ENR_SET_ENABLE(FLASH);
624 AHB1ENR_SET_ENABLE(DMA2);
625 AHB1ENR_SET_ENABLE(DMA1);
626
627 #undef AHB1ENR_SET_ENABLE
628 }
629
rcc_update_ahb2enr(Stm32l4x5RccState * s)630 static void rcc_update_ahb2enr(Stm32l4x5RccState *s)
631 {
632 #define AHB2ENR_SET_ENABLE(_peripheral_name) \
633 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \
634 FIELD_EX32(s->ahb2enr, AHB2ENR, _peripheral_name##EN))
635
636 AHB2ENR_SET_ENABLE(RNG);
637 /* HASHEN: reserved for STM32L475xx */
638 AHB2ENR_SET_ENABLE(AES);
639 /* DCMIEN: reserved for STM32L475xx */
640 AHB2ENR_SET_ENABLE(ADC);
641 AHB2ENR_SET_ENABLE(OTGFS);
642 /* GPIOIEN: reserved for STM32L475xx */
643 AHB2ENR_SET_ENABLE(GPIOA);
644 AHB2ENR_SET_ENABLE(GPIOB);
645 AHB2ENR_SET_ENABLE(GPIOC);
646 AHB2ENR_SET_ENABLE(GPIOD);
647 AHB2ENR_SET_ENABLE(GPIOE);
648 AHB2ENR_SET_ENABLE(GPIOF);
649 AHB2ENR_SET_ENABLE(GPIOG);
650 AHB2ENR_SET_ENABLE(GPIOH);
651
652 #undef AHB2ENR_SET_ENABLE
653 }
654
rcc_update_ahb3enr(Stm32l4x5RccState * s)655 static void rcc_update_ahb3enr(Stm32l4x5RccState *s)
656 {
657 #define AHB3ENR_SET_ENABLE(_peripheral_name) \
658 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \
659 FIELD_EX32(s->ahb3enr, AHB3ENR, _peripheral_name##EN))
660
661 AHB3ENR_SET_ENABLE(QSPI);
662 AHB3ENR_SET_ENABLE(FMC);
663
664 #undef AHB3ENR_SET_ENABLE
665 }
666
rcc_update_apb1enr(Stm32l4x5RccState * s)667 static void rcc_update_apb1enr(Stm32l4x5RccState *s)
668 {
669 #define APB1ENR1_SET_ENABLE(_peripheral_name) \
670 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \
671 FIELD_EX32(s->apb1enr1, APB1ENR1, _peripheral_name##EN))
672 #define APB1ENR2_SET_ENABLE(_peripheral_name) \
673 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \
674 FIELD_EX32(s->apb1enr2, APB1ENR2, _peripheral_name##EN))
675
676 /* APB1ENR1 */
677 APB1ENR1_SET_ENABLE(LPTIM1);
678 APB1ENR1_SET_ENABLE(OPAMP);
679 APB1ENR1_SET_ENABLE(DAC1);
680 APB1ENR1_SET_ENABLE(PWR);
681 /* CAN2: reserved for STM32L4x5 */
682 APB1ENR1_SET_ENABLE(CAN1);
683 /* CRSEN: reserved for STM32L4x5 */
684 APB1ENR1_SET_ENABLE(I2C3);
685 APB1ENR1_SET_ENABLE(I2C2);
686 APB1ENR1_SET_ENABLE(I2C1);
687 APB1ENR1_SET_ENABLE(UART5);
688 APB1ENR1_SET_ENABLE(UART4);
689 APB1ENR1_SET_ENABLE(USART3);
690 APB1ENR1_SET_ENABLE(USART2);
691 APB1ENR1_SET_ENABLE(SPI3);
692 APB1ENR1_SET_ENABLE(SPI2);
693 APB1ENR1_SET_ENABLE(WWDG);
694 /* RTCAPB: reserved for STM32L4x5 */
695 APB1ENR1_SET_ENABLE(LCD);
696 APB1ENR1_SET_ENABLE(TIM7);
697 APB1ENR1_SET_ENABLE(TIM6);
698 APB1ENR1_SET_ENABLE(TIM5);
699 APB1ENR1_SET_ENABLE(TIM4);
700 APB1ENR1_SET_ENABLE(TIM3);
701 APB1ENR1_SET_ENABLE(TIM2);
702
703 /* APB1ENR2 */
704 APB1ENR2_SET_ENABLE(LPTIM2);
705 APB1ENR2_SET_ENABLE(SWPMI1);
706 /* I2C4EN: reserved for STM32L4x5 */
707 APB1ENR2_SET_ENABLE(LPUART1);
708
709 #undef APB1ENR1_SET_ENABLE
710 #undef APB1ENR2_SET_ENABLE
711 }
712
rcc_update_apb2enr(Stm32l4x5RccState * s)713 static void rcc_update_apb2enr(Stm32l4x5RccState *s)
714 {
715 #define APB2ENR_SET_ENABLE(_peripheral_name) \
716 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \
717 FIELD_EX32(s->apb2enr, APB2ENR, _peripheral_name##EN))
718
719 APB2ENR_SET_ENABLE(DFSDM1);
720 APB2ENR_SET_ENABLE(SAI2);
721 APB2ENR_SET_ENABLE(SAI1);
722 APB2ENR_SET_ENABLE(TIM17);
723 APB2ENR_SET_ENABLE(TIM16);
724 APB2ENR_SET_ENABLE(TIM15);
725 APB2ENR_SET_ENABLE(USART1);
726 APB2ENR_SET_ENABLE(TIM8);
727 APB2ENR_SET_ENABLE(SPI1);
728 APB2ENR_SET_ENABLE(TIM1);
729 APB2ENR_SET_ENABLE(SDMMC1);
730 APB2ENR_SET_ENABLE(FW);
731 APB2ENR_SET_ENABLE(SYSCFG);
732
733 #undef APB2ENR_SET_ENABLE
734 }
735
736 /*
737 * The 3 PLLs share the same register layout
738 * so we can use the same function for all of them
739 * Note: no frequency bounds checking is done here.
740 */
rcc_update_pllsaixcfgr(Stm32l4x5RccState * s,RccPll pll_id)741 static void rcc_update_pllsaixcfgr(Stm32l4x5RccState *s, RccPll pll_id)
742 {
743 uint32_t reg, val;
744 switch (pll_id) {
745 case RCC_PLL_PLL:
746 reg = s->pllcfgr;
747 break;
748 case RCC_PLL_PLLSAI1:
749 reg = s->pllsai1cfgr;
750 break;
751 case RCC_PLL_PLLSAI2:
752 reg = s->pllsai2cfgr;
753 break;
754 default:
755 qemu_log_mask(LOG_GUEST_ERROR,
756 "%s: Invalid PLL ID: %u\n", __func__, pll_id);
757 return;
758 }
759
760 /* PLLPDIV */
761 val = FIELD_EX32(reg, PLLCFGR, PLLPDIV);
762 /* 1 is a reserved value */
763 if (val == 0) {
764 /* Get PLLP value */
765 val = FIELD_EX32(reg, PLLCFGR, PLLP);
766 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_P,
767 (val ? 17 : 7));
768 } else if (val > 1) {
769 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_P,
770 val);
771 }
772
773
774 /* PLLR */
775 val = FIELD_EX32(reg, PLLCFGR, PLLR);
776 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_R,
777 2 * (val + 1));
778
779 /* PLLREN */
780 val = FIELD_EX32(reg, PLLCFGR, PLLREN);
781 pll_set_channel_enable(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_R, val);
782
783 /* PLLQ */
784 val = FIELD_EX32(reg, PLLCFGR, PLLQ);
785 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_Q,
786 2 * (val + 1));
787
788 /* PLLQEN */
789 val = FIELD_EX32(reg, PLLCFGR, PLLQEN);
790 pll_set_channel_enable(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_Q, val);
791
792 /* PLLPEN */
793 val = FIELD_EX32(reg, PLLCFGR, PLLPEN);
794 pll_set_channel_enable(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_P, val);
795
796 /* PLLN */
797 val = FIELD_EX32(reg, PLLCFGR, PLLN);
798 pll_set_vco_multiplier(&s->plls[pll_id], val);
799 }
800
rcc_update_pllcfgr(Stm32l4x5RccState * s)801 static void rcc_update_pllcfgr(Stm32l4x5RccState *s)
802 {
803 int val;
804
805 /* Use common layout */
806 rcc_update_pllsaixcfgr(s, RCC_PLL_PLL);
807
808 /* Fetch specific fields for pllcfgr */
809
810 /* PLLM */
811 val = FIELD_EX32(s->pllcfgr, PLLCFGR, PLLM);
812 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT], 1, (val + 1));
813
814 /* PLLSRC */
815 val = FIELD_EX32(s->pllcfgr, PLLCFGR, PLLSRC);
816 if (val == 0) {
817 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT], false);
818 } else {
819 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT], val - 1);
820 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT], true);
821 }
822 }
823
rcc_update_ccipr(Stm32l4x5RccState * s)824 static void rcc_update_ccipr(Stm32l4x5RccState *s)
825 {
826 #define CCIPR_SET_SOURCE(_peripheral_name) \
827 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \
828 FIELD_EX32(s->ccipr, CCIPR, _peripheral_name##SEL))
829
830 CCIPR_SET_SOURCE(DFSDM1);
831 CCIPR_SET_SOURCE(SWPMI1);
832 CCIPR_SET_SOURCE(ADC);
833 CCIPR_SET_SOURCE(CLK48);
834 CCIPR_SET_SOURCE(SAI2);
835 CCIPR_SET_SOURCE(SAI1);
836 CCIPR_SET_SOURCE(LPTIM2);
837 CCIPR_SET_SOURCE(LPTIM1);
838 CCIPR_SET_SOURCE(I2C3);
839 CCIPR_SET_SOURCE(I2C2);
840 CCIPR_SET_SOURCE(I2C1);
841 CCIPR_SET_SOURCE(LPUART1);
842 CCIPR_SET_SOURCE(UART5);
843 CCIPR_SET_SOURCE(UART4);
844 CCIPR_SET_SOURCE(USART3);
845 CCIPR_SET_SOURCE(USART2);
846 CCIPR_SET_SOURCE(USART1);
847
848 #undef CCIPR_SET_SOURCE
849 }
850
rcc_update_bdcr(Stm32l4x5RccState * s)851 static void rcc_update_bdcr(Stm32l4x5RccState *s)
852 {
853 int val;
854
855 /* LSCOSEL */
856 val = FIELD_EX32(s->bdcr, BDCR, LSCOSEL);
857 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_LSCO], val);
858
859 val = FIELD_EX32(s->bdcr, BDCR, LSCOEN);
860 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_LSCO], val);
861
862 /* BDRST */
863 /*
864 * The documentation is not clear if the RTCEN flag disables the RTC and
865 * the LCD common mux or if it only affects the RTC.
866 * As the LCDEN flag exists, we assume here that it only affects the RTC.
867 */
868 val = FIELD_EX32(s->bdcr, BDCR, RTCEN);
869 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_RTC], val);
870 /* LCD and RTC share the same clock */
871 val = FIELD_EX32(s->bdcr, BDCR, RTCSEL);
872 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_LCD_AND_RTC_COMMON], val);
873
874 /* LSECSSON */
875 /* LSEDRV[1:0] */
876 /* LSEBYP */
877
878 /* LSEON: Update LSERDY at the same time */
879 val = FIELD_EX32(s->bdcr, BDCR, LSEON);
880 if (val) {
881 clock_update_hz(s->lse_crystal, LSE_FRQ);
882 s->bdcr |= R_BDCR_LSERDY_MASK;
883 if (s->cier & R_CIER_LSERDYIE_MASK) {
884 s->cifr |= R_CIFR_LSERDYF_MASK;
885 }
886 } else {
887 clock_update(s->lse_crystal, 0);
888 s->bdcr &= ~R_BDCR_LSERDY_MASK;
889 }
890
891 rcc_update_irq(s);
892 }
893
rcc_update_csr(Stm32l4x5RccState * s)894 static void rcc_update_csr(Stm32l4x5RccState *s)
895 {
896 int val;
897
898 /* Reset flags: Not implemented */
899 /* MSISRANGE: Not implemented after reset */
900
901 /* LSION: Update LSIRDY at the same time */
902 val = FIELD_EX32(s->csr, CSR, LSION);
903 if (val) {
904 clock_update_hz(s->lsi_rc, LSI_FRQ);
905 s->csr |= R_CSR_LSIRDY_MASK;
906 if (s->cier & R_CIER_LSIRDYIE_MASK) {
907 s->cifr |= R_CIFR_LSIRDYF_MASK;
908 }
909 } else {
910 /*
911 * TODO: Handle when the LSI is set independently of LSION.
912 * E.g. when the LSI is set by the RTC.
913 * See the reference manual for more details.
914 */
915 clock_update(s->lsi_rc, 0);
916 s->csr &= ~R_CSR_LSIRDY_MASK;
917 }
918
919 rcc_update_irq(s);
920 }
921
stm32l4x5_rcc_reset_hold(Object * obj,ResetType type)922 static void stm32l4x5_rcc_reset_hold(Object *obj, ResetType type)
923 {
924 Stm32l4x5RccState *s = STM32L4X5_RCC(obj);
925 s->cr = 0x00000063;
926 /*
927 * Factory-programmed calibration data
928 * From the reference manual: 0x10XX 00XX
929 * Value taken from a real card.
930 */
931 s->icscr = 0x106E0082;
932 s->cfgr = 0x0;
933 s->pllcfgr = 0x00001000;
934 s->pllsai1cfgr = 0x00001000;
935 s->pllsai2cfgr = 0x00001000;
936 s->cier = 0x0;
937 s->cifr = 0x0;
938 s->ahb1rstr = 0x0;
939 s->ahb2rstr = 0x0;
940 s->ahb3rstr = 0x0;
941 s->apb1rstr1 = 0x0;
942 s->apb1rstr2 = 0x0;
943 s->apb2rstr = 0x0;
944 s->ahb1enr = 0x00000100;
945 s->ahb2enr = 0x0;
946 s->ahb3enr = 0x0;
947 s->apb1enr1 = 0x0;
948 s->apb1enr2 = 0x0;
949 s->apb2enr = 0x0;
950 s->ahb1smenr = 0x00011303;
951 s->ahb2smenr = 0x000532FF;
952 s->ahb3smenr = 0x00000101;
953 s->apb1smenr1 = 0xF2FECA3F;
954 s->apb1smenr2 = 0x00000025;
955 s->apb2smenr = 0x01677C01;
956 s->ccipr = 0x0;
957 s->bdcr = 0x0;
958 s->csr = 0x0C000600;
959 }
960
stm32l4x5_rcc_read(void * opaque,hwaddr addr,unsigned int size)961 static uint64_t stm32l4x5_rcc_read(void *opaque, hwaddr addr,
962 unsigned int size)
963 {
964 Stm32l4x5RccState *s = opaque;
965 uint64_t retvalue = 0;
966
967 switch (addr) {
968 case A_CR:
969 retvalue = s->cr;
970 break;
971 case A_ICSCR:
972 retvalue = s->icscr;
973 break;
974 case A_CFGR:
975 retvalue = s->cfgr;
976 break;
977 case A_PLLCFGR:
978 retvalue = s->pllcfgr;
979 break;
980 case A_PLLSAI1CFGR:
981 retvalue = s->pllsai1cfgr;
982 break;
983 case A_PLLSAI2CFGR:
984 retvalue = s->pllsai2cfgr;
985 break;
986 case A_CIER:
987 retvalue = s->cier;
988 break;
989 case A_CIFR:
990 retvalue = s->cifr;
991 break;
992 case A_CICR:
993 /* CICR is write only, return the reset value = 0 */
994 break;
995 case A_AHB1RSTR:
996 retvalue = s->ahb1rstr;
997 break;
998 case A_AHB2RSTR:
999 retvalue = s->ahb2rstr;
1000 break;
1001 case A_AHB3RSTR:
1002 retvalue = s->ahb3rstr;
1003 break;
1004 case A_APB1RSTR1:
1005 retvalue = s->apb1rstr1;
1006 break;
1007 case A_APB1RSTR2:
1008 retvalue = s->apb1rstr2;
1009 break;
1010 case A_APB2RSTR:
1011 retvalue = s->apb2rstr;
1012 break;
1013 case A_AHB1ENR:
1014 retvalue = s->ahb1enr;
1015 break;
1016 case A_AHB2ENR:
1017 retvalue = s->ahb2enr;
1018 break;
1019 case A_AHB3ENR:
1020 retvalue = s->ahb3enr;
1021 break;
1022 case A_APB1ENR1:
1023 retvalue = s->apb1enr1;
1024 break;
1025 case A_APB1ENR2:
1026 retvalue = s->apb1enr2;
1027 break;
1028 case A_APB2ENR:
1029 retvalue = s->apb2enr;
1030 break;
1031 case A_AHB1SMENR:
1032 retvalue = s->ahb1smenr;
1033 break;
1034 case A_AHB2SMENR:
1035 retvalue = s->ahb2smenr;
1036 break;
1037 case A_AHB3SMENR:
1038 retvalue = s->ahb3smenr;
1039 break;
1040 case A_APB1SMENR1:
1041 retvalue = s->apb1smenr1;
1042 break;
1043 case A_APB1SMENR2:
1044 retvalue = s->apb1smenr2;
1045 break;
1046 case A_APB2SMENR:
1047 retvalue = s->apb2smenr;
1048 break;
1049 case A_CCIPR:
1050 retvalue = s->ccipr;
1051 break;
1052 case A_BDCR:
1053 retvalue = s->bdcr;
1054 break;
1055 case A_CSR:
1056 retvalue = s->csr;
1057 break;
1058 default:
1059 qemu_log_mask(LOG_GUEST_ERROR,
1060 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
1061 break;
1062 }
1063
1064 trace_stm32l4x5_rcc_read(addr, retvalue);
1065
1066 return retvalue;
1067 }
1068
stm32l4x5_rcc_write(void * opaque,hwaddr addr,uint64_t val64,unsigned int size)1069 static void stm32l4x5_rcc_write(void *opaque, hwaddr addr,
1070 uint64_t val64, unsigned int size)
1071 {
1072 Stm32l4x5RccState *s = opaque;
1073 uint32_t previous_value = 0;
1074 const uint32_t value = val64;
1075
1076 trace_stm32l4x5_rcc_write(addr, value);
1077
1078 switch (addr) {
1079 case A_CR:
1080 previous_value = s->cr;
1081 s->cr = (s->cr & CR_READ_SET_MASK) |
1082 (value & (CR_READ_SET_MASK | ~CR_READ_ONLY_MASK));
1083 rcc_update_cr_register(s, previous_value);
1084 break;
1085 case A_ICSCR:
1086 s->icscr = value & ~ICSCR_READ_ONLY_MASK;
1087 qemu_log_mask(LOG_UNIMP,
1088 "%s: Side-effects not implemented for ICSCR\n", __func__);
1089 break;
1090 case A_CFGR:
1091 s->cfgr = value & ~CFGR_READ_ONLY_MASK;
1092 rcc_update_cfgr_register(s);
1093 break;
1094 case A_PLLCFGR:
1095 s->pllcfgr = value;
1096 rcc_update_pllcfgr(s);
1097 break;
1098 case A_PLLSAI1CFGR:
1099 s->pllsai1cfgr = value;
1100 rcc_update_pllsaixcfgr(s, RCC_PLL_PLLSAI1);
1101 break;
1102 case A_PLLSAI2CFGR:
1103 s->pllsai2cfgr = value;
1104 rcc_update_pllsaixcfgr(s, RCC_PLL_PLLSAI2);
1105 break;
1106 case A_CIER:
1107 s->cier = value;
1108 qemu_log_mask(LOG_UNIMP,
1109 "%s: Side-effects not implemented for CIER\n", __func__);
1110 break;
1111 case A_CIFR:
1112 qemu_log_mask(LOG_GUEST_ERROR,
1113 "%s: Write attempt into read-only register (CIFR) 0x%"PRIx32"\n",
1114 __func__, value);
1115 break;
1116 case A_CICR:
1117 /* Clear interrupt flags by writing a 1 to the CICR register */
1118 s->cifr &= ~value;
1119 rcc_update_irq(s);
1120 break;
1121 /* Reset behaviors are not implemented */
1122 case A_AHB1RSTR:
1123 s->ahb1rstr = value;
1124 qemu_log_mask(LOG_UNIMP,
1125 "%s: Side-effects not implemented for AHB1RSTR\n", __func__);
1126 break;
1127 case A_AHB2RSTR:
1128 s->ahb2rstr = value;
1129 qemu_log_mask(LOG_UNIMP,
1130 "%s: Side-effects not implemented for AHB2RSTR\n", __func__);
1131 break;
1132 case A_AHB3RSTR:
1133 s->ahb3rstr = value;
1134 qemu_log_mask(LOG_UNIMP,
1135 "%s: Side-effects not implemented for AHB3RSTR\n", __func__);
1136 break;
1137 case A_APB1RSTR1:
1138 s->apb1rstr1 = value;
1139 qemu_log_mask(LOG_UNIMP,
1140 "%s: Side-effects not implemented for APB1RSTR1\n", __func__);
1141 break;
1142 case A_APB1RSTR2:
1143 s->apb1rstr2 = value;
1144 qemu_log_mask(LOG_UNIMP,
1145 "%s: Side-effects not implemented for APB1RSTR2\n", __func__);
1146 break;
1147 case A_APB2RSTR:
1148 s->apb2rstr = value;
1149 qemu_log_mask(LOG_UNIMP,
1150 "%s: Side-effects not implemented for APB2RSTR\n", __func__);
1151 break;
1152 case A_AHB1ENR:
1153 s->ahb1enr = value;
1154 rcc_update_ahb1enr(s);
1155 break;
1156 case A_AHB2ENR:
1157 s->ahb2enr = value;
1158 rcc_update_ahb2enr(s);
1159 break;
1160 case A_AHB3ENR:
1161 s->ahb3enr = value;
1162 rcc_update_ahb3enr(s);
1163 break;
1164 case A_APB1ENR1:
1165 s->apb1enr1 = value;
1166 rcc_update_apb1enr(s);
1167 break;
1168 case A_APB1ENR2:
1169 s->apb1enr2 = value;
1170 rcc_update_apb1enr(s);
1171 break;
1172 case A_APB2ENR:
1173 s->apb2enr = (s->apb2enr & APB2ENR_READ_SET_MASK) | value;
1174 rcc_update_apb2enr(s);
1175 break;
1176 /* Behaviors for Sleep and Stop modes are not implemented */
1177 case A_AHB1SMENR:
1178 s->ahb1smenr = value;
1179 qemu_log_mask(LOG_UNIMP,
1180 "%s: Side-effects not implemented for AHB1SMENR\n", __func__);
1181 break;
1182 case A_AHB2SMENR:
1183 s->ahb2smenr = value;
1184 qemu_log_mask(LOG_UNIMP,
1185 "%s: Side-effects not implemented for AHB2SMENR\n", __func__);
1186 break;
1187 case A_AHB3SMENR:
1188 s->ahb3smenr = value;
1189 qemu_log_mask(LOG_UNIMP,
1190 "%s: Side-effects not implemented for AHB3SMENR\n", __func__);
1191 break;
1192 case A_APB1SMENR1:
1193 s->apb1smenr1 = value;
1194 qemu_log_mask(LOG_UNIMP,
1195 "%s: Side-effects not implemented for APB1SMENR1\n", __func__);
1196 break;
1197 case A_APB1SMENR2:
1198 s->apb1smenr2 = value;
1199 qemu_log_mask(LOG_UNIMP,
1200 "%s: Side-effects not implemented for APB1SMENR2\n", __func__);
1201 break;
1202 case A_APB2SMENR:
1203 s->apb2smenr = value;
1204 qemu_log_mask(LOG_UNIMP,
1205 "%s: Side-effects not implemented for APB2SMENR\n", __func__);
1206 break;
1207 case A_CCIPR:
1208 s->ccipr = value;
1209 rcc_update_ccipr(s);
1210 break;
1211 case A_BDCR:
1212 s->bdcr = value & ~BDCR_READ_ONLY_MASK;
1213 rcc_update_bdcr(s);
1214 break;
1215 case A_CSR:
1216 s->csr = value & ~CSR_READ_ONLY_MASK;
1217 rcc_update_csr(s);
1218 break;
1219 default:
1220 qemu_log_mask(LOG_GUEST_ERROR,
1221 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
1222 }
1223 }
1224
1225 static const MemoryRegionOps stm32l4x5_rcc_ops = {
1226 .read = stm32l4x5_rcc_read,
1227 .write = stm32l4x5_rcc_write,
1228 .endianness = DEVICE_NATIVE_ENDIAN,
1229 .valid = {
1230 .max_access_size = 4,
1231 .min_access_size = 4,
1232 .unaligned = false
1233 },
1234 .impl = {
1235 .max_access_size = 4,
1236 .min_access_size = 4,
1237 .unaligned = false
1238 },
1239 };
1240
1241 static const ClockPortInitArray stm32l4x5_rcc_clocks = {
1242 QDEV_CLOCK_IN(Stm32l4x5RccState, hsi16_rc, NULL, 0),
1243 QDEV_CLOCK_IN(Stm32l4x5RccState, msi_rc, NULL, 0),
1244 QDEV_CLOCK_IN(Stm32l4x5RccState, hse, NULL, 0),
1245 QDEV_CLOCK_IN(Stm32l4x5RccState, lsi_rc, NULL, 0),
1246 QDEV_CLOCK_IN(Stm32l4x5RccState, lse_crystal, NULL, 0),
1247 QDEV_CLOCK_IN(Stm32l4x5RccState, sai1_extclk, NULL, 0),
1248 QDEV_CLOCK_IN(Stm32l4x5RccState, sai2_extclk, NULL, 0),
1249 QDEV_CLOCK_END
1250 };
1251
1252
stm32l4x5_rcc_init(Object * obj)1253 static void stm32l4x5_rcc_init(Object *obj)
1254 {
1255 Stm32l4x5RccState *s = STM32L4X5_RCC(obj);
1256 size_t i;
1257
1258 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
1259
1260 memory_region_init_io(&s->mmio, obj, &stm32l4x5_rcc_ops, s,
1261 TYPE_STM32L4X5_RCC, 0x400);
1262 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
1263
1264 qdev_init_clocks(DEVICE(s), stm32l4x5_rcc_clocks);
1265
1266 for (i = 0; i < RCC_NUM_PLL; i++) {
1267 object_initialize_child(obj, PLL_INIT_INFO[i].name,
1268 &s->plls[i], TYPE_RCC_PLL);
1269 set_pll_init_info(&s->plls[i], i);
1270 }
1271
1272 for (i = 0; i < RCC_NUM_CLOCK_MUX; i++) {
1273 char *alias;
1274
1275 object_initialize_child(obj, CLOCK_MUX_INIT_INFO[i].name,
1276 &s->clock_muxes[i],
1277 TYPE_RCC_CLOCK_MUX);
1278 set_clock_mux_init_info(&s->clock_muxes[i], i);
1279
1280 if (!CLOCK_MUX_INIT_INFO[i].hidden) {
1281 /* Expose muxes output as RCC outputs */
1282 alias = g_strdup_printf("%s-out", CLOCK_MUX_INIT_INFO[i].name);
1283 qdev_alias_clock(DEVICE(&s->clock_muxes[i]), "out", DEVICE(obj), alias);
1284 g_free(alias);
1285 }
1286 }
1287
1288 s->gnd = clock_new(obj, "gnd");
1289 }
1290
connect_mux_sources(Stm32l4x5RccState * s,RccClockMuxState * mux,const RccClockMuxSource * clk_mapping)1291 static void connect_mux_sources(Stm32l4x5RccState *s,
1292 RccClockMuxState *mux,
1293 const RccClockMuxSource *clk_mapping)
1294 {
1295 size_t i;
1296
1297 Clock * const CLK_SRC_MAPPING[] = {
1298 [RCC_CLOCK_MUX_SRC_GND] = s->gnd,
1299 [RCC_CLOCK_MUX_SRC_HSI] = s->hsi16_rc,
1300 [RCC_CLOCK_MUX_SRC_HSE] = s->hse,
1301 [RCC_CLOCK_MUX_SRC_MSI] = s->msi_rc,
1302 [RCC_CLOCK_MUX_SRC_LSI] = s->lsi_rc,
1303 [RCC_CLOCK_MUX_SRC_LSE] = s->lse_crystal,
1304 [RCC_CLOCK_MUX_SRC_SAI1_EXTCLK] = s->sai1_extclk,
1305 [RCC_CLOCK_MUX_SRC_SAI2_EXTCLK] = s->sai2_extclk,
1306 [RCC_CLOCK_MUX_SRC_PLL] =
1307 s->plls[RCC_PLL_PLL].channels[RCC_PLL_CHANNEL_PLLCLK],
1308 [RCC_CLOCK_MUX_SRC_PLLSAI1] =
1309 s->plls[RCC_PLL_PLLSAI1].channels[RCC_PLLSAI1_CHANNEL_PLLSAI1CLK],
1310 [RCC_CLOCK_MUX_SRC_PLLSAI2] =
1311 s->plls[RCC_PLL_PLLSAI2].channels[RCC_PLLSAI2_CHANNEL_PLLSAI2CLK],
1312 [RCC_CLOCK_MUX_SRC_PLLSAI3] =
1313 s->plls[RCC_PLL_PLL].channels[RCC_PLL_CHANNEL_PLLSAI3CLK],
1314 [RCC_CLOCK_MUX_SRC_PLL48M1] =
1315 s->plls[RCC_PLL_PLL].channels[RCC_PLL_CHANNEL_PLL48M1CLK],
1316 [RCC_CLOCK_MUX_SRC_PLL48M2] =
1317 s->plls[RCC_PLL_PLLSAI1].channels[RCC_PLLSAI1_CHANNEL_PLL48M2CLK],
1318 [RCC_CLOCK_MUX_SRC_PLLADC1] =
1319 s->plls[RCC_PLL_PLLSAI1].channels[RCC_PLLSAI1_CHANNEL_PLLADC1CLK],
1320 [RCC_CLOCK_MUX_SRC_PLLADC2] =
1321 s->plls[RCC_PLL_PLLSAI2] .channels[RCC_PLLSAI2_CHANNEL_PLLADC2CLK],
1322 [RCC_CLOCK_MUX_SRC_SYSCLK] = s->clock_muxes[RCC_CLOCK_MUX_SYSCLK].out,
1323 [RCC_CLOCK_MUX_SRC_HCLK] = s->clock_muxes[RCC_CLOCK_MUX_HCLK].out,
1324 [RCC_CLOCK_MUX_SRC_PCLK1] = s->clock_muxes[RCC_CLOCK_MUX_PCLK1].out,
1325 [RCC_CLOCK_MUX_SRC_PCLK2] = s->clock_muxes[RCC_CLOCK_MUX_PCLK2].out,
1326 [RCC_CLOCK_MUX_SRC_HSE_OVER_32] = s->clock_muxes[RCC_CLOCK_MUX_HSE_OVER_32].out,
1327 [RCC_CLOCK_MUX_SRC_LCD_AND_RTC_COMMON] =
1328 s->clock_muxes[RCC_CLOCK_MUX_LCD_AND_RTC_COMMON].out,
1329 };
1330
1331 assert(ARRAY_SIZE(CLK_SRC_MAPPING) == RCC_CLOCK_MUX_SRC_NUMBER);
1332
1333 for (i = 0; i < RCC_NUM_CLOCK_MUX_SRC; i++) {
1334 RccClockMuxSource mapping = clk_mapping[i];
1335 clock_set_source(mux->srcs[i], CLK_SRC_MAPPING[mapping]);
1336 }
1337 }
1338
1339
1340 static const VMStateDescription vmstate_stm32l4x5_rcc = {
1341 .name = TYPE_STM32L4X5_RCC,
1342 .version_id = 1,
1343 .minimum_version_id = 1,
1344 .fields = (VMStateField[]) {
1345 VMSTATE_UINT32(cr, Stm32l4x5RccState),
1346 VMSTATE_UINT32(icscr, Stm32l4x5RccState),
1347 VMSTATE_UINT32(cfgr, Stm32l4x5RccState),
1348 VMSTATE_UINT32(pllcfgr, Stm32l4x5RccState),
1349 VMSTATE_UINT32(pllsai1cfgr, Stm32l4x5RccState),
1350 VMSTATE_UINT32(pllsai2cfgr, Stm32l4x5RccState),
1351 VMSTATE_UINT32(cier, Stm32l4x5RccState),
1352 VMSTATE_UINT32(cifr, Stm32l4x5RccState),
1353 VMSTATE_UINT32(ahb1rstr, Stm32l4x5RccState),
1354 VMSTATE_UINT32(ahb2rstr, Stm32l4x5RccState),
1355 VMSTATE_UINT32(ahb3rstr, Stm32l4x5RccState),
1356 VMSTATE_UINT32(apb1rstr1, Stm32l4x5RccState),
1357 VMSTATE_UINT32(apb1rstr2, Stm32l4x5RccState),
1358 VMSTATE_UINT32(apb2rstr, Stm32l4x5RccState),
1359 VMSTATE_UINT32(ahb1enr, Stm32l4x5RccState),
1360 VMSTATE_UINT32(ahb2enr, Stm32l4x5RccState),
1361 VMSTATE_UINT32(ahb3enr, Stm32l4x5RccState),
1362 VMSTATE_UINT32(apb1enr1, Stm32l4x5RccState),
1363 VMSTATE_UINT32(apb1enr2, Stm32l4x5RccState),
1364 VMSTATE_UINT32(apb2enr, Stm32l4x5RccState),
1365 VMSTATE_UINT32(ahb1smenr, Stm32l4x5RccState),
1366 VMSTATE_UINT32(ahb2smenr, Stm32l4x5RccState),
1367 VMSTATE_UINT32(ahb3smenr, Stm32l4x5RccState),
1368 VMSTATE_UINT32(apb1smenr1, Stm32l4x5RccState),
1369 VMSTATE_UINT32(apb1smenr2, Stm32l4x5RccState),
1370 VMSTATE_UINT32(apb2smenr, Stm32l4x5RccState),
1371 VMSTATE_UINT32(ccipr, Stm32l4x5RccState),
1372 VMSTATE_UINT32(bdcr, Stm32l4x5RccState),
1373 VMSTATE_UINT32(csr, Stm32l4x5RccState),
1374 VMSTATE_CLOCK(hsi16_rc, Stm32l4x5RccState),
1375 VMSTATE_CLOCK(msi_rc, Stm32l4x5RccState),
1376 VMSTATE_CLOCK(hse, Stm32l4x5RccState),
1377 VMSTATE_CLOCK(lsi_rc, Stm32l4x5RccState),
1378 VMSTATE_CLOCK(lse_crystal, Stm32l4x5RccState),
1379 VMSTATE_CLOCK(sai1_extclk, Stm32l4x5RccState),
1380 VMSTATE_CLOCK(sai2_extclk, Stm32l4x5RccState),
1381 VMSTATE_END_OF_LIST()
1382 }
1383 };
1384
1385
stm32l4x5_rcc_realize(DeviceState * dev,Error ** errp)1386 static void stm32l4x5_rcc_realize(DeviceState *dev, Error **errp)
1387 {
1388 Stm32l4x5RccState *s = STM32L4X5_RCC(dev);
1389 size_t i;
1390
1391 if (s->hse_frequency < 4000000ULL ||
1392 s->hse_frequency > 48000000ULL) {
1393 error_setg(errp,
1394 "HSE frequency is outside of the allowed [4-48]Mhz range: %" PRIx64 "",
1395 s->hse_frequency);
1396 return;
1397 }
1398
1399 for (i = 0; i < RCC_NUM_PLL; i++) {
1400 RccPllState *pll = &s->plls[i];
1401
1402 clock_set_source(pll->in, s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT].out);
1403
1404 if (!qdev_realize(DEVICE(pll), NULL, errp)) {
1405 return;
1406 }
1407 }
1408
1409 for (i = 0; i < RCC_NUM_CLOCK_MUX; i++) {
1410 RccClockMuxState *clock_mux = &s->clock_muxes[i];
1411
1412 connect_mux_sources(s, clock_mux, CLOCK_MUX_INIT_INFO[i].src_mapping);
1413
1414 if (!qdev_realize(DEVICE(clock_mux), NULL, errp)) {
1415 return;
1416 }
1417 }
1418
1419 /*
1420 * Start clocks after everything is connected
1421 * to propagate the frequencies along the tree.
1422 */
1423 clock_update_hz(s->msi_rc, MSI_DEFAULT_FRQ);
1424 clock_update_hz(s->sai1_extclk, s->sai1_extclk_frequency);
1425 clock_update_hz(s->sai2_extclk, s->sai2_extclk_frequency);
1426 clock_update(s->gnd, 0);
1427 }
1428
1429 static Property stm32l4x5_rcc_properties[] = {
1430 DEFINE_PROP_UINT64("hse_frequency", Stm32l4x5RccState,
1431 hse_frequency, HSE_DEFAULT_FRQ),
1432 DEFINE_PROP_UINT64("sai1_extclk_frequency", Stm32l4x5RccState,
1433 sai1_extclk_frequency, 0),
1434 DEFINE_PROP_UINT64("sai2_extclk_frequency", Stm32l4x5RccState,
1435 sai2_extclk_frequency, 0),
1436 DEFINE_PROP_END_OF_LIST(),
1437 };
1438
stm32l4x5_rcc_class_init(ObjectClass * klass,void * data)1439 static void stm32l4x5_rcc_class_init(ObjectClass *klass, void *data)
1440 {
1441 DeviceClass *dc = DEVICE_CLASS(klass);
1442 ResettableClass *rc = RESETTABLE_CLASS(klass);
1443
1444 assert(ARRAY_SIZE(CLOCK_MUX_INIT_INFO) == RCC_NUM_CLOCK_MUX);
1445
1446 rc->phases.hold = stm32l4x5_rcc_reset_hold;
1447 device_class_set_props(dc, stm32l4x5_rcc_properties);
1448 dc->realize = stm32l4x5_rcc_realize;
1449 dc->vmsd = &vmstate_stm32l4x5_rcc;
1450 }
1451
1452 static const TypeInfo stm32l4x5_rcc_types[] = {
1453 {
1454 .name = TYPE_STM32L4X5_RCC,
1455 .parent = TYPE_SYS_BUS_DEVICE,
1456 .instance_size = sizeof(Stm32l4x5RccState),
1457 .instance_init = stm32l4x5_rcc_init,
1458 .class_init = stm32l4x5_rcc_class_init,
1459 }, {
1460 .name = TYPE_RCC_CLOCK_MUX,
1461 .parent = TYPE_DEVICE,
1462 .instance_size = sizeof(RccClockMuxState),
1463 .instance_init = clock_mux_init,
1464 .class_init = clock_mux_class_init,
1465 }, {
1466 .name = TYPE_RCC_PLL,
1467 .parent = TYPE_DEVICE,
1468 .instance_size = sizeof(RccPllState),
1469 .instance_init = pll_init,
1470 .class_init = pll_class_init,
1471 }
1472 };
1473
1474 DEFINE_TYPES(stm32l4x5_rcc_types)
1475