1 /* 2 * STM32L4x5 EXTI (Extended interrupts and events controller) 3 * 4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr> 5 * Copyright (c) 2023 Samuel Tardieu <samuel.tardieu@telecom-paris.fr> 6 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr> 7 * 8 * SPDX-License-Identifier: GPL-2.0-or-later 9 * 10 * This work is licensed under the terms of the GNU GPL, version 2 or later. 11 * See the COPYING file in the top-level directory. 12 * 13 * This work is based on the stm32f4xx_exti by Alistair Francis. 14 * Original code is licensed under the MIT License: 15 * 16 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 17 */ 18 19 /* 20 * The reference used is the STMicroElectronics RM0351 Reference manual 21 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. 22 * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/log.h" 27 #include "trace.h" 28 #include "hw/irq.h" 29 #include "migration/vmstate.h" 30 #include "hw/misc/stm32l4x5_exti.h" 31 32 #define EXTI_IMR1 0x00 33 #define EXTI_EMR1 0x04 34 #define EXTI_RTSR1 0x08 35 #define EXTI_FTSR1 0x0C 36 #define EXTI_SWIER1 0x10 37 #define EXTI_PR1 0x14 38 #define EXTI_IMR2 0x20 39 #define EXTI_EMR2 0x24 40 #define EXTI_RTSR2 0x28 41 #define EXTI_FTSR2 0x2C 42 #define EXTI_SWIER2 0x30 43 #define EXTI_PR2 0x34 44 45 #define EXTI_NUM_GPIO_EVENT_IN_LINES 16 46 #define EXTI_MAX_IRQ_PER_BANK 32 47 #define EXTI_IRQS_BANK0 32 48 #define EXTI_IRQS_BANK1 8 49 50 static const unsigned irqs_per_bank[EXTI_NUM_REGISTER] = { 51 EXTI_IRQS_BANK0, 52 EXTI_IRQS_BANK1, 53 }; 54 55 static const uint32_t exti_romask[EXTI_NUM_REGISTER] = { 56 0xff820000, /* 0b11111111_10000010_00000000_00000000 */ 57 0x00000087, /* 0b00000000_00000000_00000000_10000111 */ 58 }; 59 60 static unsigned regbank_index_by_irq(unsigned irq) 61 { 62 return irq >= EXTI_MAX_IRQ_PER_BANK ? 1 : 0; 63 } 64 65 static unsigned regbank_index_by_addr(hwaddr addr) 66 { 67 return addr >= EXTI_IMR2 ? 1 : 0; 68 } 69 70 static unsigned valid_mask(unsigned bank) 71 { 72 return MAKE_64BIT_MASK(0, irqs_per_bank[bank]); 73 } 74 75 static unsigned configurable_mask(unsigned bank) 76 { 77 return valid_mask(bank) & ~exti_romask[bank]; 78 } 79 80 static void stm32l4x5_exti_reset_hold(Object *obj, ResetType type) 81 { 82 Stm32l4x5ExtiState *s = STM32L4X5_EXTI(obj); 83 84 for (unsigned bank = 0; bank < EXTI_NUM_REGISTER; bank++) { 85 s->imr[bank] = exti_romask[bank]; 86 s->emr[bank] = 0x00000000; 87 s->rtsr[bank] = 0x00000000; 88 s->ftsr[bank] = 0x00000000; 89 s->swier[bank] = 0x00000000; 90 s->pr[bank] = 0x00000000; 91 s->irq_levels[bank] = 0x00000000; 92 } 93 } 94 95 static void stm32l4x5_exti_set_irq(void *opaque, int irq, int level) 96 { 97 Stm32l4x5ExtiState *s = opaque; 98 const unsigned bank = regbank_index_by_irq(irq); 99 const int oirq = irq; 100 101 trace_stm32l4x5_exti_set_irq(irq, level); 102 103 /* Shift the value to enable access in x2 registers. */ 104 irq %= EXTI_MAX_IRQ_PER_BANK; 105 106 if (level == extract32(s->irq_levels[bank], irq, 1)) { 107 /* No change in IRQ line state: do nothing */ 108 return; 109 } 110 s->irq_levels[bank] = deposit32(s->irq_levels[bank], irq, 1, level); 111 112 /* If the interrupt is masked, pr won't be raised */ 113 if (!extract32(s->imr[bank], irq, 1)) { 114 return; 115 } 116 117 if ((level && extract32(s->rtsr[bank], irq, 1)) || 118 (!level && extract32(s->ftsr[bank], irq, 1))) { 119 120 s->pr[bank] |= 1 << irq; 121 qemu_irq_pulse(s->irq[oirq]); 122 } 123 } 124 125 static uint64_t stm32l4x5_exti_read(void *opaque, hwaddr addr, 126 unsigned int size) 127 { 128 Stm32l4x5ExtiState *s = opaque; 129 uint32_t r = 0; 130 const unsigned bank = regbank_index_by_addr(addr); 131 132 switch (addr) { 133 case EXTI_IMR1: 134 case EXTI_IMR2: 135 r = s->imr[bank]; 136 break; 137 case EXTI_EMR1: 138 case EXTI_EMR2: 139 r = s->emr[bank]; 140 break; 141 case EXTI_RTSR1: 142 case EXTI_RTSR2: 143 r = s->rtsr[bank]; 144 break; 145 case EXTI_FTSR1: 146 case EXTI_FTSR2: 147 r = s->ftsr[bank]; 148 break; 149 case EXTI_SWIER1: 150 case EXTI_SWIER2: 151 r = s->swier[bank]; 152 break; 153 case EXTI_PR1: 154 case EXTI_PR2: 155 r = s->pr[bank]; 156 break; 157 158 default: 159 qemu_log_mask(LOG_GUEST_ERROR, 160 "STM32L4X5_exti_read: Bad offset 0x%" HWADDR_PRIx "\n", 161 addr); 162 break; 163 } 164 165 trace_stm32l4x5_exti_read(addr, r); 166 167 return r; 168 } 169 170 static void stm32l4x5_exti_write(void *opaque, hwaddr addr, 171 uint64_t val64, unsigned int size) 172 { 173 Stm32l4x5ExtiState *s = opaque; 174 const unsigned bank = regbank_index_by_addr(addr); 175 176 trace_stm32l4x5_exti_write(addr, val64); 177 178 switch (addr) { 179 case EXTI_IMR1: 180 case EXTI_IMR2: 181 s->imr[bank] = val64 & valid_mask(bank); 182 return; 183 case EXTI_EMR1: 184 case EXTI_EMR2: 185 s->emr[bank] = val64 & valid_mask(bank); 186 return; 187 case EXTI_RTSR1: 188 case EXTI_RTSR2: 189 s->rtsr[bank] = val64 & configurable_mask(bank); 190 return; 191 case EXTI_FTSR1: 192 case EXTI_FTSR2: 193 s->ftsr[bank] = val64 & configurable_mask(bank); 194 return; 195 case EXTI_SWIER1: 196 case EXTI_SWIER2: { 197 const uint32_t set = val64 & configurable_mask(bank); 198 const uint32_t pend = set & ~s->swier[bank] & s->imr[bank] & 199 ~s->pr[bank]; 200 s->swier[bank] = set; 201 s->pr[bank] |= pend; 202 for (unsigned i = 0; i < irqs_per_bank[bank]; i++) { 203 if (extract32(pend, i, 1)) { 204 qemu_irq_pulse(s->irq[i + 32 * bank]); 205 } 206 } 207 return; 208 } 209 case EXTI_PR1: 210 case EXTI_PR2: { 211 const uint32_t cleared = s->pr[bank] & val64 & configurable_mask(bank); 212 /* This bit is cleared by writing a 1 to it */ 213 s->pr[bank] &= ~cleared; 214 /* Software triggered interrupts are cleared as well */ 215 s->swier[bank] &= ~cleared; 216 return; 217 } 218 default: 219 qemu_log_mask(LOG_GUEST_ERROR, 220 "STM32L4X5_exti_write: Bad offset 0x%" HWADDR_PRIx "\n", 221 addr); 222 } 223 } 224 225 static const MemoryRegionOps stm32l4x5_exti_ops = { 226 .read = stm32l4x5_exti_read, 227 .write = stm32l4x5_exti_write, 228 .endianness = DEVICE_NATIVE_ENDIAN, 229 .impl.min_access_size = 4, 230 .impl.max_access_size = 4, 231 .impl.unaligned = false, 232 .valid.min_access_size = 4, 233 .valid.max_access_size = 4, 234 .valid.unaligned = false, 235 }; 236 237 static void stm32l4x5_exti_init(Object *obj) 238 { 239 Stm32l4x5ExtiState *s = STM32L4X5_EXTI(obj); 240 241 for (size_t i = 0; i < EXTI_NUM_INTERRUPT_OUT_LINES; i++) { 242 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]); 243 } 244 245 memory_region_init_io(&s->mmio, obj, &stm32l4x5_exti_ops, s, 246 TYPE_STM32L4X5_EXTI, 0x400); 247 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 248 249 qdev_init_gpio_in(DEVICE(obj), stm32l4x5_exti_set_irq, 250 EXTI_NUM_GPIO_EVENT_IN_LINES); 251 } 252 253 static const VMStateDescription vmstate_stm32l4x5_exti = { 254 .name = TYPE_STM32L4X5_EXTI, 255 .version_id = 2, 256 .minimum_version_id = 2, 257 .fields = (VMStateField[]) { 258 VMSTATE_UINT32_ARRAY(imr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER), 259 VMSTATE_UINT32_ARRAY(emr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER), 260 VMSTATE_UINT32_ARRAY(rtsr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER), 261 VMSTATE_UINT32_ARRAY(ftsr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER), 262 VMSTATE_UINT32_ARRAY(swier, Stm32l4x5ExtiState, EXTI_NUM_REGISTER), 263 VMSTATE_UINT32_ARRAY(pr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER), 264 VMSTATE_UINT32_ARRAY(irq_levels, Stm32l4x5ExtiState, EXTI_NUM_REGISTER), 265 VMSTATE_END_OF_LIST() 266 } 267 }; 268 269 static void stm32l4x5_exti_class_init(ObjectClass *klass, void *data) 270 { 271 DeviceClass *dc = DEVICE_CLASS(klass); 272 ResettableClass *rc = RESETTABLE_CLASS(klass); 273 274 dc->vmsd = &vmstate_stm32l4x5_exti; 275 rc->phases.hold = stm32l4x5_exti_reset_hold; 276 } 277 278 static const TypeInfo stm32l4x5_exti_types[] = { 279 { 280 .name = TYPE_STM32L4X5_EXTI, 281 .parent = TYPE_SYS_BUS_DEVICE, 282 .instance_size = sizeof(Stm32l4x5ExtiState), 283 .instance_init = stm32l4x5_exti_init, 284 .class_init = stm32l4x5_exti_class_init, 285 } 286 }; 287 288 DEFINE_TYPES(stm32l4x5_exti_types) 289