1 /*
2 * QEMU SiFive Test Finisher
3 *
4 * Copyright (c) 2018 SiFive, Inc.
5 *
6 * Test finisher memory mapped device used to exit simulation
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "hw/sysbus.h"
23 #include "qapi/error.h"
24 #include "qemu/log.h"
25 #include "qemu/module.h"
26 #include "sysemu/runstate.h"
27 #include "hw/misc/sifive_test.h"
28 #include "sysemu/sysemu.h"
29
sifive_test_read(void * opaque,hwaddr addr,unsigned int size)30 static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
31 {
32 return 0;
33 }
34
sifive_test_write(void * opaque,hwaddr addr,uint64_t val64,unsigned int size)35 static void sifive_test_write(void *opaque, hwaddr addr,
36 uint64_t val64, unsigned int size)
37 {
38 if (addr == 0) {
39 int status = val64 & 0xffff;
40 int code = (val64 >> 16) & 0xffff;
41 switch (status) {
42 case FINISHER_FAIL:
43 qemu_system_shutdown_request_with_code(
44 SHUTDOWN_CAUSE_GUEST_PANIC, code);
45 return;
46 case FINISHER_PASS:
47 qemu_system_shutdown_request_with_code(
48 SHUTDOWN_CAUSE_GUEST_SHUTDOWN, code);
49 return;
50 case FINISHER_RESET:
51 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
52 return;
53 default:
54 break;
55 }
56 }
57 qemu_log_mask(LOG_GUEST_ERROR, "%s: write: addr=0x%x val=0x%016" PRIx64 "\n",
58 __func__, (int)addr, val64);
59 }
60
61 static const MemoryRegionOps sifive_test_ops = {
62 .read = sifive_test_read,
63 .write = sifive_test_write,
64 .endianness = DEVICE_NATIVE_ENDIAN,
65 .valid = {
66 .min_access_size = 2,
67 .max_access_size = 4
68 }
69 };
70
sifive_test_init(Object * obj)71 static void sifive_test_init(Object *obj)
72 {
73 SiFiveTestState *s = SIFIVE_TEST(obj);
74
75 memory_region_init_io(&s->mmio, obj, &sifive_test_ops, s,
76 TYPE_SIFIVE_TEST, 0x1000);
77 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
78 }
79
80 static const TypeInfo sifive_test_info = {
81 .name = TYPE_SIFIVE_TEST,
82 .parent = TYPE_SYS_BUS_DEVICE,
83 .instance_size = sizeof(SiFiveTestState),
84 .instance_init = sifive_test_init,
85 };
86
sifive_test_register_types(void)87 static void sifive_test_register_types(void)
88 {
89 type_register_static(&sifive_test_info);
90 }
91
type_init(sifive_test_register_types)92 type_init(sifive_test_register_types)
93
94
95 /*
96 * Create Test device.
97 */
98 DeviceState *sifive_test_create(hwaddr addr)
99 {
100 DeviceState *dev = qdev_new(TYPE_SIFIVE_TEST);
101 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
102 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
103 return dev;
104 }
105