1 /* 2 * QEMU x86 ISA testdev 3 * 4 * Copyright (c) 2012 Avi Kivity, Gerd Hoffmann, Marcelo Tosatti 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* 26 * This device is used to test KVM features specific to the x86 port, such 27 * as emulation, power management, interrupt routing, among others. It's meant 28 * to be used like: 29 * 30 * qemu-system-x86_64 -device pc-testdev -serial stdio \ 31 * -device isa-debug-exit,iobase=0xf4,iosize=0x4 \ 32 * -kernel /home/lmr/Code/virt-test.git/kvm/unittests/msr.flat 33 * 34 * Where msr.flat is one of the KVM unittests, present on a separate repo, 35 * git://git.kernel.org/pub/scm/virt/kvm/kvm-unit-tests.git 36 */ 37 38 #include "qemu/osdep.h" 39 #include "hw/hw.h" 40 #include "hw/qdev.h" 41 #include "hw/isa/isa.h" 42 43 #define IOMEM_LEN 0x10000 44 45 typedef struct PCTestdev { 46 ISADevice parent_obj; 47 48 MemoryRegion ioport; 49 MemoryRegion ioport_byte; 50 MemoryRegion flush; 51 MemoryRegion irq; 52 MemoryRegion iomem; 53 uint32_t ioport_data; 54 char iomem_buf[IOMEM_LEN]; 55 } PCTestdev; 56 57 #define TYPE_TESTDEV "pc-testdev" 58 #define TESTDEV(obj) \ 59 OBJECT_CHECK(PCTestdev, (obj), TYPE_TESTDEV) 60 61 static void test_irq_line(void *opaque, hwaddr addr, uint64_t data, 62 unsigned len) 63 { 64 PCTestdev *dev = opaque; 65 ISADevice *isa = ISA_DEVICE(dev); 66 67 qemu_set_irq(isa_get_irq(isa, addr), !!data); 68 } 69 70 static const MemoryRegionOps test_irq_ops = { 71 .write = test_irq_line, 72 .valid.min_access_size = 1, 73 .valid.max_access_size = 1, 74 .endianness = DEVICE_LITTLE_ENDIAN, 75 }; 76 77 static void test_ioport_write(void *opaque, hwaddr addr, uint64_t data, 78 unsigned len) 79 { 80 PCTestdev *dev = opaque; 81 int bits = len * 8; 82 int start_bit = (addr & 3) * 8; 83 uint32_t mask = ((uint32_t)-1 >> (32 - bits)) << start_bit; 84 dev->ioport_data &= ~mask; 85 dev->ioport_data |= data << start_bit; 86 } 87 88 static uint64_t test_ioport_read(void *opaque, hwaddr addr, unsigned len) 89 { 90 PCTestdev *dev = opaque; 91 int bits = len * 8; 92 int start_bit = (addr & 3) * 8; 93 uint32_t mask = ((uint32_t)-1 >> (32 - bits)) << start_bit; 94 return (dev->ioport_data & mask) >> start_bit; 95 } 96 97 static const MemoryRegionOps test_ioport_ops = { 98 .read = test_ioport_read, 99 .write = test_ioport_write, 100 .endianness = DEVICE_LITTLE_ENDIAN, 101 }; 102 103 static const MemoryRegionOps test_ioport_byte_ops = { 104 .read = test_ioport_read, 105 .write = test_ioport_write, 106 .valid.min_access_size = 1, 107 .valid.max_access_size = 4, 108 .impl.min_access_size = 1, 109 .impl.max_access_size = 1, 110 .endianness = DEVICE_LITTLE_ENDIAN, 111 }; 112 113 static void test_flush_page(void *opaque, hwaddr addr, uint64_t data, 114 unsigned len) 115 { 116 hwaddr page = 4096; 117 void *a = cpu_physical_memory_map(data & ~0xffful, &page, 0); 118 119 /* We might not be able to get the full page, only mprotect what we actually 120 have mapped */ 121 #if defined(CONFIG_POSIX) 122 mprotect(a, page, PROT_NONE); 123 mprotect(a, page, PROT_READ|PROT_WRITE); 124 #endif 125 cpu_physical_memory_unmap(a, page, 0, 0); 126 } 127 128 static const MemoryRegionOps test_flush_ops = { 129 .write = test_flush_page, 130 .valid.min_access_size = 4, 131 .valid.max_access_size = 4, 132 .endianness = DEVICE_LITTLE_ENDIAN, 133 }; 134 135 static uint64_t test_iomem_read(void *opaque, hwaddr addr, unsigned len) 136 { 137 PCTestdev *dev = opaque; 138 uint64_t ret = 0; 139 memcpy(&ret, &dev->iomem_buf[addr], len); 140 141 return ret; 142 } 143 144 static void test_iomem_write(void *opaque, hwaddr addr, uint64_t val, 145 unsigned len) 146 { 147 PCTestdev *dev = opaque; 148 memcpy(&dev->iomem_buf[addr], &val, len); 149 dev->iomem_buf[addr] = val; 150 } 151 152 static const MemoryRegionOps test_iomem_ops = { 153 .read = test_iomem_read, 154 .write = test_iomem_write, 155 .endianness = DEVICE_LITTLE_ENDIAN, 156 }; 157 158 static void testdev_realizefn(DeviceState *d, Error **errp) 159 { 160 ISADevice *isa = ISA_DEVICE(d); 161 PCTestdev *dev = TESTDEV(d); 162 MemoryRegion *mem = isa_address_space(isa); 163 MemoryRegion *io = isa_address_space_io(isa); 164 165 memory_region_init_io(&dev->ioport, OBJECT(dev), &test_ioport_ops, dev, 166 "pc-testdev-ioport", 4); 167 memory_region_init_io(&dev->ioport_byte, OBJECT(dev), 168 &test_ioport_byte_ops, dev, 169 "pc-testdev-ioport-byte", 4); 170 memory_region_init_io(&dev->flush, OBJECT(dev), &test_flush_ops, dev, 171 "pc-testdev-flush-page", 4); 172 memory_region_init_io(&dev->irq, OBJECT(dev), &test_irq_ops, dev, 173 "pc-testdev-irq-line", 24); 174 memory_region_init_io(&dev->iomem, OBJECT(dev), &test_iomem_ops, dev, 175 "pc-testdev-iomem", IOMEM_LEN); 176 177 memory_region_add_subregion(io, 0xe0, &dev->ioport); 178 memory_region_add_subregion(io, 0xe4, &dev->flush); 179 memory_region_add_subregion(io, 0xe8, &dev->ioport_byte); 180 memory_region_add_subregion(io, 0x2000, &dev->irq); 181 memory_region_add_subregion(mem, 0xff000000, &dev->iomem); 182 } 183 184 static void testdev_class_init(ObjectClass *klass, void *data) 185 { 186 DeviceClass *dc = DEVICE_CLASS(klass); 187 188 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 189 dc->realize = testdev_realizefn; 190 } 191 192 static const TypeInfo testdev_info = { 193 .name = TYPE_TESTDEV, 194 .parent = TYPE_ISA_DEVICE, 195 .instance_size = sizeof(PCTestdev), 196 .class_init = testdev_class_init, 197 }; 198 199 static void testdev_register_types(void) 200 { 201 type_register_static(&testdev_info); 202 } 203 204 type_init(testdev_register_types) 205