xref: /openbmc/qemu/hw/misc/pc-testdev.c (revision 6a0acfff)
1 /*
2  * QEMU x86 ISA testdev
3  *
4  * Copyright (c) 2012 Avi Kivity, Gerd Hoffmann, Marcelo Tosatti
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 /*
26  * This device is used to test KVM features specific to the x86 port, such
27  * as emulation, power management, interrupt routing, among others. It's meant
28  * to be used like:
29  *
30  * qemu-system-x86_64 -device pc-testdev -serial stdio \
31  * -device isa-debug-exit,iobase=0xf4,iosize=0x4 \
32  * -kernel /home/lmr/Code/virt-test.git/kvm/unittests/msr.flat
33  *
34  * Where msr.flat is one of the KVM unittests, present on a separate repo,
35  * https://git.kernel.org/pub/scm/virt/kvm/kvm-unit-tests.git
36 */
37 
38 #include "qemu/osdep.h"
39 #include "hw/hw.h"
40 #include "hw/qdev.h"
41 #include "qemu/module.h"
42 #include "hw/irq.h"
43 #include "hw/isa/isa.h"
44 
45 #define IOMEM_LEN    0x10000
46 
47 typedef struct PCTestdev {
48     ISADevice parent_obj;
49 
50     MemoryRegion ioport;
51     MemoryRegion ioport_byte;
52     MemoryRegion flush;
53     MemoryRegion irq;
54     MemoryRegion iomem;
55     uint32_t ioport_data;
56     char iomem_buf[IOMEM_LEN];
57 } PCTestdev;
58 
59 #define TYPE_TESTDEV "pc-testdev"
60 #define TESTDEV(obj) \
61      OBJECT_CHECK(PCTestdev, (obj), TYPE_TESTDEV)
62 
63 static uint64_t test_irq_line_read(void *opaque, hwaddr addr, unsigned size)
64 {
65     return 0;
66 }
67 
68 static void test_irq_line_write(void *opaque, hwaddr addr, uint64_t data,
69                           unsigned len)
70 {
71     PCTestdev *dev = opaque;
72     ISADevice *isa = ISA_DEVICE(dev);
73 
74     qemu_set_irq(isa_get_irq(isa, addr), !!data);
75 }
76 
77 static const MemoryRegionOps test_irq_ops = {
78     .read = test_irq_line_read,
79     .write = test_irq_line_write,
80     .valid.min_access_size = 1,
81     .valid.max_access_size = 1,
82     .endianness = DEVICE_LITTLE_ENDIAN,
83 };
84 
85 static void test_ioport_write(void *opaque, hwaddr addr, uint64_t data,
86                               unsigned len)
87 {
88     PCTestdev *dev = opaque;
89     int bits = len * 8;
90     int start_bit = (addr & 3) * 8;
91     uint32_t mask = ((uint32_t)-1 >> (32 - bits)) << start_bit;
92     dev->ioport_data &= ~mask;
93     dev->ioport_data |= data << start_bit;
94 }
95 
96 static uint64_t test_ioport_read(void *opaque, hwaddr addr, unsigned len)
97 {
98     PCTestdev *dev = opaque;
99     int bits = len * 8;
100     int start_bit = (addr & 3) * 8;
101     uint32_t mask = ((uint32_t)-1 >> (32 - bits)) << start_bit;
102     return (dev->ioport_data & mask) >> start_bit;
103 }
104 
105 static const MemoryRegionOps test_ioport_ops = {
106     .read = test_ioport_read,
107     .write = test_ioport_write,
108     .endianness = DEVICE_LITTLE_ENDIAN,
109 };
110 
111 static const MemoryRegionOps test_ioport_byte_ops = {
112     .read = test_ioport_read,
113     .write = test_ioport_write,
114     .valid.min_access_size = 1,
115     .valid.max_access_size = 4,
116     .impl.min_access_size = 1,
117     .impl.max_access_size = 1,
118     .endianness = DEVICE_LITTLE_ENDIAN,
119 };
120 
121 static uint64_t test_flush_page_read(void *opaque, hwaddr addr, unsigned size)
122 {
123     return 0;
124 }
125 
126 static void test_flush_page_write(void *opaque, hwaddr addr, uint64_t data,
127                             unsigned len)
128 {
129     hwaddr page = 4096;
130     void *a = cpu_physical_memory_map(data & ~0xffful, &page, 0);
131 
132     /* We might not be able to get the full page, only mprotect what we actually
133        have mapped */
134 #if defined(CONFIG_POSIX)
135     mprotect(a, page, PROT_NONE);
136     mprotect(a, page, PROT_READ|PROT_WRITE);
137 #endif
138     cpu_physical_memory_unmap(a, page, 0, 0);
139 }
140 
141 static const MemoryRegionOps test_flush_ops = {
142     .read = test_flush_page_read,
143     .write = test_flush_page_write,
144     .valid.min_access_size = 4,
145     .valid.max_access_size = 4,
146     .endianness = DEVICE_LITTLE_ENDIAN,
147 };
148 
149 static uint64_t test_iomem_read(void *opaque, hwaddr addr, unsigned len)
150 {
151     PCTestdev *dev = opaque;
152     uint64_t ret = 0;
153     memcpy(&ret, &dev->iomem_buf[addr], len);
154 
155     return ret;
156 }
157 
158 static void test_iomem_write(void *opaque, hwaddr addr, uint64_t val,
159                              unsigned len)
160 {
161     PCTestdev *dev = opaque;
162     memcpy(&dev->iomem_buf[addr], &val, len);
163     dev->iomem_buf[addr] = val;
164 }
165 
166 static const MemoryRegionOps test_iomem_ops = {
167     .read = test_iomem_read,
168     .write = test_iomem_write,
169     .endianness = DEVICE_LITTLE_ENDIAN,
170 };
171 
172 static void testdev_realizefn(DeviceState *d, Error **errp)
173 {
174     ISADevice *isa = ISA_DEVICE(d);
175     PCTestdev *dev = TESTDEV(d);
176     MemoryRegion *mem = isa_address_space(isa);
177     MemoryRegion *io = isa_address_space_io(isa);
178 
179     memory_region_init_io(&dev->ioport, OBJECT(dev), &test_ioport_ops, dev,
180                           "pc-testdev-ioport", 4);
181     memory_region_init_io(&dev->ioport_byte, OBJECT(dev),
182                           &test_ioport_byte_ops, dev,
183                           "pc-testdev-ioport-byte", 4);
184     memory_region_init_io(&dev->flush, OBJECT(dev), &test_flush_ops, dev,
185                           "pc-testdev-flush-page", 4);
186     memory_region_init_io(&dev->irq, OBJECT(dev), &test_irq_ops, dev,
187                           "pc-testdev-irq-line", 24);
188     memory_region_init_io(&dev->iomem, OBJECT(dev), &test_iomem_ops, dev,
189                           "pc-testdev-iomem", IOMEM_LEN);
190 
191     memory_region_add_subregion(io,  0xe0,       &dev->ioport);
192     memory_region_add_subregion(io,  0xe4,       &dev->flush);
193     memory_region_add_subregion(io,  0xe8,       &dev->ioport_byte);
194     memory_region_add_subregion(io,  0x2000,     &dev->irq);
195     memory_region_add_subregion(mem, 0xff000000, &dev->iomem);
196 }
197 
198 static void testdev_class_init(ObjectClass *klass, void *data)
199 {
200     DeviceClass *dc = DEVICE_CLASS(klass);
201 
202     set_bit(DEVICE_CATEGORY_MISC, dc->categories);
203     dc->realize = testdev_realizefn;
204 }
205 
206 static const TypeInfo testdev_info = {
207     .name           = TYPE_TESTDEV,
208     .parent         = TYPE_ISA_DEVICE,
209     .instance_size  = sizeof(PCTestdev),
210     .class_init     = testdev_class_init,
211 };
212 
213 static void testdev_register_types(void)
214 {
215     type_register_static(&testdev_info);
216 }
217 
218 type_init(testdev_register_types)
219