1 /* 2 * ARM MPS2 SCC emulation 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* This is a model of the SCC (Serial Communication Controller) 13 * found in the FPGA images of MPS2 development boards. 14 * 15 * Documentation of it can be found in the MPS2 TRM: 16 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100112_0100_03_en/index.html 17 * and also in the Application Notes documenting individual FPGA images. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/module.h" 23 #include "trace.h" 24 #include "hw/sysbus.h" 25 #include "migration/vmstate.h" 26 #include "hw/registerfields.h" 27 #include "hw/misc/mps2-scc.h" 28 29 REG32(CFG0, 0) 30 REG32(CFG1, 4) 31 REG32(CFG3, 0xc) 32 REG32(CFG4, 0x10) 33 REG32(CFGDATA_RTN, 0xa0) 34 REG32(CFGDATA_OUT, 0xa4) 35 REG32(CFGCTRL, 0xa8) 36 FIELD(CFGCTRL, DEVICE, 0, 12) 37 FIELD(CFGCTRL, RES1, 12, 8) 38 FIELD(CFGCTRL, FUNCTION, 20, 6) 39 FIELD(CFGCTRL, RES2, 26, 4) 40 FIELD(CFGCTRL, WRITE, 30, 1) 41 FIELD(CFGCTRL, START, 31, 1) 42 REG32(CFGSTAT, 0xac) 43 FIELD(CFGSTAT, DONE, 0, 1) 44 FIELD(CFGSTAT, ERROR, 1, 1) 45 REG32(DLL, 0x100) 46 REG32(AID, 0xFF8) 47 REG32(ID, 0xFFC) 48 49 /* Handle a write via the SYS_CFG channel to the specified function/device. 50 * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit). 51 */ 52 static bool scc_cfg_write(MPS2SCC *s, unsigned function, 53 unsigned device, uint32_t value) 54 { 55 trace_mps2_scc_cfg_write(function, device, value); 56 57 if (function != 1 || device >= NUM_OSCCLK) { 58 qemu_log_mask(LOG_GUEST_ERROR, 59 "MPS2 SCC config write: bad function %d device %d\n", 60 function, device); 61 return false; 62 } 63 64 s->oscclk[device] = value; 65 return true; 66 } 67 68 /* Handle a read via the SYS_CFG channel to the specified function/device. 69 * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit), 70 * or set *value on success. 71 */ 72 static bool scc_cfg_read(MPS2SCC *s, unsigned function, 73 unsigned device, uint32_t *value) 74 { 75 if (function != 1 || device >= NUM_OSCCLK) { 76 qemu_log_mask(LOG_GUEST_ERROR, 77 "MPS2 SCC config read: bad function %d device %d\n", 78 function, device); 79 return false; 80 } 81 82 *value = s->oscclk[device]; 83 84 trace_mps2_scc_cfg_read(function, device, *value); 85 return true; 86 } 87 88 static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) 89 { 90 MPS2SCC *s = MPS2_SCC(opaque); 91 uint64_t r; 92 93 switch (offset) { 94 case A_CFG0: 95 r = s->cfg0; 96 break; 97 case A_CFG1: 98 r = s->cfg1; 99 break; 100 case A_CFG3: 101 /* These are user-settable DIP switches on the board. We don't 102 * model that, so just return zeroes. 103 */ 104 r = 0; 105 break; 106 case A_CFG4: 107 r = s->cfg4; 108 break; 109 case A_CFGDATA_RTN: 110 r = s->cfgdata_rtn; 111 break; 112 case A_CFGDATA_OUT: 113 r = s->cfgdata_out; 114 break; 115 case A_CFGCTRL: 116 r = s->cfgctrl; 117 break; 118 case A_CFGSTAT: 119 r = s->cfgstat; 120 break; 121 case A_DLL: 122 r = s->dll; 123 break; 124 case A_AID: 125 r = s->aid; 126 break; 127 case A_ID: 128 r = s->id; 129 break; 130 default: 131 qemu_log_mask(LOG_GUEST_ERROR, 132 "MPS2 SCC read: bad offset %x\n", (int) offset); 133 r = 0; 134 break; 135 } 136 137 trace_mps2_scc_read(offset, r, size); 138 return r; 139 } 140 141 static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, 142 unsigned size) 143 { 144 MPS2SCC *s = MPS2_SCC(opaque); 145 146 trace_mps2_scc_write(offset, value, size); 147 148 switch (offset) { 149 case A_CFG0: 150 /* TODO on some boards bit 0 controls RAM remapping */ 151 s->cfg0 = value; 152 break; 153 case A_CFG1: 154 /* CFG1 bits [7:0] control the board LEDs. We don't currently have 155 * a mechanism for displaying this graphically, so use a trace event. 156 */ 157 trace_mps2_scc_leds(value & 0x80 ? '*' : '.', 158 value & 0x40 ? '*' : '.', 159 value & 0x20 ? '*' : '.', 160 value & 0x10 ? '*' : '.', 161 value & 0x08 ? '*' : '.', 162 value & 0x04 ? '*' : '.', 163 value & 0x02 ? '*' : '.', 164 value & 0x01 ? '*' : '.'); 165 s->cfg1 = value; 166 break; 167 case A_CFGDATA_OUT: 168 s->cfgdata_out = value; 169 break; 170 case A_CFGCTRL: 171 /* Writing to CFGCTRL clears SYS_CFGSTAT */ 172 s->cfgstat = 0; 173 s->cfgctrl = value & ~(R_CFGCTRL_RES1_MASK | 174 R_CFGCTRL_RES2_MASK | 175 R_CFGCTRL_START_MASK); 176 177 if (value & R_CFGCTRL_START_MASK) { 178 /* Start bit set -- do a read or write (instantaneously) */ 179 int device = extract32(s->cfgctrl, R_CFGCTRL_DEVICE_SHIFT, 180 R_CFGCTRL_DEVICE_LENGTH); 181 int function = extract32(s->cfgctrl, R_CFGCTRL_FUNCTION_SHIFT, 182 R_CFGCTRL_FUNCTION_LENGTH); 183 184 s->cfgstat = R_CFGSTAT_DONE_MASK; 185 if (s->cfgctrl & R_CFGCTRL_WRITE_MASK) { 186 if (!scc_cfg_write(s, function, device, s->cfgdata_out)) { 187 s->cfgstat |= R_CFGSTAT_ERROR_MASK; 188 } 189 } else { 190 uint32_t result; 191 if (!scc_cfg_read(s, function, device, &result)) { 192 s->cfgstat |= R_CFGSTAT_ERROR_MASK; 193 } else { 194 s->cfgdata_rtn = result; 195 } 196 } 197 } 198 break; 199 case A_DLL: 200 /* DLL stands for Digital Locked Loop. 201 * Bits [31:24] (DLL_LOCK_MASK) are writable, and indicate a 202 * mask of which of the DLL_LOCKED bits [16:23] should be ORed 203 * together to determine the ALL_UNMASKED_DLLS_LOCKED bit [0]. 204 * For QEMU, our DLLs are always locked, so we can leave bit 0 205 * as 1 always and don't need to recalculate it. 206 */ 207 s->dll = deposit32(s->dll, 24, 8, extract32(value, 24, 8)); 208 break; 209 default: 210 qemu_log_mask(LOG_GUEST_ERROR, 211 "MPS2 SCC write: bad offset 0x%x\n", (int) offset); 212 break; 213 } 214 } 215 216 static const MemoryRegionOps mps2_scc_ops = { 217 .read = mps2_scc_read, 218 .write = mps2_scc_write, 219 .endianness = DEVICE_LITTLE_ENDIAN, 220 }; 221 222 static void mps2_scc_reset(DeviceState *dev) 223 { 224 MPS2SCC *s = MPS2_SCC(dev); 225 int i; 226 227 trace_mps2_scc_reset(); 228 s->cfg0 = 0; 229 s->cfg1 = 0; 230 s->cfgdata_rtn = 0; 231 s->cfgdata_out = 0; 232 s->cfgctrl = 0x100000; 233 s->cfgstat = 0; 234 s->dll = 0xffff0001; 235 for (i = 0; i < NUM_OSCCLK; i++) { 236 s->oscclk[i] = s->oscclk_reset[i]; 237 } 238 } 239 240 static void mps2_scc_init(Object *obj) 241 { 242 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 243 MPS2SCC *s = MPS2_SCC(obj); 244 245 memory_region_init_io(&s->iomem, obj, &mps2_scc_ops, s, "mps2-scc", 0x1000); 246 sysbus_init_mmio(sbd, &s->iomem); 247 } 248 249 static void mps2_scc_realize(DeviceState *dev, Error **errp) 250 { 251 } 252 253 static const VMStateDescription mps2_scc_vmstate = { 254 .name = "mps2-scc", 255 .version_id = 1, 256 .minimum_version_id = 1, 257 .fields = (VMStateField[]) { 258 VMSTATE_UINT32(cfg0, MPS2SCC), 259 VMSTATE_UINT32(cfg1, MPS2SCC), 260 VMSTATE_UINT32(cfgdata_rtn, MPS2SCC), 261 VMSTATE_UINT32(cfgdata_out, MPS2SCC), 262 VMSTATE_UINT32(cfgctrl, MPS2SCC), 263 VMSTATE_UINT32(cfgstat, MPS2SCC), 264 VMSTATE_UINT32(dll, MPS2SCC), 265 VMSTATE_UINT32_ARRAY(oscclk, MPS2SCC, NUM_OSCCLK), 266 VMSTATE_END_OF_LIST() 267 } 268 }; 269 270 static Property mps2_scc_properties[] = { 271 /* Values for various read-only ID registers (which are specific 272 * to the board model or FPGA image) 273 */ 274 DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0), 275 DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0), 276 DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0), 277 /* These are the initial settings for the source clocks on the board. 278 * In hardware they can be configured via a config file read by the 279 * motherboard configuration controller to suit the FPGA image. 280 * These default values are used by most of the standard FPGA images. 281 */ 282 DEFINE_PROP_UINT32("oscclk0", MPS2SCC, oscclk_reset[0], 50000000), 283 DEFINE_PROP_UINT32("oscclk1", MPS2SCC, oscclk_reset[1], 24576000), 284 DEFINE_PROP_UINT32("oscclk2", MPS2SCC, oscclk_reset[2], 25000000), 285 DEFINE_PROP_END_OF_LIST(), 286 }; 287 288 static void mps2_scc_class_init(ObjectClass *klass, void *data) 289 { 290 DeviceClass *dc = DEVICE_CLASS(klass); 291 292 dc->realize = mps2_scc_realize; 293 dc->vmsd = &mps2_scc_vmstate; 294 dc->reset = mps2_scc_reset; 295 dc->props = mps2_scc_properties; 296 } 297 298 static const TypeInfo mps2_scc_info = { 299 .name = TYPE_MPS2_SCC, 300 .parent = TYPE_SYS_BUS_DEVICE, 301 .instance_size = sizeof(MPS2SCC), 302 .instance_init = mps2_scc_init, 303 .class_init = mps2_scc_class_init, 304 }; 305 306 static void mps2_scc_register_types(void) 307 { 308 type_register_static(&mps2_scc_info); 309 } 310 311 type_init(mps2_scc_register_types); 312