1 /* 2 * ARM MPS2 SCC emulation 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* This is a model of the SCC (Serial Communication Controller) 13 * found in the FPGA images of MPS2 development boards. 14 * 15 * Documentation of it can be found in the MPS2 TRM: 16 * https://developer.arm.com/documentation/100112/latest/ 17 * and also in the Application Notes documenting individual FPGA images. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/module.h" 23 #include "qemu/bitops.h" 24 #include "trace.h" 25 #include "hw/sysbus.h" 26 #include "migration/vmstate.h" 27 #include "hw/registerfields.h" 28 #include "hw/misc/mps2-scc.h" 29 #include "hw/misc/led.h" 30 #include "hw/qdev-properties.h" 31 32 REG32(CFG0, 0) 33 REG32(CFG1, 4) 34 REG32(CFG2, 8) 35 REG32(CFG3, 0xc) 36 REG32(CFG4, 0x10) 37 REG32(CFG5, 0x14) 38 REG32(CFG6, 0x18) 39 REG32(CFGDATA_RTN, 0xa0) 40 REG32(CFGDATA_OUT, 0xa4) 41 REG32(CFGCTRL, 0xa8) 42 FIELD(CFGCTRL, DEVICE, 0, 12) 43 FIELD(CFGCTRL, RES1, 12, 8) 44 FIELD(CFGCTRL, FUNCTION, 20, 6) 45 FIELD(CFGCTRL, RES2, 26, 4) 46 FIELD(CFGCTRL, WRITE, 30, 1) 47 FIELD(CFGCTRL, START, 31, 1) 48 REG32(CFGSTAT, 0xac) 49 FIELD(CFGSTAT, DONE, 0, 1) 50 FIELD(CFGSTAT, ERROR, 1, 1) 51 REG32(DLL, 0x100) 52 REG32(AID, 0xFF8) 53 REG32(ID, 0xFFC) 54 55 static int scc_partno(MPS2SCC *s) 56 { 57 /* Return the partno field of the SCC_ID (0x524, 0x511, etc) */ 58 return extract32(s->id, 4, 8); 59 } 60 61 /* Handle a write via the SYS_CFG channel to the specified function/device. 62 * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit). 63 */ 64 static bool scc_cfg_write(MPS2SCC *s, unsigned function, 65 unsigned device, uint32_t value) 66 { 67 trace_mps2_scc_cfg_write(function, device, value); 68 69 if (function != 1 || device >= s->num_oscclk) { 70 qemu_log_mask(LOG_GUEST_ERROR, 71 "MPS2 SCC config write: bad function %d device %d\n", 72 function, device); 73 return false; 74 } 75 76 s->oscclk[device] = value; 77 return true; 78 } 79 80 /* Handle a read via the SYS_CFG channel to the specified function/device. 81 * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit), 82 * or set *value on success. 83 */ 84 static bool scc_cfg_read(MPS2SCC *s, unsigned function, 85 unsigned device, uint32_t *value) 86 { 87 if (function != 1 || device >= s->num_oscclk) { 88 qemu_log_mask(LOG_GUEST_ERROR, 89 "MPS2 SCC config read: bad function %d device %d\n", 90 function, device); 91 return false; 92 } 93 94 *value = s->oscclk[device]; 95 96 trace_mps2_scc_cfg_read(function, device, *value); 97 return true; 98 } 99 100 static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) 101 { 102 MPS2SCC *s = MPS2_SCC(opaque); 103 uint64_t r; 104 105 switch (offset) { 106 case A_CFG0: 107 r = s->cfg0; 108 break; 109 case A_CFG1: 110 r = s->cfg1; 111 break; 112 case A_CFG2: 113 if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) { 114 /* CFG2 reserved on other boards */ 115 goto bad_offset; 116 } 117 r = s->cfg2; 118 break; 119 case A_CFG3: 120 if (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) { 121 /* CFG3 reserved on AN524 */ 122 goto bad_offset; 123 } 124 /* These are user-settable DIP switches on the board. We don't 125 * model that, so just return zeroes. 126 */ 127 r = 0; 128 break; 129 case A_CFG4: 130 r = s->cfg4; 131 break; 132 case A_CFG5: 133 if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) { 134 /* CFG5 reserved on other boards */ 135 goto bad_offset; 136 } 137 r = s->cfg5; 138 break; 139 case A_CFG6: 140 if (scc_partno(s) != 0x524) { 141 /* CFG6 reserved on other boards */ 142 goto bad_offset; 143 } 144 r = s->cfg6; 145 break; 146 case A_CFGDATA_RTN: 147 r = s->cfgdata_rtn; 148 break; 149 case A_CFGDATA_OUT: 150 r = s->cfgdata_out; 151 break; 152 case A_CFGCTRL: 153 r = s->cfgctrl; 154 break; 155 case A_CFGSTAT: 156 r = s->cfgstat; 157 break; 158 case A_DLL: 159 r = s->dll; 160 break; 161 case A_AID: 162 r = s->aid; 163 break; 164 case A_ID: 165 r = s->id; 166 break; 167 default: 168 bad_offset: 169 qemu_log_mask(LOG_GUEST_ERROR, 170 "MPS2 SCC read: bad offset %x\n", (int) offset); 171 r = 0; 172 break; 173 } 174 175 trace_mps2_scc_read(offset, r, size); 176 return r; 177 } 178 179 static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, 180 unsigned size) 181 { 182 MPS2SCC *s = MPS2_SCC(opaque); 183 184 trace_mps2_scc_write(offset, value, size); 185 186 switch (offset) { 187 case A_CFG0: 188 /* 189 * TODO on some boards bit 0 controls RAM remapping; 190 * on others bit 1 is CPU_WAIT. 191 */ 192 s->cfg0 = value; 193 break; 194 case A_CFG1: 195 s->cfg1 = value; 196 for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) { 197 led_set_state(s->led[i], extract32(value, i, 1)); 198 } 199 break; 200 case A_CFG2: 201 if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) { 202 /* CFG2 reserved on other boards */ 203 goto bad_offset; 204 } 205 /* AN524: QSPI Select signal */ 206 s->cfg2 = value; 207 break; 208 case A_CFG5: 209 if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) { 210 /* CFG5 reserved on other boards */ 211 goto bad_offset; 212 } 213 /* AN524: ACLK frequency in Hz */ 214 s->cfg5 = value; 215 break; 216 case A_CFG6: 217 if (scc_partno(s) != 0x524) { 218 /* CFG6 reserved on other boards */ 219 goto bad_offset; 220 } 221 /* AN524: Clock divider for BRAM */ 222 s->cfg6 = value; 223 break; 224 case A_CFGDATA_OUT: 225 s->cfgdata_out = value; 226 break; 227 case A_CFGCTRL: 228 /* Writing to CFGCTRL clears SYS_CFGSTAT */ 229 s->cfgstat = 0; 230 s->cfgctrl = value & ~(R_CFGCTRL_RES1_MASK | 231 R_CFGCTRL_RES2_MASK | 232 R_CFGCTRL_START_MASK); 233 234 if (value & R_CFGCTRL_START_MASK) { 235 /* Start bit set -- do a read or write (instantaneously) */ 236 int device = extract32(s->cfgctrl, R_CFGCTRL_DEVICE_SHIFT, 237 R_CFGCTRL_DEVICE_LENGTH); 238 int function = extract32(s->cfgctrl, R_CFGCTRL_FUNCTION_SHIFT, 239 R_CFGCTRL_FUNCTION_LENGTH); 240 241 s->cfgstat = R_CFGSTAT_DONE_MASK; 242 if (s->cfgctrl & R_CFGCTRL_WRITE_MASK) { 243 if (!scc_cfg_write(s, function, device, s->cfgdata_out)) { 244 s->cfgstat |= R_CFGSTAT_ERROR_MASK; 245 } 246 } else { 247 uint32_t result; 248 if (!scc_cfg_read(s, function, device, &result)) { 249 s->cfgstat |= R_CFGSTAT_ERROR_MASK; 250 } else { 251 s->cfgdata_rtn = result; 252 } 253 } 254 } 255 break; 256 case A_DLL: 257 /* DLL stands for Digital Locked Loop. 258 * Bits [31:24] (DLL_LOCK_MASK) are writable, and indicate a 259 * mask of which of the DLL_LOCKED bits [16:23] should be ORed 260 * together to determine the ALL_UNMASKED_DLLS_LOCKED bit [0]. 261 * For QEMU, our DLLs are always locked, so we can leave bit 0 262 * as 1 always and don't need to recalculate it. 263 */ 264 s->dll = deposit32(s->dll, 24, 8, extract32(value, 24, 8)); 265 break; 266 default: 267 bad_offset: 268 qemu_log_mask(LOG_GUEST_ERROR, 269 "MPS2 SCC write: bad offset 0x%x\n", (int) offset); 270 break; 271 } 272 } 273 274 static const MemoryRegionOps mps2_scc_ops = { 275 .read = mps2_scc_read, 276 .write = mps2_scc_write, 277 .endianness = DEVICE_LITTLE_ENDIAN, 278 }; 279 280 static void mps2_scc_reset(DeviceState *dev) 281 { 282 MPS2SCC *s = MPS2_SCC(dev); 283 int i; 284 285 trace_mps2_scc_reset(); 286 s->cfg0 = 0; 287 s->cfg1 = 0; 288 s->cfg2 = 0; 289 s->cfg5 = 0; 290 s->cfg6 = 0; 291 s->cfgdata_rtn = 0; 292 s->cfgdata_out = 0; 293 s->cfgctrl = 0x100000; 294 s->cfgstat = 0; 295 s->dll = 0xffff0001; 296 for (i = 0; i < s->num_oscclk; i++) { 297 s->oscclk[i] = s->oscclk_reset[i]; 298 } 299 for (i = 0; i < ARRAY_SIZE(s->led); i++) { 300 device_cold_reset(DEVICE(s->led[i])); 301 } 302 } 303 304 static void mps2_scc_init(Object *obj) 305 { 306 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 307 MPS2SCC *s = MPS2_SCC(obj); 308 309 memory_region_init_io(&s->iomem, obj, &mps2_scc_ops, s, "mps2-scc", 0x1000); 310 sysbus_init_mmio(sbd, &s->iomem); 311 } 312 313 static void mps2_scc_realize(DeviceState *dev, Error **errp) 314 { 315 MPS2SCC *s = MPS2_SCC(dev); 316 317 for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) { 318 char *name = g_strdup_printf("SCC LED%zu", i); 319 s->led[i] = led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH, 320 LED_COLOR_GREEN, name); 321 g_free(name); 322 } 323 324 s->oscclk = g_new0(uint32_t, s->num_oscclk); 325 } 326 327 static const VMStateDescription mps2_scc_vmstate = { 328 .name = "mps2-scc", 329 .version_id = 3, 330 .minimum_version_id = 3, 331 .fields = (VMStateField[]) { 332 VMSTATE_UINT32(cfg0, MPS2SCC), 333 VMSTATE_UINT32(cfg1, MPS2SCC), 334 VMSTATE_UINT32(cfg2, MPS2SCC), 335 /* cfg3, cfg4 are read-only so need not be migrated */ 336 VMSTATE_UINT32(cfg5, MPS2SCC), 337 VMSTATE_UINT32(cfg6, MPS2SCC), 338 VMSTATE_UINT32(cfgdata_rtn, MPS2SCC), 339 VMSTATE_UINT32(cfgdata_out, MPS2SCC), 340 VMSTATE_UINT32(cfgctrl, MPS2SCC), 341 VMSTATE_UINT32(cfgstat, MPS2SCC), 342 VMSTATE_UINT32(dll, MPS2SCC), 343 VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk, 344 0, vmstate_info_uint32, uint32_t), 345 VMSTATE_END_OF_LIST() 346 } 347 }; 348 349 static Property mps2_scc_properties[] = { 350 /* Values for various read-only ID registers (which are specific 351 * to the board model or FPGA image) 352 */ 353 DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0), 354 DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0), 355 DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0), 356 /* 357 * These are the initial settings for the source clocks on the board. 358 * In hardware they can be configured via a config file read by the 359 * motherboard configuration controller to suit the FPGA image. 360 */ 361 DEFINE_PROP_ARRAY("oscclk", MPS2SCC, num_oscclk, oscclk_reset, 362 qdev_prop_uint32, uint32_t), 363 DEFINE_PROP_END_OF_LIST(), 364 }; 365 366 static void mps2_scc_class_init(ObjectClass *klass, void *data) 367 { 368 DeviceClass *dc = DEVICE_CLASS(klass); 369 370 dc->realize = mps2_scc_realize; 371 dc->vmsd = &mps2_scc_vmstate; 372 dc->reset = mps2_scc_reset; 373 device_class_set_props(dc, mps2_scc_properties); 374 } 375 376 static const TypeInfo mps2_scc_info = { 377 .name = TYPE_MPS2_SCC, 378 .parent = TYPE_SYS_BUS_DEVICE, 379 .instance_size = sizeof(MPS2SCC), 380 .instance_init = mps2_scc_init, 381 .class_init = mps2_scc_class_init, 382 }; 383 384 static void mps2_scc_register_types(void) 385 { 386 type_register_static(&mps2_scc_info); 387 } 388 389 type_init(mps2_scc_register_types); 390