1 /* 2 * ARM MPS2 SCC emulation 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* This is a model of the SCC (Serial Communication Controller) 13 * found in the FPGA images of MPS2 development boards. 14 * 15 * Documentation of it can be found in the MPS2 TRM: 16 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100112_0100_03_en/index.html 17 * and also in the Application Notes documenting individual FPGA images. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/module.h" 23 #include "trace.h" 24 #include "hw/sysbus.h" 25 #include "hw/registerfields.h" 26 #include "hw/misc/mps2-scc.h" 27 28 REG32(CFG0, 0) 29 REG32(CFG1, 4) 30 REG32(CFG3, 0xc) 31 REG32(CFG4, 0x10) 32 REG32(CFGDATA_RTN, 0xa0) 33 REG32(CFGDATA_OUT, 0xa4) 34 REG32(CFGCTRL, 0xa8) 35 FIELD(CFGCTRL, DEVICE, 0, 12) 36 FIELD(CFGCTRL, RES1, 12, 8) 37 FIELD(CFGCTRL, FUNCTION, 20, 6) 38 FIELD(CFGCTRL, RES2, 26, 4) 39 FIELD(CFGCTRL, WRITE, 30, 1) 40 FIELD(CFGCTRL, START, 31, 1) 41 REG32(CFGSTAT, 0xac) 42 FIELD(CFGSTAT, DONE, 0, 1) 43 FIELD(CFGSTAT, ERROR, 1, 1) 44 REG32(DLL, 0x100) 45 REG32(AID, 0xFF8) 46 REG32(ID, 0xFFC) 47 48 /* Handle a write via the SYS_CFG channel to the specified function/device. 49 * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit). 50 */ 51 static bool scc_cfg_write(MPS2SCC *s, unsigned function, 52 unsigned device, uint32_t value) 53 { 54 trace_mps2_scc_cfg_write(function, device, value); 55 56 if (function != 1 || device >= NUM_OSCCLK) { 57 qemu_log_mask(LOG_GUEST_ERROR, 58 "MPS2 SCC config write: bad function %d device %d\n", 59 function, device); 60 return false; 61 } 62 63 s->oscclk[device] = value; 64 return true; 65 } 66 67 /* Handle a read via the SYS_CFG channel to the specified function/device. 68 * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit), 69 * or set *value on success. 70 */ 71 static bool scc_cfg_read(MPS2SCC *s, unsigned function, 72 unsigned device, uint32_t *value) 73 { 74 if (function != 1 || device >= NUM_OSCCLK) { 75 qemu_log_mask(LOG_GUEST_ERROR, 76 "MPS2 SCC config read: bad function %d device %d\n", 77 function, device); 78 return false; 79 } 80 81 *value = s->oscclk[device]; 82 83 trace_mps2_scc_cfg_read(function, device, *value); 84 return true; 85 } 86 87 static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) 88 { 89 MPS2SCC *s = MPS2_SCC(opaque); 90 uint64_t r; 91 92 switch (offset) { 93 case A_CFG0: 94 r = s->cfg0; 95 break; 96 case A_CFG1: 97 r = s->cfg1; 98 break; 99 case A_CFG3: 100 /* These are user-settable DIP switches on the board. We don't 101 * model that, so just return zeroes. 102 */ 103 r = 0; 104 break; 105 case A_CFG4: 106 r = s->cfg4; 107 break; 108 case A_CFGDATA_RTN: 109 r = s->cfgdata_rtn; 110 break; 111 case A_CFGDATA_OUT: 112 r = s->cfgdata_out; 113 break; 114 case A_CFGCTRL: 115 r = s->cfgctrl; 116 break; 117 case A_CFGSTAT: 118 r = s->cfgstat; 119 break; 120 case A_DLL: 121 r = s->dll; 122 break; 123 case A_AID: 124 r = s->aid; 125 break; 126 case A_ID: 127 r = s->id; 128 break; 129 default: 130 qemu_log_mask(LOG_GUEST_ERROR, 131 "MPS2 SCC read: bad offset %x\n", (int) offset); 132 r = 0; 133 break; 134 } 135 136 trace_mps2_scc_read(offset, r, size); 137 return r; 138 } 139 140 static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, 141 unsigned size) 142 { 143 MPS2SCC *s = MPS2_SCC(opaque); 144 145 trace_mps2_scc_write(offset, value, size); 146 147 switch (offset) { 148 case A_CFG0: 149 /* TODO on some boards bit 0 controls RAM remapping */ 150 s->cfg0 = value; 151 break; 152 case A_CFG1: 153 /* CFG1 bits [7:0] control the board LEDs. We don't currently have 154 * a mechanism for displaying this graphically, so use a trace event. 155 */ 156 trace_mps2_scc_leds(value & 0x80 ? '*' : '.', 157 value & 0x40 ? '*' : '.', 158 value & 0x20 ? '*' : '.', 159 value & 0x10 ? '*' : '.', 160 value & 0x08 ? '*' : '.', 161 value & 0x04 ? '*' : '.', 162 value & 0x02 ? '*' : '.', 163 value & 0x01 ? '*' : '.'); 164 s->cfg1 = value; 165 break; 166 case A_CFGDATA_OUT: 167 s->cfgdata_out = value; 168 break; 169 case A_CFGCTRL: 170 /* Writing to CFGCTRL clears SYS_CFGSTAT */ 171 s->cfgstat = 0; 172 s->cfgctrl = value & ~(R_CFGCTRL_RES1_MASK | 173 R_CFGCTRL_RES2_MASK | 174 R_CFGCTRL_START_MASK); 175 176 if (value & R_CFGCTRL_START_MASK) { 177 /* Start bit set -- do a read or write (instantaneously) */ 178 int device = extract32(s->cfgctrl, R_CFGCTRL_DEVICE_SHIFT, 179 R_CFGCTRL_DEVICE_LENGTH); 180 int function = extract32(s->cfgctrl, R_CFGCTRL_FUNCTION_SHIFT, 181 R_CFGCTRL_FUNCTION_LENGTH); 182 183 s->cfgstat = R_CFGSTAT_DONE_MASK; 184 if (s->cfgctrl & R_CFGCTRL_WRITE_MASK) { 185 if (!scc_cfg_write(s, function, device, s->cfgdata_out)) { 186 s->cfgstat |= R_CFGSTAT_ERROR_MASK; 187 } 188 } else { 189 uint32_t result; 190 if (!scc_cfg_read(s, function, device, &result)) { 191 s->cfgstat |= R_CFGSTAT_ERROR_MASK; 192 } else { 193 s->cfgdata_rtn = result; 194 } 195 } 196 } 197 break; 198 case A_DLL: 199 /* DLL stands for Digital Locked Loop. 200 * Bits [31:24] (DLL_LOCK_MASK) are writable, and indicate a 201 * mask of which of the DLL_LOCKED bits [16:23] should be ORed 202 * together to determine the ALL_UNMASKED_DLLS_LOCKED bit [0]. 203 * For QEMU, our DLLs are always locked, so we can leave bit 0 204 * as 1 always and don't need to recalculate it. 205 */ 206 s->dll = deposit32(s->dll, 24, 8, extract32(value, 24, 8)); 207 break; 208 default: 209 qemu_log_mask(LOG_GUEST_ERROR, 210 "MPS2 SCC write: bad offset 0x%x\n", (int) offset); 211 break; 212 } 213 } 214 215 static const MemoryRegionOps mps2_scc_ops = { 216 .read = mps2_scc_read, 217 .write = mps2_scc_write, 218 .endianness = DEVICE_LITTLE_ENDIAN, 219 }; 220 221 static void mps2_scc_reset(DeviceState *dev) 222 { 223 MPS2SCC *s = MPS2_SCC(dev); 224 int i; 225 226 trace_mps2_scc_reset(); 227 s->cfg0 = 0; 228 s->cfg1 = 0; 229 s->cfgdata_rtn = 0; 230 s->cfgdata_out = 0; 231 s->cfgctrl = 0x100000; 232 s->cfgstat = 0; 233 s->dll = 0xffff0001; 234 for (i = 0; i < NUM_OSCCLK; i++) { 235 s->oscclk[i] = s->oscclk_reset[i]; 236 } 237 } 238 239 static void mps2_scc_init(Object *obj) 240 { 241 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 242 MPS2SCC *s = MPS2_SCC(obj); 243 244 memory_region_init_io(&s->iomem, obj, &mps2_scc_ops, s, "mps2-scc", 0x1000); 245 sysbus_init_mmio(sbd, &s->iomem); 246 } 247 248 static void mps2_scc_realize(DeviceState *dev, Error **errp) 249 { 250 } 251 252 static const VMStateDescription mps2_scc_vmstate = { 253 .name = "mps2-scc", 254 .version_id = 1, 255 .minimum_version_id = 1, 256 .fields = (VMStateField[]) { 257 VMSTATE_UINT32(cfg0, MPS2SCC), 258 VMSTATE_UINT32(cfg1, MPS2SCC), 259 VMSTATE_UINT32(cfgdata_rtn, MPS2SCC), 260 VMSTATE_UINT32(cfgdata_out, MPS2SCC), 261 VMSTATE_UINT32(cfgctrl, MPS2SCC), 262 VMSTATE_UINT32(cfgstat, MPS2SCC), 263 VMSTATE_UINT32(dll, MPS2SCC), 264 VMSTATE_UINT32_ARRAY(oscclk, MPS2SCC, NUM_OSCCLK), 265 VMSTATE_END_OF_LIST() 266 } 267 }; 268 269 static Property mps2_scc_properties[] = { 270 /* Values for various read-only ID registers (which are specific 271 * to the board model or FPGA image) 272 */ 273 DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0), 274 DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0), 275 DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0), 276 /* These are the initial settings for the source clocks on the board. 277 * In hardware they can be configured via a config file read by the 278 * motherboard configuration controller to suit the FPGA image. 279 * These default values are used by most of the standard FPGA images. 280 */ 281 DEFINE_PROP_UINT32("oscclk0", MPS2SCC, oscclk_reset[0], 50000000), 282 DEFINE_PROP_UINT32("oscclk1", MPS2SCC, oscclk_reset[1], 24576000), 283 DEFINE_PROP_UINT32("oscclk2", MPS2SCC, oscclk_reset[2], 25000000), 284 DEFINE_PROP_END_OF_LIST(), 285 }; 286 287 static void mps2_scc_class_init(ObjectClass *klass, void *data) 288 { 289 DeviceClass *dc = DEVICE_CLASS(klass); 290 291 dc->realize = mps2_scc_realize; 292 dc->vmsd = &mps2_scc_vmstate; 293 dc->reset = mps2_scc_reset; 294 dc->props = mps2_scc_properties; 295 } 296 297 static const TypeInfo mps2_scc_info = { 298 .name = TYPE_MPS2_SCC, 299 .parent = TYPE_SYS_BUS_DEVICE, 300 .instance_size = sizeof(MPS2SCC), 301 .instance_init = mps2_scc_init, 302 .class_init = mps2_scc_class_init, 303 }; 304 305 static void mps2_scc_register_types(void) 306 { 307 type_register_static(&mps2_scc_info); 308 } 309 310 type_init(mps2_scc_register_types); 311