1 /* 2 * ARM MPS2 AN505 FPGAIO emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* This is a model of the "FPGA system control and I/O" block found 13 * in the AN505 FPGA image for the MPS2 devboard. 14 * It is documented in AN505: 15 * https://developer.arm.com/documentation/dai0505/latest/ 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/log.h" 20 #include "qemu/module.h" 21 #include "qapi/error.h" 22 #include "trace.h" 23 #include "hw/sysbus.h" 24 #include "migration/vmstate.h" 25 #include "hw/registerfields.h" 26 #include "hw/misc/mps2-fpgaio.h" 27 #include "hw/misc/led.h" 28 #include "hw/qdev-properties.h" 29 #include "qemu/timer.h" 30 31 REG32(LED0, 0) 32 REG32(BUTTON, 8) 33 REG32(CLK1HZ, 0x10) 34 REG32(CLK100HZ, 0x14) 35 REG32(COUNTER, 0x18) 36 REG32(PRESCALE, 0x1c) 37 REG32(PSCNTR, 0x20) 38 REG32(SWITCH, 0x28) 39 REG32(MISC, 0x4c) 40 41 static uint32_t counter_from_tickoff(int64_t now, int64_t tick_offset, int frq) 42 { 43 return muldiv64(now - tick_offset, frq, NANOSECONDS_PER_SECOND); 44 } 45 46 static int64_t tickoff_from_counter(int64_t now, uint32_t count, int frq) 47 { 48 return now - muldiv64(count, NANOSECONDS_PER_SECOND, frq); 49 } 50 51 static void resync_counter(MPS2FPGAIO *s) 52 { 53 /* 54 * Update s->counter and s->pscntr to their true current values 55 * by calculating how many times PSCNTR has ticked since the 56 * last time we did a resync. 57 */ 58 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 59 int64_t elapsed = now - s->pscntr_sync_ticks; 60 61 /* 62 * Round elapsed down to a whole number of PSCNTR ticks, so we don't 63 * lose time if we do multiple resyncs in a single tick. 64 */ 65 uint64_t ticks = muldiv64(elapsed, s->prescale_clk, NANOSECONDS_PER_SECOND); 66 67 /* 68 * Work out what PSCNTR and COUNTER have moved to. We assume that 69 * PSCNTR reloads from PRESCALE one tick-period after it hits zero, 70 * and that COUNTER increments at the same moment. 71 */ 72 if (ticks == 0) { 73 /* We haven't ticked since the last time we were asked */ 74 return; 75 } else if (ticks < s->pscntr) { 76 /* We haven't yet reached zero, just reduce the PSCNTR */ 77 s->pscntr -= ticks; 78 } else { 79 if (s->prescale == 0) { 80 /* 81 * If the reload value is zero then the PSCNTR will stick 82 * at zero once it reaches it, and so we will increment 83 * COUNTER every tick after that. 84 */ 85 s->counter += ticks - s->pscntr; 86 s->pscntr = 0; 87 } else { 88 /* 89 * This is the complicated bit. This ASCII art diagram gives an 90 * example with PRESCALE==5 PSCNTR==7: 91 * 92 * ticks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 93 * PSCNTR 7 6 5 4 3 2 1 0 5 4 3 2 1 0 5 94 * cinc 1 2 95 * y 0 1 2 3 4 5 6 7 8 9 10 11 12 96 * x 0 1 2 3 4 5 0 1 2 3 4 5 0 97 * 98 * where x = y % (s->prescale + 1) 99 * and so PSCNTR = s->prescale - x 100 * and COUNTER is incremented by y / (s->prescale + 1) 101 * 102 * The case where PSCNTR < PRESCALE works out the same, 103 * though we must be careful to calculate y as 64-bit unsigned 104 * for all parts of the expression. 105 * y < 0 is not possible because that implies ticks < s->pscntr. 106 */ 107 uint64_t y = ticks - s->pscntr + s->prescale; 108 s->pscntr = s->prescale - (y % (s->prescale + 1)); 109 s->counter += y / (s->prescale + 1); 110 } 111 } 112 113 /* 114 * Only advance the sync time to the timestamp of the last PSCNTR tick, 115 * not all the way to 'now', so we don't lose time if we do multiple 116 * resyncs in a single tick. 117 */ 118 s->pscntr_sync_ticks += muldiv64(ticks, NANOSECONDS_PER_SECOND, 119 s->prescale_clk); 120 } 121 122 static uint64_t mps2_fpgaio_read(void *opaque, hwaddr offset, unsigned size) 123 { 124 MPS2FPGAIO *s = MPS2_FPGAIO(opaque); 125 uint64_t r; 126 int64_t now; 127 128 switch (offset) { 129 case A_LED0: 130 r = s->led0; 131 break; 132 case A_BUTTON: 133 /* User-pressable board buttons. We don't model that, so just return 134 * zeroes. 135 */ 136 r = 0; 137 break; 138 case A_PRESCALE: 139 r = s->prescale; 140 break; 141 case A_MISC: 142 r = s->misc; 143 break; 144 case A_CLK1HZ: 145 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 146 r = counter_from_tickoff(now, s->clk1hz_tick_offset, 1); 147 break; 148 case A_CLK100HZ: 149 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 150 r = counter_from_tickoff(now, s->clk100hz_tick_offset, 100); 151 break; 152 case A_COUNTER: 153 resync_counter(s); 154 r = s->counter; 155 break; 156 case A_PSCNTR: 157 resync_counter(s); 158 r = s->pscntr; 159 break; 160 case A_SWITCH: 161 if (!s->has_switches) { 162 goto bad_offset; 163 } 164 /* User-togglable board switches. We don't model that, so report 0. */ 165 r = 0; 166 break; 167 default: 168 bad_offset: 169 qemu_log_mask(LOG_GUEST_ERROR, 170 "MPS2 FPGAIO read: bad offset %x\n", (int) offset); 171 r = 0; 172 break; 173 } 174 175 trace_mps2_fpgaio_read(offset, r, size); 176 return r; 177 } 178 179 static void mps2_fpgaio_write(void *opaque, hwaddr offset, uint64_t value, 180 unsigned size) 181 { 182 MPS2FPGAIO *s = MPS2_FPGAIO(opaque); 183 int64_t now; 184 185 trace_mps2_fpgaio_write(offset, value, size); 186 187 switch (offset) { 188 case A_LED0: 189 if (s->num_leds != 0) { 190 uint32_t i; 191 192 s->led0 = value & MAKE_64BIT_MASK(0, s->num_leds); 193 for (i = 0; i < s->num_leds; i++) { 194 led_set_state(s->led[i], value & (1 << i)); 195 } 196 } 197 break; 198 case A_PRESCALE: 199 resync_counter(s); 200 s->prescale = value; 201 break; 202 case A_MISC: 203 /* These are control bits for some of the other devices on the 204 * board (SPI, CLCD, etc). We don't implement that yet, so just 205 * make the bits read as written. 206 */ 207 qemu_log_mask(LOG_UNIMP, 208 "MPS2 FPGAIO: MISC control bits unimplemented\n"); 209 s->misc = value; 210 break; 211 case A_CLK1HZ: 212 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 213 s->clk1hz_tick_offset = tickoff_from_counter(now, value, 1); 214 break; 215 case A_CLK100HZ: 216 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 217 s->clk100hz_tick_offset = tickoff_from_counter(now, value, 100); 218 break; 219 case A_COUNTER: 220 resync_counter(s); 221 s->counter = value; 222 break; 223 case A_PSCNTR: 224 resync_counter(s); 225 s->pscntr = value; 226 break; 227 default: 228 qemu_log_mask(LOG_GUEST_ERROR, 229 "MPS2 FPGAIO write: bad offset 0x%x\n", (int) offset); 230 break; 231 } 232 } 233 234 static const MemoryRegionOps mps2_fpgaio_ops = { 235 .read = mps2_fpgaio_read, 236 .write = mps2_fpgaio_write, 237 .endianness = DEVICE_LITTLE_ENDIAN, 238 }; 239 240 static void mps2_fpgaio_reset(DeviceState *dev) 241 { 242 MPS2FPGAIO *s = MPS2_FPGAIO(dev); 243 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 244 245 trace_mps2_fpgaio_reset(); 246 s->led0 = 0; 247 s->prescale = 0; 248 s->misc = 0; 249 s->clk1hz_tick_offset = tickoff_from_counter(now, 0, 1); 250 s->clk100hz_tick_offset = tickoff_from_counter(now, 0, 100); 251 s->counter = 0; 252 s->pscntr = 0; 253 s->pscntr_sync_ticks = now; 254 255 for (size_t i = 0; i < s->num_leds; i++) { 256 device_cold_reset(DEVICE(s->led[i])); 257 } 258 } 259 260 static void mps2_fpgaio_init(Object *obj) 261 { 262 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 263 MPS2FPGAIO *s = MPS2_FPGAIO(obj); 264 265 memory_region_init_io(&s->iomem, obj, &mps2_fpgaio_ops, s, 266 "mps2-fpgaio", 0x1000); 267 sysbus_init_mmio(sbd, &s->iomem); 268 } 269 270 static void mps2_fpgaio_realize(DeviceState *dev, Error **errp) 271 { 272 MPS2FPGAIO *s = MPS2_FPGAIO(dev); 273 uint32_t i; 274 275 if (s->num_leds > MPS2FPGAIO_MAX_LEDS) { 276 error_setg(errp, "num-leds cannot be greater than %d", 277 MPS2FPGAIO_MAX_LEDS); 278 return; 279 } 280 281 for (i = 0; i < s->num_leds; i++) { 282 g_autofree char *ledname = g_strdup_printf("USERLED%d", i); 283 s->led[i] = led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH, 284 LED_COLOR_GREEN, ledname); 285 } 286 } 287 288 static bool mps2_fpgaio_counters_needed(void *opaque) 289 { 290 /* Currently vmstate.c insists all subsections have a 'needed' function */ 291 return true; 292 } 293 294 static const VMStateDescription mps2_fpgaio_counters_vmstate = { 295 .name = "mps2-fpgaio/counters", 296 .version_id = 2, 297 .minimum_version_id = 2, 298 .needed = mps2_fpgaio_counters_needed, 299 .fields = (VMStateField[]) { 300 VMSTATE_INT64(clk1hz_tick_offset, MPS2FPGAIO), 301 VMSTATE_INT64(clk100hz_tick_offset, MPS2FPGAIO), 302 VMSTATE_UINT32(counter, MPS2FPGAIO), 303 VMSTATE_UINT32(pscntr, MPS2FPGAIO), 304 VMSTATE_INT64(pscntr_sync_ticks, MPS2FPGAIO), 305 VMSTATE_END_OF_LIST() 306 } 307 }; 308 309 static const VMStateDescription mps2_fpgaio_vmstate = { 310 .name = "mps2-fpgaio", 311 .version_id = 1, 312 .minimum_version_id = 1, 313 .fields = (VMStateField[]) { 314 VMSTATE_UINT32(led0, MPS2FPGAIO), 315 VMSTATE_UINT32(prescale, MPS2FPGAIO), 316 VMSTATE_UINT32(misc, MPS2FPGAIO), 317 VMSTATE_END_OF_LIST() 318 }, 319 .subsections = (const VMStateDescription*[]) { 320 &mps2_fpgaio_counters_vmstate, 321 NULL 322 } 323 }; 324 325 static Property mps2_fpgaio_properties[] = { 326 /* Frequency of the prescale counter */ 327 DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000), 328 /* Number of LEDs controlled by LED0 register */ 329 DEFINE_PROP_UINT32("num-leds", MPS2FPGAIO, num_leds, 2), 330 DEFINE_PROP_BOOL("has-switches", MPS2FPGAIO, has_switches, false), 331 DEFINE_PROP_END_OF_LIST(), 332 }; 333 334 static void mps2_fpgaio_class_init(ObjectClass *klass, void *data) 335 { 336 DeviceClass *dc = DEVICE_CLASS(klass); 337 338 dc->vmsd = &mps2_fpgaio_vmstate; 339 dc->realize = mps2_fpgaio_realize; 340 dc->reset = mps2_fpgaio_reset; 341 device_class_set_props(dc, mps2_fpgaio_properties); 342 } 343 344 static const TypeInfo mps2_fpgaio_info = { 345 .name = TYPE_MPS2_FPGAIO, 346 .parent = TYPE_SYS_BUS_DEVICE, 347 .instance_size = sizeof(MPS2FPGAIO), 348 .instance_init = mps2_fpgaio_init, 349 .class_init = mps2_fpgaio_class_init, 350 }; 351 352 static void mps2_fpgaio_register_types(void) 353 { 354 type_register_static(&mps2_fpgaio_info); 355 } 356 357 type_init(mps2_fpgaio_register_types); 358