1 /* 2 * ARM MPS2 AN505 FPGAIO emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* This is a model of the "FPGA system control and I/O" block found 13 * in the AN505 FPGA image for the MPS2 devboard. 14 * It is documented in AN505: 15 * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/log.h" 20 #include "qemu/module.h" 21 #include "qapi/error.h" 22 #include "trace.h" 23 #include "hw/sysbus.h" 24 #include "migration/vmstate.h" 25 #include "hw/registerfields.h" 26 #include "hw/misc/mps2-fpgaio.h" 27 #include "hw/misc/led.h" 28 #include "hw/qdev-properties.h" 29 #include "qemu/timer.h" 30 31 REG32(LED0, 0) 32 REG32(BUTTON, 8) 33 REG32(CLK1HZ, 0x10) 34 REG32(CLK100HZ, 0x14) 35 REG32(COUNTER, 0x18) 36 REG32(PRESCALE, 0x1c) 37 REG32(PSCNTR, 0x20) 38 REG32(MISC, 0x4c) 39 40 static uint32_t counter_from_tickoff(int64_t now, int64_t tick_offset, int frq) 41 { 42 return muldiv64(now - tick_offset, frq, NANOSECONDS_PER_SECOND); 43 } 44 45 static int64_t tickoff_from_counter(int64_t now, uint32_t count, int frq) 46 { 47 return now - muldiv64(count, NANOSECONDS_PER_SECOND, frq); 48 } 49 50 static void resync_counter(MPS2FPGAIO *s) 51 { 52 /* 53 * Update s->counter and s->pscntr to their true current values 54 * by calculating how many times PSCNTR has ticked since the 55 * last time we did a resync. 56 */ 57 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 58 int64_t elapsed = now - s->pscntr_sync_ticks; 59 60 /* 61 * Round elapsed down to a whole number of PSCNTR ticks, so we don't 62 * lose time if we do multiple resyncs in a single tick. 63 */ 64 uint64_t ticks = muldiv64(elapsed, s->prescale_clk, NANOSECONDS_PER_SECOND); 65 66 /* 67 * Work out what PSCNTR and COUNTER have moved to. We assume that 68 * PSCNTR reloads from PRESCALE one tick-period after it hits zero, 69 * and that COUNTER increments at the same moment. 70 */ 71 if (ticks == 0) { 72 /* We haven't ticked since the last time we were asked */ 73 return; 74 } else if (ticks < s->pscntr) { 75 /* We haven't yet reached zero, just reduce the PSCNTR */ 76 s->pscntr -= ticks; 77 } else { 78 if (s->prescale == 0) { 79 /* 80 * If the reload value is zero then the PSCNTR will stick 81 * at zero once it reaches it, and so we will increment 82 * COUNTER every tick after that. 83 */ 84 s->counter += ticks - s->pscntr; 85 s->pscntr = 0; 86 } else { 87 /* 88 * This is the complicated bit. This ASCII art diagram gives an 89 * example with PRESCALE==5 PSCNTR==7: 90 * 91 * ticks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 92 * PSCNTR 7 6 5 4 3 2 1 0 5 4 3 2 1 0 5 93 * cinc 1 2 94 * y 0 1 2 3 4 5 6 7 8 9 10 11 12 95 * x 0 1 2 3 4 5 0 1 2 3 4 5 0 96 * 97 * where x = y % (s->prescale + 1) 98 * and so PSCNTR = s->prescale - x 99 * and COUNTER is incremented by y / (s->prescale + 1) 100 * 101 * The case where PSCNTR < PRESCALE works out the same, 102 * though we must be careful to calculate y as 64-bit unsigned 103 * for all parts of the expression. 104 * y < 0 is not possible because that implies ticks < s->pscntr. 105 */ 106 uint64_t y = ticks - s->pscntr + s->prescale; 107 s->pscntr = s->prescale - (y % (s->prescale + 1)); 108 s->counter += y / (s->prescale + 1); 109 } 110 } 111 112 /* 113 * Only advance the sync time to the timestamp of the last PSCNTR tick, 114 * not all the way to 'now', so we don't lose time if we do multiple 115 * resyncs in a single tick. 116 */ 117 s->pscntr_sync_ticks += muldiv64(ticks, NANOSECONDS_PER_SECOND, 118 s->prescale_clk); 119 } 120 121 static uint64_t mps2_fpgaio_read(void *opaque, hwaddr offset, unsigned size) 122 { 123 MPS2FPGAIO *s = MPS2_FPGAIO(opaque); 124 uint64_t r; 125 int64_t now; 126 127 switch (offset) { 128 case A_LED0: 129 r = s->led0; 130 break; 131 case A_BUTTON: 132 /* User-pressable board buttons. We don't model that, so just return 133 * zeroes. 134 */ 135 r = 0; 136 break; 137 case A_PRESCALE: 138 r = s->prescale; 139 break; 140 case A_MISC: 141 r = s->misc; 142 break; 143 case A_CLK1HZ: 144 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 145 r = counter_from_tickoff(now, s->clk1hz_tick_offset, 1); 146 break; 147 case A_CLK100HZ: 148 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 149 r = counter_from_tickoff(now, s->clk100hz_tick_offset, 100); 150 break; 151 case A_COUNTER: 152 resync_counter(s); 153 r = s->counter; 154 break; 155 case A_PSCNTR: 156 resync_counter(s); 157 r = s->pscntr; 158 break; 159 default: 160 qemu_log_mask(LOG_GUEST_ERROR, 161 "MPS2 FPGAIO read: bad offset %x\n", (int) offset); 162 r = 0; 163 break; 164 } 165 166 trace_mps2_fpgaio_read(offset, r, size); 167 return r; 168 } 169 170 static void mps2_fpgaio_write(void *opaque, hwaddr offset, uint64_t value, 171 unsigned size) 172 { 173 MPS2FPGAIO *s = MPS2_FPGAIO(opaque); 174 int64_t now; 175 176 trace_mps2_fpgaio_write(offset, value, size); 177 178 switch (offset) { 179 case A_LED0: 180 s->led0 = value & 0x3; 181 led_set_state(s->led[0], value & 0x01); 182 led_set_state(s->led[1], value & 0x02); 183 break; 184 case A_PRESCALE: 185 resync_counter(s); 186 s->prescale = value; 187 break; 188 case A_MISC: 189 /* These are control bits for some of the other devices on the 190 * board (SPI, CLCD, etc). We don't implement that yet, so just 191 * make the bits read as written. 192 */ 193 qemu_log_mask(LOG_UNIMP, 194 "MPS2 FPGAIO: MISC control bits unimplemented\n"); 195 s->misc = value; 196 break; 197 case A_CLK1HZ: 198 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 199 s->clk1hz_tick_offset = tickoff_from_counter(now, value, 1); 200 break; 201 case A_CLK100HZ: 202 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 203 s->clk100hz_tick_offset = tickoff_from_counter(now, value, 100); 204 break; 205 case A_COUNTER: 206 resync_counter(s); 207 s->counter = value; 208 break; 209 case A_PSCNTR: 210 resync_counter(s); 211 s->pscntr = value; 212 break; 213 default: 214 qemu_log_mask(LOG_GUEST_ERROR, 215 "MPS2 FPGAIO write: bad offset 0x%x\n", (int) offset); 216 break; 217 } 218 } 219 220 static const MemoryRegionOps mps2_fpgaio_ops = { 221 .read = mps2_fpgaio_read, 222 .write = mps2_fpgaio_write, 223 .endianness = DEVICE_LITTLE_ENDIAN, 224 }; 225 226 static void mps2_fpgaio_reset(DeviceState *dev) 227 { 228 MPS2FPGAIO *s = MPS2_FPGAIO(dev); 229 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 230 231 trace_mps2_fpgaio_reset(); 232 s->led0 = 0; 233 s->prescale = 0; 234 s->misc = 0; 235 s->clk1hz_tick_offset = tickoff_from_counter(now, 0, 1); 236 s->clk100hz_tick_offset = tickoff_from_counter(now, 0, 100); 237 s->counter = 0; 238 s->pscntr = 0; 239 s->pscntr_sync_ticks = now; 240 241 for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) { 242 device_cold_reset(DEVICE(s->led[i])); 243 } 244 } 245 246 static void mps2_fpgaio_init(Object *obj) 247 { 248 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 249 MPS2FPGAIO *s = MPS2_FPGAIO(obj); 250 251 memory_region_init_io(&s->iomem, obj, &mps2_fpgaio_ops, s, 252 "mps2-fpgaio", 0x1000); 253 sysbus_init_mmio(sbd, &s->iomem); 254 } 255 256 static void mps2_fpgaio_realize(DeviceState *dev, Error **errp) 257 { 258 MPS2FPGAIO *s = MPS2_FPGAIO(dev); 259 260 s->led[0] = led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH, 261 LED_COLOR_GREEN, "USERLED0"); 262 s->led[1] = led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH, 263 LED_COLOR_GREEN, "USERLED1"); 264 } 265 266 static bool mps2_fpgaio_counters_needed(void *opaque) 267 { 268 /* Currently vmstate.c insists all subsections have a 'needed' function */ 269 return true; 270 } 271 272 static const VMStateDescription mps2_fpgaio_counters_vmstate = { 273 .name = "mps2-fpgaio/counters", 274 .version_id = 2, 275 .minimum_version_id = 2, 276 .needed = mps2_fpgaio_counters_needed, 277 .fields = (VMStateField[]) { 278 VMSTATE_INT64(clk1hz_tick_offset, MPS2FPGAIO), 279 VMSTATE_INT64(clk100hz_tick_offset, MPS2FPGAIO), 280 VMSTATE_UINT32(counter, MPS2FPGAIO), 281 VMSTATE_UINT32(pscntr, MPS2FPGAIO), 282 VMSTATE_INT64(pscntr_sync_ticks, MPS2FPGAIO), 283 VMSTATE_END_OF_LIST() 284 } 285 }; 286 287 static const VMStateDescription mps2_fpgaio_vmstate = { 288 .name = "mps2-fpgaio", 289 .version_id = 1, 290 .minimum_version_id = 1, 291 .fields = (VMStateField[]) { 292 VMSTATE_UINT32(led0, MPS2FPGAIO), 293 VMSTATE_UINT32(prescale, MPS2FPGAIO), 294 VMSTATE_UINT32(misc, MPS2FPGAIO), 295 VMSTATE_END_OF_LIST() 296 }, 297 .subsections = (const VMStateDescription*[]) { 298 &mps2_fpgaio_counters_vmstate, 299 NULL 300 } 301 }; 302 303 static Property mps2_fpgaio_properties[] = { 304 /* Frequency of the prescale counter */ 305 DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000), 306 DEFINE_PROP_END_OF_LIST(), 307 }; 308 309 static void mps2_fpgaio_class_init(ObjectClass *klass, void *data) 310 { 311 DeviceClass *dc = DEVICE_CLASS(klass); 312 313 dc->vmsd = &mps2_fpgaio_vmstate; 314 dc->realize = mps2_fpgaio_realize; 315 dc->reset = mps2_fpgaio_reset; 316 device_class_set_props(dc, mps2_fpgaio_properties); 317 } 318 319 static const TypeInfo mps2_fpgaio_info = { 320 .name = TYPE_MPS2_FPGAIO, 321 .parent = TYPE_SYS_BUS_DEVICE, 322 .instance_size = sizeof(MPS2FPGAIO), 323 .instance_init = mps2_fpgaio_init, 324 .class_init = mps2_fpgaio_class_init, 325 }; 326 327 static void mps2_fpgaio_register_types(void) 328 { 329 type_register_static(&mps2_fpgaio_info); 330 } 331 332 type_init(mps2_fpgaio_register_types); 333