1 /* 2 * ARM MPS2 AN505 FPGAIO emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* This is a model of the "FPGA system control and I/O" block found 13 * in the AN505 FPGA image for the MPS2 devboard. 14 * It is documented in AN505: 15 * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/log.h" 20 #include "qapi/error.h" 21 #include "trace.h" 22 #include "hw/sysbus.h" 23 #include "hw/registerfields.h" 24 #include "hw/misc/mps2-fpgaio.h" 25 #include "qemu/timer.h" 26 27 REG32(LED0, 0) 28 REG32(BUTTON, 8) 29 REG32(CLK1HZ, 0x10) 30 REG32(CLK100HZ, 0x14) 31 REG32(COUNTER, 0x18) 32 REG32(PRESCALE, 0x1c) 33 REG32(PSCNTR, 0x20) 34 REG32(MISC, 0x4c) 35 36 static uint32_t counter_from_tickoff(int64_t now, int64_t tick_offset, int frq) 37 { 38 return muldiv64(now - tick_offset, frq, NANOSECONDS_PER_SECOND); 39 } 40 41 static int64_t tickoff_from_counter(int64_t now, uint32_t count, int frq) 42 { 43 return now - muldiv64(count, NANOSECONDS_PER_SECOND, frq); 44 } 45 46 static void resync_counter(MPS2FPGAIO *s) 47 { 48 /* 49 * Update s->counter and s->pscntr to their true current values 50 * by calculating how many times PSCNTR has ticked since the 51 * last time we did a resync. 52 */ 53 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 54 int64_t elapsed = now - s->pscntr_sync_ticks; 55 56 /* 57 * Round elapsed down to a whole number of PSCNTR ticks, so we don't 58 * lose time if we do multiple resyncs in a single tick. 59 */ 60 uint64_t ticks = muldiv64(elapsed, s->prescale_clk, NANOSECONDS_PER_SECOND); 61 62 /* 63 * Work out what PSCNTR and COUNTER have moved to. We assume that 64 * PSCNTR reloads from PRESCALE one tick-period after it hits zero, 65 * and that COUNTER increments at the same moment. 66 */ 67 if (ticks == 0) { 68 /* We haven't ticked since the last time we were asked */ 69 return; 70 } else if (ticks < s->pscntr) { 71 /* We haven't yet reached zero, just reduce the PSCNTR */ 72 s->pscntr -= ticks; 73 } else { 74 if (s->prescale == 0) { 75 /* 76 * If the reload value is zero then the PSCNTR will stick 77 * at zero once it reaches it, and so we will increment 78 * COUNTER every tick after that. 79 */ 80 s->counter += ticks - s->pscntr; 81 s->pscntr = 0; 82 } else { 83 /* 84 * This is the complicated bit. This ASCII art diagram gives an 85 * example with PRESCALE==5 PSCNTR==7: 86 * 87 * ticks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 88 * PSCNTR 7 6 5 4 3 2 1 0 5 4 3 2 1 0 5 89 * cinc 1 2 90 * y 0 1 2 3 4 5 6 7 8 9 10 11 12 91 * x 0 1 2 3 4 5 0 1 2 3 4 5 0 92 * 93 * where x = y % (s->prescale + 1) 94 * and so PSCNTR = s->prescale - x 95 * and COUNTER is incremented by y / (s->prescale + 1) 96 * 97 * The case where PSCNTR < PRESCALE works out the same, 98 * though we must be careful to calculate y as 64-bit unsigned 99 * for all parts of the expression. 100 * y < 0 is not possible because that implies ticks < s->pscntr. 101 */ 102 uint64_t y = ticks - s->pscntr + s->prescale; 103 s->pscntr = s->prescale - (y % (s->prescale + 1)); 104 s->counter += y / (s->prescale + 1); 105 } 106 } 107 108 /* 109 * Only advance the sync time to the timestamp of the last PSCNTR tick, 110 * not all the way to 'now', so we don't lose time if we do multiple 111 * resyncs in a single tick. 112 */ 113 s->pscntr_sync_ticks += muldiv64(ticks, NANOSECONDS_PER_SECOND, 114 s->prescale_clk); 115 } 116 117 static uint64_t mps2_fpgaio_read(void *opaque, hwaddr offset, unsigned size) 118 { 119 MPS2FPGAIO *s = MPS2_FPGAIO(opaque); 120 uint64_t r; 121 int64_t now; 122 123 switch (offset) { 124 case A_LED0: 125 r = s->led0; 126 break; 127 case A_BUTTON: 128 /* User-pressable board buttons. We don't model that, so just return 129 * zeroes. 130 */ 131 r = 0; 132 break; 133 case A_PRESCALE: 134 r = s->prescale; 135 break; 136 case A_MISC: 137 r = s->misc; 138 break; 139 case A_CLK1HZ: 140 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 141 r = counter_from_tickoff(now, s->clk1hz_tick_offset, 1); 142 break; 143 case A_CLK100HZ: 144 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 145 r = counter_from_tickoff(now, s->clk100hz_tick_offset, 100); 146 break; 147 case A_COUNTER: 148 resync_counter(s); 149 r = s->counter; 150 break; 151 case A_PSCNTR: 152 resync_counter(s); 153 r = s->pscntr; 154 break; 155 default: 156 qemu_log_mask(LOG_GUEST_ERROR, 157 "MPS2 FPGAIO read: bad offset %x\n", (int) offset); 158 r = 0; 159 break; 160 } 161 162 trace_mps2_fpgaio_read(offset, r, size); 163 return r; 164 } 165 166 static void mps2_fpgaio_write(void *opaque, hwaddr offset, uint64_t value, 167 unsigned size) 168 { 169 MPS2FPGAIO *s = MPS2_FPGAIO(opaque); 170 int64_t now; 171 172 trace_mps2_fpgaio_write(offset, value, size); 173 174 switch (offset) { 175 case A_LED0: 176 /* LED bits [1:0] control board LEDs. We don't currently have 177 * a mechanism for displaying this graphically, so use a trace event. 178 */ 179 trace_mps2_fpgaio_leds(value & 0x02 ? '*' : '.', 180 value & 0x01 ? '*' : '.'); 181 s->led0 = value & 0x3; 182 break; 183 case A_PRESCALE: 184 resync_counter(s); 185 s->prescale = value; 186 break; 187 case A_MISC: 188 /* These are control bits for some of the other devices on the 189 * board (SPI, CLCD, etc). We don't implement that yet, so just 190 * make the bits read as written. 191 */ 192 qemu_log_mask(LOG_UNIMP, 193 "MPS2 FPGAIO: MISC control bits unimplemented\n"); 194 s->misc = value; 195 break; 196 case A_CLK1HZ: 197 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 198 s->clk1hz_tick_offset = tickoff_from_counter(now, value, 1); 199 break; 200 case A_CLK100HZ: 201 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 202 s->clk100hz_tick_offset = tickoff_from_counter(now, value, 100); 203 break; 204 case A_COUNTER: 205 resync_counter(s); 206 s->counter = value; 207 break; 208 case A_PSCNTR: 209 resync_counter(s); 210 s->pscntr = value; 211 break; 212 default: 213 qemu_log_mask(LOG_GUEST_ERROR, 214 "MPS2 FPGAIO write: bad offset 0x%x\n", (int) offset); 215 break; 216 } 217 } 218 219 static const MemoryRegionOps mps2_fpgaio_ops = { 220 .read = mps2_fpgaio_read, 221 .write = mps2_fpgaio_write, 222 .endianness = DEVICE_LITTLE_ENDIAN, 223 }; 224 225 static void mps2_fpgaio_reset(DeviceState *dev) 226 { 227 MPS2FPGAIO *s = MPS2_FPGAIO(dev); 228 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 229 230 trace_mps2_fpgaio_reset(); 231 s->led0 = 0; 232 s->prescale = 0; 233 s->misc = 0; 234 s->clk1hz_tick_offset = tickoff_from_counter(now, 0, 1); 235 s->clk100hz_tick_offset = tickoff_from_counter(now, 0, 100); 236 s->counter = 0; 237 s->pscntr = 0; 238 s->pscntr_sync_ticks = now; 239 } 240 241 static void mps2_fpgaio_init(Object *obj) 242 { 243 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 244 MPS2FPGAIO *s = MPS2_FPGAIO(obj); 245 246 memory_region_init_io(&s->iomem, obj, &mps2_fpgaio_ops, s, 247 "mps2-fpgaio", 0x1000); 248 sysbus_init_mmio(sbd, &s->iomem); 249 } 250 251 static bool mps2_fpgaio_counters_needed(void *opaque) 252 { 253 /* Currently vmstate.c insists all subsections have a 'needed' function */ 254 return true; 255 } 256 257 static const VMStateDescription mps2_fpgaio_counters_vmstate = { 258 .name = "mps2-fpgaio/counters", 259 .version_id = 2, 260 .minimum_version_id = 2, 261 .needed = mps2_fpgaio_counters_needed, 262 .fields = (VMStateField[]) { 263 VMSTATE_INT64(clk1hz_tick_offset, MPS2FPGAIO), 264 VMSTATE_INT64(clk100hz_tick_offset, MPS2FPGAIO), 265 VMSTATE_UINT32(counter, MPS2FPGAIO), 266 VMSTATE_UINT32(pscntr, MPS2FPGAIO), 267 VMSTATE_INT64(pscntr_sync_ticks, MPS2FPGAIO), 268 VMSTATE_END_OF_LIST() 269 } 270 }; 271 272 static const VMStateDescription mps2_fpgaio_vmstate = { 273 .name = "mps2-fpgaio", 274 .version_id = 1, 275 .minimum_version_id = 1, 276 .fields = (VMStateField[]) { 277 VMSTATE_UINT32(led0, MPS2FPGAIO), 278 VMSTATE_UINT32(prescale, MPS2FPGAIO), 279 VMSTATE_UINT32(misc, MPS2FPGAIO), 280 VMSTATE_END_OF_LIST() 281 }, 282 .subsections = (const VMStateDescription*[]) { 283 &mps2_fpgaio_counters_vmstate, 284 NULL 285 } 286 }; 287 288 static Property mps2_fpgaio_properties[] = { 289 /* Frequency of the prescale counter */ 290 DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000), 291 DEFINE_PROP_END_OF_LIST(), 292 }; 293 294 static void mps2_fpgaio_class_init(ObjectClass *klass, void *data) 295 { 296 DeviceClass *dc = DEVICE_CLASS(klass); 297 298 dc->vmsd = &mps2_fpgaio_vmstate; 299 dc->reset = mps2_fpgaio_reset; 300 dc->props = mps2_fpgaio_properties; 301 } 302 303 static const TypeInfo mps2_fpgaio_info = { 304 .name = TYPE_MPS2_FPGAIO, 305 .parent = TYPE_SYS_BUS_DEVICE, 306 .instance_size = sizeof(MPS2FPGAIO), 307 .instance_init = mps2_fpgaio_init, 308 .class_init = mps2_fpgaio_class_init, 309 }; 310 311 static void mps2_fpgaio_register_types(void) 312 { 313 type_register_static(&mps2_fpgaio_info); 314 } 315 316 type_init(mps2_fpgaio_register_types); 317