xref: /openbmc/qemu/hw/misc/mos6522.c (revision dc5bd18f)
1 /*
2  * QEMU MOS6522 VIA emulation
3  *
4  * Copyright (c) 2004-2007 Fabrice Bellard
5  * Copyright (c) 2007 Jocelyn Mayer
6  * Copyright (c) 2018 Mark Cave-Ayland
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a copy
9  * of this software and associated documentation files (the "Software"), to deal
10  * in the Software without restriction, including without limitation the rights
11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12  * copies of the Software, and to permit persons to whom the Software is
13  * furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be included in
16  * all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24  * THE SOFTWARE.
25  */
26 #include "qemu/osdep.h"
27 #include "hw/hw.h"
28 #include "hw/input/adb.h"
29 #include "hw/misc/mos6522.h"
30 #include "qemu/timer.h"
31 #include "sysemu/sysemu.h"
32 #include "qemu/cutils.h"
33 #include "qemu/log.h"
34 #include "trace.h"
35 
36 /* XXX: implement all timer modes */
37 
38 static void mos6522_timer_update(MOS6522State *s, MOS6522Timer *ti,
39                                  int64_t current_time);
40 
41 static void mos6522_update_irq(MOS6522State *s)
42 {
43     if (s->ifr & s->ier & (SR_INT | T1_INT | T2_INT)) {
44         qemu_irq_raise(s->irq);
45     } else {
46         qemu_irq_lower(s->irq);
47     }
48 }
49 
50 static uint64_t get_counter_value(MOS6522State *s, MOS6522Timer *ti)
51 {
52     MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s);
53 
54     if (ti->index == 0) {
55         return mdc->get_timer1_counter_value(s, ti);
56     } else {
57         return mdc->get_timer2_counter_value(s, ti);
58     }
59 }
60 
61 static uint64_t get_load_time(MOS6522State *s, MOS6522Timer *ti)
62 {
63     MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s);
64 
65     if (ti->index == 0) {
66         return mdc->get_timer1_load_time(s, ti);
67     } else {
68         return mdc->get_timer2_load_time(s, ti);
69     }
70 }
71 
72 static unsigned int get_counter(MOS6522State *s, MOS6522Timer *ti)
73 {
74     int64_t d;
75     unsigned int counter;
76 
77     d = get_counter_value(s, ti);
78 
79     if (ti->index == 0) {
80         /* the timer goes down from latch to -1 (period of latch + 2) */
81         if (d <= (ti->counter_value + 1)) {
82             counter = (ti->counter_value - d) & 0xffff;
83         } else {
84             counter = (d - (ti->counter_value + 1)) % (ti->latch + 2);
85             counter = (ti->latch - counter) & 0xffff;
86         }
87     } else {
88         counter = (ti->counter_value - d) & 0xffff;
89     }
90     return counter;
91 }
92 
93 static void set_counter(MOS6522State *s, MOS6522Timer *ti, unsigned int val)
94 {
95     trace_mos6522_set_counter(1 + ti->index, val);
96     ti->load_time = get_load_time(s, ti);
97     ti->counter_value = val;
98     mos6522_timer_update(s, ti, ti->load_time);
99 }
100 
101 static int64_t get_next_irq_time(MOS6522State *s, MOS6522Timer *ti,
102                                  int64_t current_time)
103 {
104     int64_t d, next_time;
105     unsigned int counter;
106 
107     /* current counter value */
108     d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time,
109                  ti->frequency, NANOSECONDS_PER_SECOND);
110 
111     /* the timer goes down from latch to -1 (period of latch + 2) */
112     if (d <= (ti->counter_value + 1)) {
113         counter = (ti->counter_value - d) & 0xffff;
114     } else {
115         counter = (d - (ti->counter_value + 1)) % (ti->latch + 2);
116         counter = (ti->latch - counter) & 0xffff;
117     }
118 
119     /* Note: we consider the irq is raised on 0 */
120     if (counter == 0xffff) {
121         next_time = d + ti->latch + 1;
122     } else if (counter == 0) {
123         next_time = d + ti->latch + 2;
124     } else {
125         next_time = d + counter;
126     }
127     trace_mos6522_get_next_irq_time(ti->latch, d, next_time - d);
128     next_time = muldiv64(next_time, NANOSECONDS_PER_SECOND, ti->frequency) +
129                          ti->load_time;
130     if (next_time <= current_time) {
131         next_time = current_time + 1;
132     }
133     return next_time;
134 }
135 
136 static void mos6522_timer_update(MOS6522State *s, MOS6522Timer *ti,
137                                  int64_t current_time)
138 {
139     if (!ti->timer) {
140         return;
141     }
142     if (ti->index == 0 && (s->acr & T1MODE) != T1MODE_CONT) {
143         timer_del(ti->timer);
144     } else {
145         ti->next_irq_time = get_next_irq_time(s, ti, current_time);
146         timer_mod(ti->timer, ti->next_irq_time);
147     }
148 }
149 
150 static void mos6522_timer1(void *opaque)
151 {
152     MOS6522State *s = opaque;
153     MOS6522Timer *ti = &s->timers[0];
154 
155     mos6522_timer_update(s, ti, ti->next_irq_time);
156     s->ifr |= T1_INT;
157     mos6522_update_irq(s);
158 }
159 
160 static void mos6522_timer2(void *opaque)
161 {
162     MOS6522State *s = opaque;
163     MOS6522Timer *ti = &s->timers[1];
164 
165     mos6522_timer_update(s, ti, ti->next_irq_time);
166     s->ifr |= T2_INT;
167     mos6522_update_irq(s);
168 }
169 
170 static void mos6522_set_sr_int(MOS6522State *s)
171 {
172     trace_mos6522_set_sr_int();
173     s->ifr |= SR_INT;
174     mos6522_update_irq(s);
175 }
176 
177 static uint64_t mos6522_get_counter_value(MOS6522State *s, MOS6522Timer *ti)
178 {
179     uint64_t d;
180 
181     d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time,
182                  ti->frequency, NANOSECONDS_PER_SECOND);
183 
184     return d;
185 }
186 
187 static uint64_t mos6522_get_load_time(MOS6522State *s, MOS6522Timer *ti)
188 {
189     uint64_t load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
190 
191     return load_time;
192 }
193 
194 static void mos6522_portA_write(MOS6522State *s)
195 {
196     qemu_log_mask(LOG_UNIMP, "portA_write unimplemented");
197 }
198 
199 static void mos6522_portB_write(MOS6522State *s)
200 {
201     qemu_log_mask(LOG_UNIMP, "portB_write unimplemented");
202 }
203 
204 uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size)
205 {
206     MOS6522State *s = opaque;
207     uint32_t val;
208 
209     switch (addr) {
210     case VIA_REG_B:
211         val = s->b;
212         break;
213     case VIA_REG_A:
214         val = s->a;
215         break;
216     case VIA_REG_DIRB:
217         val = s->dirb;
218         break;
219     case VIA_REG_DIRA:
220         val = s->dira;
221         break;
222     case VIA_REG_T1CL:
223         val = get_counter(s, &s->timers[0]) & 0xff;
224         s->ifr &= ~T1_INT;
225         mos6522_update_irq(s);
226         break;
227     case VIA_REG_T1CH:
228         val = get_counter(s, &s->timers[0]) >> 8;
229         mos6522_update_irq(s);
230         break;
231     case VIA_REG_T1LL:
232         val = s->timers[0].latch & 0xff;
233         break;
234     case VIA_REG_T1LH:
235         /* XXX: check this */
236         val = (s->timers[0].latch >> 8) & 0xff;
237         break;
238     case VIA_REG_T2CL:
239         val = get_counter(s, &s->timers[1]) & 0xff;
240         s->ifr &= ~T2_INT;
241         mos6522_update_irq(s);
242         break;
243     case VIA_REG_T2CH:
244         val = get_counter(s, &s->timers[1]) >> 8;
245         break;
246     case VIA_REG_SR:
247         val = s->sr;
248         s->ifr &= ~(SR_INT | CB1_INT | CB2_INT);
249         mos6522_update_irq(s);
250         break;
251     case VIA_REG_ACR:
252         val = s->acr;
253         break;
254     case VIA_REG_PCR:
255         val = s->pcr;
256         break;
257     case VIA_REG_IFR:
258         val = s->ifr;
259         if (s->ifr & s->ier) {
260             val |= 0x80;
261         }
262         break;
263     case VIA_REG_IER:
264         val = s->ier | 0x80;
265         break;
266     default:
267     case VIA_REG_ANH:
268         val = s->anh;
269         break;
270     }
271 
272     if (addr != VIA_REG_IFR || val != 0) {
273         trace_mos6522_read(addr, val);
274     }
275 
276     return val;
277 }
278 
279 void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
280 {
281     MOS6522State *s = opaque;
282     MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s);
283 
284     trace_mos6522_write(addr, val);
285 
286     switch (addr) {
287     case VIA_REG_B:
288         s->b = (s->b & ~s->dirb) | (val & s->dirb);
289         mdc->portB_write(s);
290         break;
291     case VIA_REG_A:
292         s->a = (s->a & ~s->dira) | (val & s->dira);
293         mdc->portA_write(s);
294         break;
295     case VIA_REG_DIRB:
296         s->dirb = val;
297         break;
298     case VIA_REG_DIRA:
299         s->dira = val;
300         break;
301     case VIA_REG_T1CL:
302         s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
303         mos6522_timer_update(s, &s->timers[0],
304                              qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
305         break;
306     case VIA_REG_T1CH:
307         s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
308         s->ifr &= ~T1_INT;
309         set_counter(s, &s->timers[0], s->timers[0].latch);
310         break;
311     case VIA_REG_T1LL:
312         s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
313         mos6522_timer_update(s, &s->timers[0],
314                              qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
315         break;
316     case VIA_REG_T1LH:
317         s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
318         s->ifr &= ~T1_INT;
319         mos6522_timer_update(s, &s->timers[0],
320                              qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
321         break;
322     case VIA_REG_T2CL:
323         s->timers[1].latch = (s->timers[1].latch & 0xff00) | val;
324         break;
325     case VIA_REG_T2CH:
326         /* To ensure T2 generates an interrupt on zero crossing with the
327            common timer code, write the value directly from the latch to
328            the counter */
329         s->timers[1].latch = (s->timers[1].latch & 0xff) | (val << 8);
330         s->ifr &= ~T2_INT;
331         set_counter(s, &s->timers[1], s->timers[1].latch);
332         break;
333     case VIA_REG_SR:
334         s->sr = val;
335         break;
336     case VIA_REG_ACR:
337         s->acr = val;
338         mos6522_timer_update(s, &s->timers[0],
339                              qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
340         break;
341     case VIA_REG_PCR:
342         s->pcr = val;
343         break;
344     case VIA_REG_IFR:
345         /* reset bits */
346         s->ifr &= ~val;
347         mos6522_update_irq(s);
348         break;
349     case VIA_REG_IER:
350         if (val & IER_SET) {
351             /* set bits */
352             s->ier |= val & 0x7f;
353         } else {
354             /* reset bits */
355             s->ier &= ~val;
356         }
357         mos6522_update_irq(s);
358         break;
359     default:
360     case VIA_REG_ANH:
361         s->anh = val;
362         break;
363     }
364 }
365 
366 static const MemoryRegionOps mos6522_ops = {
367     .read = mos6522_read,
368     .write = mos6522_write,
369     .endianness = DEVICE_NATIVE_ENDIAN,
370     .valid = {
371         .min_access_size = 1,
372         .max_access_size = 1,
373     },
374 };
375 
376 static bool mos6522_timer_exist(void *opaque, int version_id)
377 {
378     MOS6522Timer *s = opaque;
379 
380     return s->timer != NULL;
381 }
382 
383 static const VMStateDescription vmstate_mos6522_timer = {
384     .name = "mos6522_timer",
385     .version_id = 0,
386     .minimum_version_id = 0,
387     .fields = (VMStateField[]) {
388         VMSTATE_UINT16(latch, MOS6522Timer),
389         VMSTATE_UINT16(counter_value, MOS6522Timer),
390         VMSTATE_INT64(load_time, MOS6522Timer),
391         VMSTATE_INT64(next_irq_time, MOS6522Timer),
392         VMSTATE_TIMER_PTR_TEST(timer, MOS6522Timer, mos6522_timer_exist),
393         VMSTATE_END_OF_LIST()
394     }
395 };
396 
397 static const VMStateDescription vmstate_mos6522 = {
398     .name = "mos6522",
399     .version_id = 0,
400     .minimum_version_id = 0,
401     .fields = (VMStateField[]) {
402         VMSTATE_UINT8(a, MOS6522State),
403         VMSTATE_UINT8(b, MOS6522State),
404         VMSTATE_UINT8(dira, MOS6522State),
405         VMSTATE_UINT8(dirb, MOS6522State),
406         VMSTATE_UINT8(sr, MOS6522State),
407         VMSTATE_UINT8(acr, MOS6522State),
408         VMSTATE_UINT8(pcr, MOS6522State),
409         VMSTATE_UINT8(ifr, MOS6522State),
410         VMSTATE_UINT8(ier, MOS6522State),
411         VMSTATE_UINT8(anh, MOS6522State),
412         VMSTATE_STRUCT_ARRAY(timers, MOS6522State, 2, 1,
413                              vmstate_mos6522_timer, MOS6522Timer),
414         VMSTATE_END_OF_LIST()
415     }
416 };
417 
418 static void mos6522_reset(DeviceState *dev)
419 {
420     MOS6522State *s = MOS6522(dev);
421 
422     s->b = 0;
423     s->a = 0;
424     s->dirb = 0xff;
425     s->dira = 0;
426     s->sr = 0;
427     s->acr = 0;
428     s->pcr = 0;
429     s->ifr = 0;
430     s->ier = 0;
431     /* s->ier = T1_INT | SR_INT; */
432     s->anh = 0;
433 
434     s->timers[0].latch = 0xffff;
435     set_counter(s, &s->timers[0], 0xffff);
436 
437     s->timers[1].latch = 0xffff;
438 }
439 
440 static void mos6522_realize(DeviceState *dev, Error **errp)
441 {
442     MOS6522State *s = MOS6522(dev);
443 
444     s->timers[0].frequency = s->frequency;
445     s->timers[1].frequency = s->frequency;
446 }
447 
448 static void mos6522_init(Object *obj)
449 {
450     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
451     MOS6522State *s = MOS6522(obj);
452     int i;
453 
454     memory_region_init_io(&s->mem, obj, &mos6522_ops, s, "mos6522", 0x10);
455     sysbus_init_mmio(sbd, &s->mem);
456     sysbus_init_irq(sbd, &s->irq);
457 
458     for (i = 0; i < ARRAY_SIZE(s->timers); i++) {
459         s->timers[i].index = i;
460     }
461 
462     s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer1, s);
463     s->timers[1].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer2, s);
464 }
465 
466 static Property mos6522_properties[] = {
467     DEFINE_PROP_UINT64("frequency", MOS6522State, frequency, 0),
468     DEFINE_PROP_END_OF_LIST()
469 };
470 
471 static void mos6522_class_init(ObjectClass *oc, void *data)
472 {
473     DeviceClass *dc = DEVICE_CLASS(oc);
474     MOS6522DeviceClass *mdc = MOS6522_DEVICE_CLASS(oc);
475 
476     dc->realize = mos6522_realize;
477     dc->reset = mos6522_reset;
478     dc->vmsd = &vmstate_mos6522;
479     dc->props = mos6522_properties;
480     mdc->parent_realize = dc->realize;
481     mdc->set_sr_int = mos6522_set_sr_int;
482     mdc->portB_write = mos6522_portB_write;
483     mdc->portA_write = mos6522_portA_write;
484     mdc->get_timer1_counter_value = mos6522_get_counter_value;
485     mdc->get_timer2_counter_value = mos6522_get_counter_value;
486     mdc->get_timer1_load_time = mos6522_get_load_time;
487     mdc->get_timer2_load_time = mos6522_get_load_time;
488 }
489 
490 static const TypeInfo mos6522_type_info = {
491     .name = TYPE_MOS6522,
492     .parent = TYPE_SYS_BUS_DEVICE,
493     .instance_size = sizeof(MOS6522State),
494     .instance_init = mos6522_init,
495     .abstract = true,
496     .class_size = sizeof(MOS6522DeviceClass),
497     .class_init = mos6522_class_init,
498 };
499 
500 static void mos6522_register_types(void)
501 {
502     type_register_static(&mos6522_type_info);
503 }
504 
505 type_init(mos6522_register_types)
506