1 /* 2 * QEMU MOS6522 VIA emulation 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2018 Mark Cave-Ayland 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "hw/input/adb.h" 29 #include "hw/irq.h" 30 #include "hw/misc/mos6522.h" 31 #include "hw/qdev-properties.h" 32 #include "migration/vmstate.h" 33 #include "qemu/timer.h" 34 #include "qemu/cutils.h" 35 #include "qemu/log.h" 36 #include "qemu/module.h" 37 #include "trace.h" 38 39 /* XXX: implement all timer modes */ 40 41 static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti, 42 int64_t current_time); 43 static void mos6522_timer2_update(MOS6522State *s, MOS6522Timer *ti, 44 int64_t current_time); 45 46 static void mos6522_update_irq(MOS6522State *s) 47 { 48 if (s->ifr & s->ier) { 49 qemu_irq_raise(s->irq); 50 } else { 51 qemu_irq_lower(s->irq); 52 } 53 } 54 55 static uint64_t get_counter_value(MOS6522State *s, MOS6522Timer *ti) 56 { 57 MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s); 58 59 if (ti->index == 0) { 60 return mdc->get_timer1_counter_value(s, ti); 61 } else { 62 return mdc->get_timer2_counter_value(s, ti); 63 } 64 } 65 66 static uint64_t get_load_time(MOS6522State *s, MOS6522Timer *ti) 67 { 68 MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s); 69 70 if (ti->index == 0) { 71 return mdc->get_timer1_load_time(s, ti); 72 } else { 73 return mdc->get_timer2_load_time(s, ti); 74 } 75 } 76 77 static unsigned int get_counter(MOS6522State *s, MOS6522Timer *ti) 78 { 79 int64_t d; 80 unsigned int counter; 81 82 d = get_counter_value(s, ti); 83 84 if (ti->index == 0) { 85 /* the timer goes down from latch to -1 (period of latch + 2) */ 86 if (d <= (ti->counter_value + 1)) { 87 counter = (ti->counter_value - d) & 0xffff; 88 } else { 89 counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); 90 counter = (ti->latch - counter) & 0xffff; 91 } 92 } else { 93 counter = (ti->counter_value - d) & 0xffff; 94 } 95 return counter; 96 } 97 98 static void set_counter(MOS6522State *s, MOS6522Timer *ti, unsigned int val) 99 { 100 trace_mos6522_set_counter(1 + ti->index, val); 101 ti->load_time = get_load_time(s, ti); 102 ti->counter_value = val; 103 if (ti->index == 0) { 104 mos6522_timer1_update(s, ti, ti->load_time); 105 } else { 106 mos6522_timer2_update(s, ti, ti->load_time); 107 } 108 } 109 110 static int64_t get_next_irq_time(MOS6522State *s, MOS6522Timer *ti, 111 int64_t current_time) 112 { 113 int64_t d, next_time; 114 unsigned int counter; 115 116 /* current counter value */ 117 d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, 118 ti->frequency, NANOSECONDS_PER_SECOND); 119 120 /* the timer goes down from latch to -1 (period of latch + 2) */ 121 if (d <= (ti->counter_value + 1)) { 122 counter = (ti->counter_value - d) & 0xffff; 123 } else { 124 counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); 125 counter = (ti->latch - counter) & 0xffff; 126 } 127 128 /* Note: we consider the irq is raised on 0 */ 129 if (counter == 0xffff) { 130 next_time = d + ti->latch + 1; 131 } else if (counter == 0) { 132 next_time = d + ti->latch + 2; 133 } else { 134 next_time = d + counter; 135 } 136 trace_mos6522_get_next_irq_time(ti->latch, d, next_time - d); 137 next_time = muldiv64(next_time, NANOSECONDS_PER_SECOND, ti->frequency) + 138 ti->load_time; 139 140 if (next_time <= current_time) { 141 next_time = current_time + 1; 142 } 143 return next_time; 144 } 145 146 static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti, 147 int64_t current_time) 148 { 149 if (!ti->timer) { 150 return; 151 } 152 if ((s->ier & T1_INT) == 0 || (s->acr & T1MODE) != T1MODE_CONT) { 153 timer_del(ti->timer); 154 } else { 155 ti->next_irq_time = get_next_irq_time(s, ti, current_time); 156 timer_mod(ti->timer, ti->next_irq_time); 157 } 158 } 159 160 static void mos6522_timer2_update(MOS6522State *s, MOS6522Timer *ti, 161 int64_t current_time) 162 { 163 if (!ti->timer) { 164 return; 165 } 166 if ((s->ier & T2_INT) == 0) { 167 timer_del(ti->timer); 168 } else { 169 ti->next_irq_time = get_next_irq_time(s, ti, current_time); 170 timer_mod(ti->timer, ti->next_irq_time); 171 } 172 } 173 174 static void mos6522_timer1(void *opaque) 175 { 176 MOS6522State *s = opaque; 177 MOS6522Timer *ti = &s->timers[0]; 178 179 mos6522_timer1_update(s, ti, ti->next_irq_time); 180 s->ifr |= T1_INT; 181 mos6522_update_irq(s); 182 } 183 184 static void mos6522_timer2(void *opaque) 185 { 186 MOS6522State *s = opaque; 187 MOS6522Timer *ti = &s->timers[1]; 188 189 mos6522_timer2_update(s, ti, ti->next_irq_time); 190 s->ifr |= T2_INT; 191 mos6522_update_irq(s); 192 } 193 194 static void mos6522_set_sr_int(MOS6522State *s) 195 { 196 trace_mos6522_set_sr_int(); 197 s->ifr |= SR_INT; 198 mos6522_update_irq(s); 199 } 200 201 static uint64_t mos6522_get_counter_value(MOS6522State *s, MOS6522Timer *ti) 202 { 203 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, 204 ti->frequency, NANOSECONDS_PER_SECOND); 205 } 206 207 static uint64_t mos6522_get_load_time(MOS6522State *s, MOS6522Timer *ti) 208 { 209 uint64_t load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 210 211 return load_time; 212 } 213 214 static void mos6522_portA_write(MOS6522State *s) 215 { 216 qemu_log_mask(LOG_UNIMP, "portA_write unimplemented\n"); 217 } 218 219 static void mos6522_portB_write(MOS6522State *s) 220 { 221 qemu_log_mask(LOG_UNIMP, "portB_write unimplemented\n"); 222 } 223 224 uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) 225 { 226 MOS6522State *s = opaque; 227 uint32_t val; 228 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 229 230 if (now >= s->timers[0].next_irq_time) { 231 mos6522_timer1_update(s, &s->timers[0], now); 232 s->ifr |= T1_INT; 233 } 234 if (now >= s->timers[1].next_irq_time) { 235 mos6522_timer2_update(s, &s->timers[1], now); 236 s->ifr |= T2_INT; 237 } 238 switch (addr) { 239 case VIA_REG_B: 240 val = s->b; 241 break; 242 case VIA_REG_A: 243 val = s->a; 244 break; 245 case VIA_REG_DIRB: 246 val = s->dirb; 247 break; 248 case VIA_REG_DIRA: 249 val = s->dira; 250 break; 251 case VIA_REG_T1CL: 252 val = get_counter(s, &s->timers[0]) & 0xff; 253 s->ifr &= ~T1_INT; 254 mos6522_update_irq(s); 255 break; 256 case VIA_REG_T1CH: 257 val = get_counter(s, &s->timers[0]) >> 8; 258 mos6522_update_irq(s); 259 break; 260 case VIA_REG_T1LL: 261 val = s->timers[0].latch & 0xff; 262 break; 263 case VIA_REG_T1LH: 264 /* XXX: check this */ 265 val = (s->timers[0].latch >> 8) & 0xff; 266 break; 267 case VIA_REG_T2CL: 268 val = get_counter(s, &s->timers[1]) & 0xff; 269 s->ifr &= ~T2_INT; 270 mos6522_update_irq(s); 271 break; 272 case VIA_REG_T2CH: 273 val = get_counter(s, &s->timers[1]) >> 8; 274 break; 275 case VIA_REG_SR: 276 val = s->sr; 277 s->ifr &= ~SR_INT; 278 mos6522_update_irq(s); 279 break; 280 case VIA_REG_ACR: 281 val = s->acr; 282 break; 283 case VIA_REG_PCR: 284 val = s->pcr; 285 break; 286 case VIA_REG_IFR: 287 val = s->ifr; 288 if (s->ifr & s->ier) { 289 val |= 0x80; 290 } 291 break; 292 case VIA_REG_IER: 293 val = s->ier | 0x80; 294 break; 295 default: 296 case VIA_REG_ANH: 297 val = s->anh; 298 break; 299 } 300 301 if (addr != VIA_REG_IFR || val != 0) { 302 trace_mos6522_read(addr, val); 303 } 304 305 return val; 306 } 307 308 void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) 309 { 310 MOS6522State *s = opaque; 311 MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s); 312 313 trace_mos6522_write(addr, val); 314 315 switch (addr) { 316 case VIA_REG_B: 317 s->b = (s->b & ~s->dirb) | (val & s->dirb); 318 mdc->portB_write(s); 319 break; 320 case VIA_REG_A: 321 s->a = (s->a & ~s->dira) | (val & s->dira); 322 mdc->portA_write(s); 323 break; 324 case VIA_REG_DIRB: 325 s->dirb = val; 326 break; 327 case VIA_REG_DIRA: 328 s->dira = val; 329 break; 330 case VIA_REG_T1CL: 331 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; 332 mos6522_timer1_update(s, &s->timers[0], 333 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 334 break; 335 case VIA_REG_T1CH: 336 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); 337 s->ifr &= ~T1_INT; 338 set_counter(s, &s->timers[0], s->timers[0].latch); 339 break; 340 case VIA_REG_T1LL: 341 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; 342 mos6522_timer1_update(s, &s->timers[0], 343 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 344 break; 345 case VIA_REG_T1LH: 346 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); 347 s->ifr &= ~T1_INT; 348 mos6522_timer1_update(s, &s->timers[0], 349 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 350 break; 351 case VIA_REG_T2CL: 352 s->timers[1].latch = (s->timers[1].latch & 0xff00) | val; 353 break; 354 case VIA_REG_T2CH: 355 /* To ensure T2 generates an interrupt on zero crossing with the 356 common timer code, write the value directly from the latch to 357 the counter */ 358 s->timers[1].latch = (s->timers[1].latch & 0xff) | (val << 8); 359 s->ifr &= ~T2_INT; 360 set_counter(s, &s->timers[1], s->timers[1].latch); 361 break; 362 case VIA_REG_SR: 363 s->sr = val; 364 break; 365 case VIA_REG_ACR: 366 s->acr = val; 367 mos6522_timer1_update(s, &s->timers[0], 368 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 369 break; 370 case VIA_REG_PCR: 371 s->pcr = val; 372 break; 373 case VIA_REG_IFR: 374 /* reset bits */ 375 s->ifr &= ~val; 376 mos6522_update_irq(s); 377 break; 378 case VIA_REG_IER: 379 if (val & IER_SET) { 380 /* set bits */ 381 s->ier |= val & 0x7f; 382 } else { 383 /* reset bits */ 384 s->ier &= ~val; 385 } 386 mos6522_update_irq(s); 387 /* if IER is modified starts needed timers */ 388 mos6522_timer1_update(s, &s->timers[0], 389 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 390 mos6522_timer2_update(s, &s->timers[1], 391 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 392 break; 393 default: 394 case VIA_REG_ANH: 395 s->anh = val; 396 break; 397 } 398 } 399 400 static const MemoryRegionOps mos6522_ops = { 401 .read = mos6522_read, 402 .write = mos6522_write, 403 .endianness = DEVICE_NATIVE_ENDIAN, 404 .valid = { 405 .min_access_size = 1, 406 .max_access_size = 1, 407 }, 408 }; 409 410 static const VMStateDescription vmstate_mos6522_timer = { 411 .name = "mos6522_timer", 412 .version_id = 0, 413 .minimum_version_id = 0, 414 .fields = (VMStateField[]) { 415 VMSTATE_UINT16(latch, MOS6522Timer), 416 VMSTATE_UINT16(counter_value, MOS6522Timer), 417 VMSTATE_INT64(load_time, MOS6522Timer), 418 VMSTATE_INT64(next_irq_time, MOS6522Timer), 419 VMSTATE_TIMER_PTR(timer, MOS6522Timer), 420 VMSTATE_END_OF_LIST() 421 } 422 }; 423 424 const VMStateDescription vmstate_mos6522 = { 425 .name = "mos6522", 426 .version_id = 0, 427 .minimum_version_id = 0, 428 .fields = (VMStateField[]) { 429 VMSTATE_UINT8(a, MOS6522State), 430 VMSTATE_UINT8(b, MOS6522State), 431 VMSTATE_UINT8(dira, MOS6522State), 432 VMSTATE_UINT8(dirb, MOS6522State), 433 VMSTATE_UINT8(sr, MOS6522State), 434 VMSTATE_UINT8(acr, MOS6522State), 435 VMSTATE_UINT8(pcr, MOS6522State), 436 VMSTATE_UINT8(ifr, MOS6522State), 437 VMSTATE_UINT8(ier, MOS6522State), 438 VMSTATE_UINT8(anh, MOS6522State), 439 VMSTATE_STRUCT_ARRAY(timers, MOS6522State, 2, 0, 440 vmstate_mos6522_timer, MOS6522Timer), 441 VMSTATE_END_OF_LIST() 442 } 443 }; 444 445 static void mos6522_reset(DeviceState *dev) 446 { 447 MOS6522State *s = MOS6522(dev); 448 449 s->b = 0; 450 s->a = 0; 451 s->dirb = 0xff; 452 s->dira = 0; 453 s->sr = 0; 454 s->acr = 0; 455 s->pcr = 0; 456 s->ifr = 0; 457 s->ier = 0; 458 /* s->ier = T1_INT | SR_INT; */ 459 s->anh = 0; 460 461 s->timers[0].frequency = s->frequency; 462 s->timers[0].latch = 0xffff; 463 set_counter(s, &s->timers[0], 0xffff); 464 timer_del(s->timers[0].timer); 465 466 s->timers[1].frequency = s->frequency; 467 s->timers[1].latch = 0xffff; 468 timer_del(s->timers[1].timer); 469 } 470 471 static void mos6522_init(Object *obj) 472 { 473 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 474 MOS6522State *s = MOS6522(obj); 475 int i; 476 477 memory_region_init_io(&s->mem, obj, &mos6522_ops, s, "mos6522", 0x10); 478 sysbus_init_mmio(sbd, &s->mem); 479 sysbus_init_irq(sbd, &s->irq); 480 481 for (i = 0; i < ARRAY_SIZE(s->timers); i++) { 482 s->timers[i].index = i; 483 } 484 485 s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer1, s); 486 s->timers[1].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer2, s); 487 } 488 489 static Property mos6522_properties[] = { 490 DEFINE_PROP_UINT64("frequency", MOS6522State, frequency, 0), 491 DEFINE_PROP_END_OF_LIST() 492 }; 493 494 static void mos6522_class_init(ObjectClass *oc, void *data) 495 { 496 DeviceClass *dc = DEVICE_CLASS(oc); 497 MOS6522DeviceClass *mdc = MOS6522_DEVICE_CLASS(oc); 498 499 dc->reset = mos6522_reset; 500 dc->vmsd = &vmstate_mos6522; 501 dc->props = mos6522_properties; 502 mdc->parent_reset = dc->reset; 503 mdc->set_sr_int = mos6522_set_sr_int; 504 mdc->portB_write = mos6522_portB_write; 505 mdc->portA_write = mos6522_portA_write; 506 mdc->update_irq = mos6522_update_irq; 507 mdc->get_timer1_counter_value = mos6522_get_counter_value; 508 mdc->get_timer2_counter_value = mos6522_get_counter_value; 509 mdc->get_timer1_load_time = mos6522_get_load_time; 510 mdc->get_timer2_load_time = mos6522_get_load_time; 511 } 512 513 static const TypeInfo mos6522_type_info = { 514 .name = TYPE_MOS6522, 515 .parent = TYPE_SYS_BUS_DEVICE, 516 .instance_size = sizeof(MOS6522State), 517 .instance_init = mos6522_init, 518 .abstract = true, 519 .class_size = sizeof(MOS6522DeviceClass), 520 .class_init = mos6522_class_init, 521 }; 522 523 static void mos6522_register_types(void) 524 { 525 type_register_static(&mos6522_type_info); 526 } 527 528 type_init(mos6522_register_types) 529