1 /* 2 * QEMU MOS6522 VIA emulation 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2018 Mark Cave-Ayland 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "hw/input/adb.h" 29 #include "hw/irq.h" 30 #include "hw/misc/mos6522.h" 31 #include "hw/qdev-properties.h" 32 #include "migration/vmstate.h" 33 #include "qemu/timer.h" 34 #include "qemu/cutils.h" 35 #include "qemu/log.h" 36 #include "qemu/module.h" 37 #include "trace.h" 38 39 /* XXX: implement all timer modes */ 40 41 static void mos6522_timer_update(MOS6522State *s, MOS6522Timer *ti, 42 int64_t current_time); 43 44 static void mos6522_update_irq(MOS6522State *s) 45 { 46 if (s->ifr & s->ier) { 47 qemu_irq_raise(s->irq); 48 } else { 49 qemu_irq_lower(s->irq); 50 } 51 } 52 53 static uint64_t get_counter_value(MOS6522State *s, MOS6522Timer *ti) 54 { 55 MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s); 56 57 if (ti->index == 0) { 58 return mdc->get_timer1_counter_value(s, ti); 59 } else { 60 return mdc->get_timer2_counter_value(s, ti); 61 } 62 } 63 64 static uint64_t get_load_time(MOS6522State *s, MOS6522Timer *ti) 65 { 66 MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s); 67 68 if (ti->index == 0) { 69 return mdc->get_timer1_load_time(s, ti); 70 } else { 71 return mdc->get_timer2_load_time(s, ti); 72 } 73 } 74 75 static unsigned int get_counter(MOS6522State *s, MOS6522Timer *ti) 76 { 77 int64_t d; 78 unsigned int counter; 79 80 d = get_counter_value(s, ti); 81 82 if (ti->index == 0) { 83 /* the timer goes down from latch to -1 (period of latch + 2) */ 84 if (d <= (ti->counter_value + 1)) { 85 counter = (ti->counter_value - d) & 0xffff; 86 } else { 87 counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); 88 counter = (ti->latch - counter) & 0xffff; 89 } 90 } else { 91 counter = (ti->counter_value - d) & 0xffff; 92 } 93 return counter; 94 } 95 96 static void set_counter(MOS6522State *s, MOS6522Timer *ti, unsigned int val) 97 { 98 trace_mos6522_set_counter(1 + ti->index, val); 99 ti->load_time = get_load_time(s, ti); 100 ti->counter_value = val; 101 mos6522_timer_update(s, ti, ti->load_time); 102 } 103 104 static int64_t get_next_irq_time(MOS6522State *s, MOS6522Timer *ti, 105 int64_t current_time) 106 { 107 int64_t d, next_time; 108 unsigned int counter; 109 110 /* current counter value */ 111 d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, 112 ti->frequency, NANOSECONDS_PER_SECOND); 113 114 /* the timer goes down from latch to -1 (period of latch + 2) */ 115 if (d <= (ti->counter_value + 1)) { 116 counter = (ti->counter_value - d) & 0xffff; 117 } else { 118 counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); 119 counter = (ti->latch - counter) & 0xffff; 120 } 121 122 /* Note: we consider the irq is raised on 0 */ 123 if (counter == 0xffff) { 124 next_time = d + ti->latch + 1; 125 } else if (counter == 0) { 126 next_time = d + ti->latch + 2; 127 } else { 128 next_time = d + counter; 129 } 130 trace_mos6522_get_next_irq_time(ti->latch, d, next_time - d); 131 next_time = muldiv64(next_time, NANOSECONDS_PER_SECOND, ti->frequency) + 132 ti->load_time; 133 if (next_time <= current_time) { 134 next_time = current_time + 1; 135 } 136 return next_time; 137 } 138 139 static void mos6522_timer_update(MOS6522State *s, MOS6522Timer *ti, 140 int64_t current_time) 141 { 142 if (!ti->timer) { 143 return; 144 } 145 if (ti->index == 0 && (s->acr & T1MODE) != T1MODE_CONT) { 146 timer_del(ti->timer); 147 } else { 148 ti->next_irq_time = get_next_irq_time(s, ti, current_time); 149 timer_mod(ti->timer, ti->next_irq_time); 150 } 151 } 152 153 static void mos6522_timer1(void *opaque) 154 { 155 MOS6522State *s = opaque; 156 MOS6522Timer *ti = &s->timers[0]; 157 158 mos6522_timer_update(s, ti, ti->next_irq_time); 159 s->ifr |= T1_INT; 160 mos6522_update_irq(s); 161 } 162 163 static void mos6522_timer2(void *opaque) 164 { 165 MOS6522State *s = opaque; 166 MOS6522Timer *ti = &s->timers[1]; 167 168 mos6522_timer_update(s, ti, ti->next_irq_time); 169 s->ifr |= T2_INT; 170 mos6522_update_irq(s); 171 } 172 173 static void mos6522_set_sr_int(MOS6522State *s) 174 { 175 trace_mos6522_set_sr_int(); 176 s->ifr |= SR_INT; 177 mos6522_update_irq(s); 178 } 179 180 static uint64_t mos6522_get_counter_value(MOS6522State *s, MOS6522Timer *ti) 181 { 182 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, 183 ti->frequency, NANOSECONDS_PER_SECOND); 184 } 185 186 static uint64_t mos6522_get_load_time(MOS6522State *s, MOS6522Timer *ti) 187 { 188 uint64_t load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 189 190 return load_time; 191 } 192 193 static void mos6522_portA_write(MOS6522State *s) 194 { 195 qemu_log_mask(LOG_UNIMP, "portA_write unimplemented\n"); 196 } 197 198 static void mos6522_portB_write(MOS6522State *s) 199 { 200 qemu_log_mask(LOG_UNIMP, "portB_write unimplemented\n"); 201 } 202 203 uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) 204 { 205 MOS6522State *s = opaque; 206 uint32_t val; 207 208 switch (addr) { 209 case VIA_REG_B: 210 val = s->b; 211 break; 212 case VIA_REG_A: 213 val = s->a; 214 break; 215 case VIA_REG_DIRB: 216 val = s->dirb; 217 break; 218 case VIA_REG_DIRA: 219 val = s->dira; 220 break; 221 case VIA_REG_T1CL: 222 val = get_counter(s, &s->timers[0]) & 0xff; 223 s->ifr &= ~T1_INT; 224 mos6522_update_irq(s); 225 break; 226 case VIA_REG_T1CH: 227 val = get_counter(s, &s->timers[0]) >> 8; 228 mos6522_update_irq(s); 229 break; 230 case VIA_REG_T1LL: 231 val = s->timers[0].latch & 0xff; 232 break; 233 case VIA_REG_T1LH: 234 /* XXX: check this */ 235 val = (s->timers[0].latch >> 8) & 0xff; 236 break; 237 case VIA_REG_T2CL: 238 val = get_counter(s, &s->timers[1]) & 0xff; 239 s->ifr &= ~T2_INT; 240 mos6522_update_irq(s); 241 break; 242 case VIA_REG_T2CH: 243 val = get_counter(s, &s->timers[1]) >> 8; 244 break; 245 case VIA_REG_SR: 246 val = s->sr; 247 s->ifr &= ~SR_INT; 248 mos6522_update_irq(s); 249 break; 250 case VIA_REG_ACR: 251 val = s->acr; 252 break; 253 case VIA_REG_PCR: 254 val = s->pcr; 255 break; 256 case VIA_REG_IFR: 257 val = s->ifr; 258 if (s->ifr & s->ier) { 259 val |= 0x80; 260 } 261 break; 262 case VIA_REG_IER: 263 val = s->ier | 0x80; 264 break; 265 default: 266 case VIA_REG_ANH: 267 val = s->anh; 268 break; 269 } 270 271 if (addr != VIA_REG_IFR || val != 0) { 272 trace_mos6522_read(addr, val); 273 } 274 275 return val; 276 } 277 278 void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) 279 { 280 MOS6522State *s = opaque; 281 MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s); 282 283 trace_mos6522_write(addr, val); 284 285 switch (addr) { 286 case VIA_REG_B: 287 s->b = (s->b & ~s->dirb) | (val & s->dirb); 288 mdc->portB_write(s); 289 break; 290 case VIA_REG_A: 291 s->a = (s->a & ~s->dira) | (val & s->dira); 292 mdc->portA_write(s); 293 break; 294 case VIA_REG_DIRB: 295 s->dirb = val; 296 break; 297 case VIA_REG_DIRA: 298 s->dira = val; 299 break; 300 case VIA_REG_T1CL: 301 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; 302 mos6522_timer_update(s, &s->timers[0], 303 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 304 break; 305 case VIA_REG_T1CH: 306 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); 307 s->ifr &= ~T1_INT; 308 set_counter(s, &s->timers[0], s->timers[0].latch); 309 break; 310 case VIA_REG_T1LL: 311 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; 312 mos6522_timer_update(s, &s->timers[0], 313 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 314 break; 315 case VIA_REG_T1LH: 316 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); 317 s->ifr &= ~T1_INT; 318 mos6522_timer_update(s, &s->timers[0], 319 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 320 break; 321 case VIA_REG_T2CL: 322 s->timers[1].latch = (s->timers[1].latch & 0xff00) | val; 323 break; 324 case VIA_REG_T2CH: 325 /* To ensure T2 generates an interrupt on zero crossing with the 326 common timer code, write the value directly from the latch to 327 the counter */ 328 s->timers[1].latch = (s->timers[1].latch & 0xff) | (val << 8); 329 s->ifr &= ~T2_INT; 330 set_counter(s, &s->timers[1], s->timers[1].latch); 331 break; 332 case VIA_REG_SR: 333 s->sr = val; 334 break; 335 case VIA_REG_ACR: 336 s->acr = val; 337 mos6522_timer_update(s, &s->timers[0], 338 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 339 break; 340 case VIA_REG_PCR: 341 s->pcr = val; 342 break; 343 case VIA_REG_IFR: 344 /* reset bits */ 345 s->ifr &= ~val; 346 mos6522_update_irq(s); 347 break; 348 case VIA_REG_IER: 349 if (val & IER_SET) { 350 /* set bits */ 351 s->ier |= val & 0x7f; 352 } else { 353 /* reset bits */ 354 s->ier &= ~val; 355 } 356 mos6522_update_irq(s); 357 break; 358 default: 359 case VIA_REG_ANH: 360 s->anh = val; 361 break; 362 } 363 } 364 365 static const MemoryRegionOps mos6522_ops = { 366 .read = mos6522_read, 367 .write = mos6522_write, 368 .endianness = DEVICE_NATIVE_ENDIAN, 369 .valid = { 370 .min_access_size = 1, 371 .max_access_size = 1, 372 }, 373 }; 374 375 static const VMStateDescription vmstate_mos6522_timer = { 376 .name = "mos6522_timer", 377 .version_id = 0, 378 .minimum_version_id = 0, 379 .fields = (VMStateField[]) { 380 VMSTATE_UINT16(latch, MOS6522Timer), 381 VMSTATE_UINT16(counter_value, MOS6522Timer), 382 VMSTATE_INT64(load_time, MOS6522Timer), 383 VMSTATE_INT64(next_irq_time, MOS6522Timer), 384 VMSTATE_TIMER_PTR(timer, MOS6522Timer), 385 VMSTATE_END_OF_LIST() 386 } 387 }; 388 389 const VMStateDescription vmstate_mos6522 = { 390 .name = "mos6522", 391 .version_id = 0, 392 .minimum_version_id = 0, 393 .fields = (VMStateField[]) { 394 VMSTATE_UINT8(a, MOS6522State), 395 VMSTATE_UINT8(b, MOS6522State), 396 VMSTATE_UINT8(dira, MOS6522State), 397 VMSTATE_UINT8(dirb, MOS6522State), 398 VMSTATE_UINT8(sr, MOS6522State), 399 VMSTATE_UINT8(acr, MOS6522State), 400 VMSTATE_UINT8(pcr, MOS6522State), 401 VMSTATE_UINT8(ifr, MOS6522State), 402 VMSTATE_UINT8(ier, MOS6522State), 403 VMSTATE_UINT8(anh, MOS6522State), 404 VMSTATE_STRUCT_ARRAY(timers, MOS6522State, 2, 0, 405 vmstate_mos6522_timer, MOS6522Timer), 406 VMSTATE_END_OF_LIST() 407 } 408 }; 409 410 static void mos6522_reset(DeviceState *dev) 411 { 412 MOS6522State *s = MOS6522(dev); 413 414 s->b = 0; 415 s->a = 0; 416 s->dirb = 0xff; 417 s->dira = 0; 418 s->sr = 0; 419 s->acr = 0; 420 s->pcr = 0; 421 s->ifr = 0; 422 s->ier = 0; 423 /* s->ier = T1_INT | SR_INT; */ 424 s->anh = 0; 425 426 s->timers[0].frequency = s->frequency; 427 s->timers[0].latch = 0xffff; 428 set_counter(s, &s->timers[0], 0xffff); 429 430 s->timers[1].frequency = s->frequency; 431 s->timers[1].latch = 0xffff; 432 } 433 434 static void mos6522_init(Object *obj) 435 { 436 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 437 MOS6522State *s = MOS6522(obj); 438 int i; 439 440 memory_region_init_io(&s->mem, obj, &mos6522_ops, s, "mos6522", 0x10); 441 sysbus_init_mmio(sbd, &s->mem); 442 sysbus_init_irq(sbd, &s->irq); 443 444 for (i = 0; i < ARRAY_SIZE(s->timers); i++) { 445 s->timers[i].index = i; 446 } 447 448 s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer1, s); 449 s->timers[1].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer2, s); 450 } 451 452 static Property mos6522_properties[] = { 453 DEFINE_PROP_UINT64("frequency", MOS6522State, frequency, 0), 454 DEFINE_PROP_END_OF_LIST() 455 }; 456 457 static void mos6522_class_init(ObjectClass *oc, void *data) 458 { 459 DeviceClass *dc = DEVICE_CLASS(oc); 460 MOS6522DeviceClass *mdc = MOS6522_DEVICE_CLASS(oc); 461 462 dc->reset = mos6522_reset; 463 dc->vmsd = &vmstate_mos6522; 464 dc->props = mos6522_properties; 465 mdc->parent_reset = dc->reset; 466 mdc->set_sr_int = mos6522_set_sr_int; 467 mdc->portB_write = mos6522_portB_write; 468 mdc->portA_write = mos6522_portA_write; 469 mdc->update_irq = mos6522_update_irq; 470 mdc->get_timer1_counter_value = mos6522_get_counter_value; 471 mdc->get_timer2_counter_value = mos6522_get_counter_value; 472 mdc->get_timer1_load_time = mos6522_get_load_time; 473 mdc->get_timer2_load_time = mos6522_get_load_time; 474 } 475 476 static const TypeInfo mos6522_type_info = { 477 .name = TYPE_MOS6522, 478 .parent = TYPE_SYS_BUS_DEVICE, 479 .instance_size = sizeof(MOS6522State), 480 .instance_init = mos6522_init, 481 .abstract = true, 482 .class_size = sizeof(MOS6522DeviceClass), 483 .class_init = mos6522_class_init, 484 }; 485 486 static void mos6522_register_types(void) 487 { 488 type_register_static(&mos6522_type_info); 489 } 490 491 type_init(mos6522_register_types) 492