xref: /openbmc/qemu/hw/misc/mips_itu.c (revision cde3c425) 
1 /*
2  * Inter-Thread Communication Unit emulation.
3  *
4  * Copyright (c) 2016 Imagination Technologies
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qemu/log.h"
23 #include "qemu/module.h"
24 #include "qapi/error.h"
25 #include "hw/core/cpu.h"
26 #include "hw/misc/mips_itu.h"
27 #include "hw/qdev-properties.h"
28 #include "target/mips/cpu.h"
29 
30 #define ITC_TAG_ADDRSPACE_SZ (ITC_ADDRESSMAP_NUM * 8)
31 /* Initialize as 4kB area to fit all 32 cells with default 128B grain.
32    Storage may be resized by the software. */
33 #define ITC_STORAGE_ADDRSPACE_SZ 0x1000
34 
35 #define ITC_FIFO_NUM_MAX 16
36 #define ITC_SEMAPH_NUM_MAX 16
37 #define ITC_AM1_NUMENTRIES_OFS 20
38 
39 #define ITC_CELL_PV_MAX_VAL 0xFFFF
40 
41 #define ITC_CELL_TAG_FIFO_DEPTH 28
42 #define ITC_CELL_TAG_FIFO_PTR 18
43 #define ITC_CELL_TAG_FIFO 17
44 #define ITC_CELL_TAG_T 16
45 #define ITC_CELL_TAG_F 1
46 #define ITC_CELL_TAG_E 0
47 
48 #define ITC_AM0_BASE_ADDRESS_MASK 0xFFFFFC00ULL
49 #define ITC_AM0_EN_MASK 0x1
50 
51 #define ITC_AM1_ADDR_MASK_MASK 0x1FC00
52 #define ITC_AM1_ENTRY_GRAIN_MASK 0x7
53 
54 typedef enum ITCView {
55     ITCVIEW_BYPASS  = 0,
56     ITCVIEW_CONTROL = 1,
57     ITCVIEW_EF_SYNC = 2,
58     ITCVIEW_EF_TRY  = 3,
59     ITCVIEW_PV_SYNC = 4,
60     ITCVIEW_PV_TRY  = 5,
61     ITCVIEW_PV_ICR0 = 15,
62 } ITCView;
63 
64 #define ITC_ICR0_CELL_NUM        16
65 #define ITC_ICR0_BLK_GRAIN       8
66 #define ITC_ICR0_BLK_GRAIN_MASK  0x7
67 #define ITC_ICR0_ERR_AXI         2
68 #define ITC_ICR0_ERR_PARITY      1
69 #define ITC_ICR0_ERR_EXEC        0
70 
71 MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu)
72 {
73     return &itu->tag_io;
74 }
75 
76 static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size)
77 {
78     MIPSITUState *tag = (MIPSITUState *)opaque;
79     uint64_t index = addr >> 3;
80 
81     if (index >= ITC_ADDRESSMAP_NUM) {
82         qemu_log_mask(LOG_GUEST_ERROR, "Read 0x%" PRIx64 "\n", addr);
83         return 0;
84     }
85 
86     return tag->ITCAddressMap[index];
87 }
88 
89 static void itc_reconfigure(MIPSITUState *tag)
90 {
91     uint64_t *am = &tag->ITCAddressMap[0];
92     MemoryRegion *mr = &tag->storage_io;
93     hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK;
94     uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
95     bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0;
96 
97     memory_region_transaction_begin();
98     if (!(size & (size - 1))) {
99         memory_region_set_size(mr, size);
100     }
101     memory_region_set_address(mr, address);
102     memory_region_set_enabled(mr, is_enabled);
103     memory_region_transaction_commit();
104 }
105 
106 static void itc_tag_write(void *opaque, hwaddr addr,
107                           uint64_t data, unsigned size)
108 {
109     MIPSITUState *tag = (MIPSITUState *)opaque;
110     uint64_t *am = &tag->ITCAddressMap[0];
111     uint64_t am_old, mask;
112     uint64_t index = addr >> 3;
113 
114     switch (index) {
115     case 0:
116         mask = ITC_AM0_BASE_ADDRESS_MASK | ITC_AM0_EN_MASK;
117         break;
118     case 1:
119         mask = ITC_AM1_ADDR_MASK_MASK | ITC_AM1_ENTRY_GRAIN_MASK;
120         break;
121     default:
122         qemu_log_mask(LOG_GUEST_ERROR, "Bad write 0x%" PRIx64 "\n", addr);
123         return;
124     }
125 
126     am_old = am[index];
127     am[index] = (data & mask) | (am_old & ~mask);
128     if (am_old != am[index]) {
129         itc_reconfigure(tag);
130     }
131 }
132 
133 static const MemoryRegionOps itc_tag_ops = {
134     .read = itc_tag_read,
135     .write = itc_tag_write,
136     .impl = {
137         .max_access_size = 8,
138     },
139     .endianness = DEVICE_NATIVE_ENDIAN,
140 };
141 
142 static inline uint32_t get_num_cells(MIPSITUState *s)
143 {
144     return s->num_fifo + s->num_semaphores;
145 }
146 
147 static inline ITCView get_itc_view(hwaddr addr)
148 {
149     return (addr >> 3) & 0xf;
150 }
151 
152 static inline int get_cell_stride_shift(const MIPSITUState *s)
153 {
154     /* Minimum interval (for EntryGain = 0) is 128 B */
155     return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);
156 }
157 
158 static inline ITCStorageCell *get_cell(MIPSITUState *s,
159                                        hwaddr addr)
160 {
161     uint32_t cell_idx = addr >> get_cell_stride_shift(s);
162     uint32_t num_cells = get_num_cells(s);
163 
164     if (cell_idx >= num_cells) {
165         cell_idx = num_cells - 1;
166     }
167 
168     return &s->cell[cell_idx];
169 }
170 
171 static void wake_blocked_threads(ITCStorageCell *c)
172 {
173     CPUState *cs;
174     CPU_FOREACH(cs) {
175         if (cs->halted && (c->blocked_threads & (1ULL << cs->cpu_index))) {
176             cpu_interrupt(cs, CPU_INTERRUPT_WAKE);
177         }
178     }
179     c->blocked_threads = 0;
180 }
181 
182 static G_NORETURN
183 void block_thread_and_exit(ITCStorageCell *c)
184 {
185     c->blocked_threads |= 1ULL << current_cpu->cpu_index;
186     current_cpu->halted = 1;
187     current_cpu->exception_index = EXCP_HLT;
188     cpu_loop_exit_restore(current_cpu, current_cpu->mem_io_pc);
189 }
190 
191 /* ITC Bypass View */
192 
193 static inline uint64_t view_bypass_read(ITCStorageCell *c)
194 {
195     if (c->tag.FIFO) {
196         return c->data[c->fifo_out];
197     } else {
198         return c->data[0];
199     }
200 }
201 
202 static inline void view_bypass_write(ITCStorageCell *c, uint64_t val)
203 {
204     if (c->tag.FIFO && (c->tag.FIFOPtr > 0)) {
205         int idx = (c->fifo_out + c->tag.FIFOPtr - 1) % ITC_CELL_DEPTH;
206         c->data[idx] = val;
207     }
208 
209     /* ignore a write to the semaphore cell */
210 }
211 
212 /* ITC Control View */
213 
214 static inline uint64_t view_control_read(ITCStorageCell *c)
215 {
216     return ((uint64_t)c->tag.FIFODepth << ITC_CELL_TAG_FIFO_DEPTH) |
217            (c->tag.FIFOPtr << ITC_CELL_TAG_FIFO_PTR) |
218            (c->tag.FIFO << ITC_CELL_TAG_FIFO) |
219            (c->tag.T << ITC_CELL_TAG_T) |
220            (c->tag.E << ITC_CELL_TAG_E) |
221            (c->tag.F << ITC_CELL_TAG_F);
222 }
223 
224 static inline void view_control_write(ITCStorageCell *c, uint64_t val)
225 {
226     c->tag.T = (val >> ITC_CELL_TAG_T) & 1;
227     c->tag.E = (val >> ITC_CELL_TAG_E) & 1;
228     c->tag.F = (val >> ITC_CELL_TAG_F) & 1;
229 
230     if (c->tag.E) {
231         c->tag.FIFOPtr = 0;
232     }
233 }
234 
235 /* ITC Empty/Full View */
236 
237 static uint64_t view_ef_common_read(ITCStorageCell *c, bool blocking)
238 {
239     uint64_t ret = 0;
240 
241     if (!c->tag.FIFO) {
242         return 0;
243     }
244 
245     c->tag.F = 0;
246 
247     if (blocking && c->tag.E) {
248         block_thread_and_exit(c);
249     }
250 
251     if (c->blocked_threads) {
252         wake_blocked_threads(c);
253     }
254 
255     if (c->tag.FIFOPtr > 0) {
256         ret = c->data[c->fifo_out];
257         c->fifo_out = (c->fifo_out + 1) % ITC_CELL_DEPTH;
258         c->tag.FIFOPtr--;
259     }
260 
261     if (c->tag.FIFOPtr == 0) {
262         c->tag.E = 1;
263     }
264 
265     return ret;
266 }
267 
268 static uint64_t view_ef_sync_read(ITCStorageCell *c)
269 {
270     return view_ef_common_read(c, true);
271 }
272 
273 static uint64_t view_ef_try_read(ITCStorageCell *c)
274 {
275     return view_ef_common_read(c, false);
276 }
277 
278 static inline void view_ef_common_write(ITCStorageCell *c, uint64_t val,
279                                         bool blocking)
280 {
281     if (!c->tag.FIFO) {
282         return;
283     }
284 
285     c->tag.E = 0;
286 
287     if (blocking && c->tag.F) {
288         block_thread_and_exit(c);
289     }
290 
291     if (c->blocked_threads) {
292         wake_blocked_threads(c);
293     }
294 
295     if (c->tag.FIFOPtr < ITC_CELL_DEPTH) {
296         int idx = (c->fifo_out + c->tag.FIFOPtr) % ITC_CELL_DEPTH;
297         c->data[idx] = val;
298         c->tag.FIFOPtr++;
299     }
300 
301     if (c->tag.FIFOPtr == ITC_CELL_DEPTH) {
302         c->tag.F = 1;
303     }
304 }
305 
306 static void view_ef_sync_write(ITCStorageCell *c, uint64_t val)
307 {
308     view_ef_common_write(c, val, true);
309 }
310 
311 static void view_ef_try_write(ITCStorageCell *c, uint64_t val)
312 {
313     view_ef_common_write(c, val, false);
314 }
315 
316 /* ITC P/V View */
317 
318 static uint64_t view_pv_common_read(ITCStorageCell *c, bool blocking)
319 {
320     uint64_t ret = c->data[0];
321 
322     if (c->tag.FIFO) {
323         return 0;
324     }
325 
326     if (c->data[0] > 0) {
327         c->data[0]--;
328     } else if (blocking) {
329         block_thread_and_exit(c);
330     }
331 
332     return ret;
333 }
334 
335 static uint64_t view_pv_sync_read(ITCStorageCell *c)
336 {
337     return view_pv_common_read(c, true);
338 }
339 
340 static uint64_t view_pv_try_read(ITCStorageCell *c)
341 {
342     return view_pv_common_read(c, false);
343 }
344 
345 static inline void view_pv_common_write(ITCStorageCell *c)
346 {
347     if (c->tag.FIFO) {
348         return;
349     }
350 
351     if (c->data[0] < ITC_CELL_PV_MAX_VAL) {
352         c->data[0]++;
353     }
354 
355     if (c->blocked_threads) {
356         wake_blocked_threads(c);
357     }
358 }
359 
360 static void view_pv_sync_write(ITCStorageCell *c)
361 {
362     view_pv_common_write(c);
363 }
364 
365 static void view_pv_try_write(ITCStorageCell *c)
366 {
367     view_pv_common_write(c);
368 }
369 
370 static void raise_exception(int excp)
371 {
372     current_cpu->exception_index = excp;
373     cpu_loop_exit(current_cpu);
374 }
375 
376 static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
377 {
378     MIPSITUState *s = (MIPSITUState *)opaque;
379     ITCStorageCell *cell = get_cell(s, addr);
380     ITCView view = get_itc_view(addr);
381     uint64_t ret = -1;
382 
383     switch (size) {
384     case 1:
385     case 2:
386         s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
387         raise_exception(EXCP_DBE);
388         return 0;
389     }
390 
391     switch (view) {
392     case ITCVIEW_BYPASS:
393         ret = view_bypass_read(cell);
394         break;
395     case ITCVIEW_CONTROL:
396         ret = view_control_read(cell);
397         break;
398     case ITCVIEW_EF_SYNC:
399         ret = view_ef_sync_read(cell);
400         break;
401     case ITCVIEW_EF_TRY:
402         ret = view_ef_try_read(cell);
403         break;
404     case ITCVIEW_PV_SYNC:
405         ret = view_pv_sync_read(cell);
406         break;
407     case ITCVIEW_PV_TRY:
408         ret = view_pv_try_read(cell);
409         break;
410     case ITCVIEW_PV_ICR0:
411         ret = s->icr0;
412         break;
413     default:
414         qemu_log_mask(LOG_GUEST_ERROR,
415                       "itc_storage_read: Bad ITC View %d\n", (int)view);
416         break;
417     }
418 
419     return ret;
420 }
421 
422 static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data,
423                               unsigned size)
424 {
425     MIPSITUState *s = (MIPSITUState *)opaque;
426     ITCStorageCell *cell = get_cell(s, addr);
427     ITCView view = get_itc_view(addr);
428 
429     switch (size) {
430     case 1:
431     case 2:
432         s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
433         raise_exception(EXCP_DBE);
434         return;
435     }
436 
437     switch (view) {
438     case ITCVIEW_BYPASS:
439         view_bypass_write(cell, data);
440         break;
441     case ITCVIEW_CONTROL:
442         view_control_write(cell, data);
443         break;
444     case ITCVIEW_EF_SYNC:
445         view_ef_sync_write(cell, data);
446         break;
447     case ITCVIEW_EF_TRY:
448         view_ef_try_write(cell, data);
449         break;
450     case ITCVIEW_PV_SYNC:
451         view_pv_sync_write(cell);
452         break;
453     case ITCVIEW_PV_TRY:
454         view_pv_try_write(cell);
455         break;
456     case ITCVIEW_PV_ICR0:
457         if (data & 0x7) {
458             /* clear ERROR bits */
459             s->icr0 &= ~(data & 0x7);
460         }
461         /* set BLK_GRAIN */
462         s->icr0 &= ~0x700;
463         s->icr0 |= data & 0x700;
464         break;
465     default:
466         qemu_log_mask(LOG_GUEST_ERROR,
467                       "itc_storage_write: Bad ITC View %d\n", (int)view);
468         break;
469     }
470 
471 }
472 
473 static const MemoryRegionOps itc_storage_ops = {
474     .read = itc_storage_read,
475     .write = itc_storage_write,
476     .endianness = DEVICE_NATIVE_ENDIAN,
477 };
478 
479 static void itc_reset_cells(MIPSITUState *s)
480 {
481     int i;
482 
483     memset(s->cell, 0, get_num_cells(s) * sizeof(s->cell[0]));
484 
485     for (i = 0; i < s->num_fifo; i++) {
486         s->cell[i].tag.E = 1;
487         s->cell[i].tag.FIFO = 1;
488         s->cell[i].tag.FIFODepth = ITC_CELL_DEPTH_SHIFT;
489     }
490 }
491 
492 static void mips_itu_init(Object *obj)
493 {
494     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
495     MIPSITUState *s = MIPS_ITU(obj);
496 
497     memory_region_init_io(&s->storage_io, OBJECT(s), &itc_storage_ops, s,
498                           "mips-itc-storage", ITC_STORAGE_ADDRSPACE_SZ);
499     sysbus_init_mmio(sbd, &s->storage_io);
500 
501     memory_region_init_io(&s->tag_io, OBJECT(s), &itc_tag_ops, s,
502                           "mips-itc-tag", ITC_TAG_ADDRSPACE_SZ);
503 }
504 
505 static void mips_itu_realize(DeviceState *dev, Error **errp)
506 {
507     MIPSITUState *s = MIPS_ITU(dev);
508 
509     if (s->num_fifo > ITC_FIFO_NUM_MAX) {
510         error_setg(errp, "Exceed maximum number of FIFO cells: %d",
511                    s->num_fifo);
512         return;
513     }
514     if (s->num_semaphores > ITC_SEMAPH_NUM_MAX) {
515         error_setg(errp, "Exceed maximum number of Semaphore cells: %d",
516                    s->num_semaphores);
517         return;
518     }
519 
520     s->cell = g_new(ITCStorageCell, get_num_cells(s));
521 }
522 
523 static void mips_itu_reset(DeviceState *dev)
524 {
525     MIPSITUState *s = MIPS_ITU(dev);
526 
527     s->ITCAddressMap[0] = 0;
528     s->ITCAddressMap[1] =
529             ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) |
530             (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS);
531     itc_reconfigure(s);
532 
533     itc_reset_cells(s);
534 }
535 
536 static Property mips_itu_properties[] = {
537     DEFINE_PROP_UINT32("num-fifo", MIPSITUState, num_fifo,
538                       ITC_FIFO_NUM_MAX),
539     DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores,
540                       ITC_SEMAPH_NUM_MAX),
541     DEFINE_PROP_END_OF_LIST(),
542 };
543 
544 static void mips_itu_class_init(ObjectClass *klass, void *data)
545 {
546     DeviceClass *dc = DEVICE_CLASS(klass);
547 
548     device_class_set_props(dc, mips_itu_properties);
549     dc->realize = mips_itu_realize;
550     device_class_set_legacy_reset(dc, mips_itu_reset);
551 }
552 
553 static const TypeInfo mips_itu_info = {
554     .name          = TYPE_MIPS_ITU,
555     .parent        = TYPE_SYS_BUS_DEVICE,
556     .instance_size = sizeof(MIPSITUState),
557     .instance_init = mips_itu_init,
558     .class_init    = mips_itu_class_init,
559 };
560 
561 static void mips_itu_register_types(void)
562 {
563     type_register_static(&mips_itu_info);
564 }
565 
566 type_init(mips_itu_register_types)
567