1 /* 2 * Cluster Power Controller emulation 3 * 4 * Copyright (c) 2016 Imagination Technologies 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "cpu.h" 23 #include "qemu/log.h" 24 #include "hw/sysbus.h" 25 26 #include "hw/misc/mips_cpc.h" 27 28 static inline uint64_t cpc_vp_run_mask(MIPSCPCState *cpc) 29 { 30 return (1ULL << cpc->num_vp) - 1; 31 } 32 33 static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run) 34 { 35 CPUState *cs = first_cpu; 36 37 CPU_FOREACH(cs) { 38 uint64_t i = 1ULL << cs->cpu_index; 39 if (i & vp_run & ~cpc->vp_running) { 40 cpu_reset(cs); 41 cpc->vp_running |= i; 42 } 43 } 44 } 45 46 static void cpc_stop_vp(MIPSCPCState *cpc, uint64_t vp_stop) 47 { 48 CPUState *cs = first_cpu; 49 50 CPU_FOREACH(cs) { 51 uint64_t i = 1ULL << cs->cpu_index; 52 if (i & vp_stop & cpc->vp_running) { 53 cpu_interrupt(cs, CPU_INTERRUPT_HALT); 54 cpc->vp_running &= ~i; 55 } 56 } 57 } 58 59 static void cpc_write(void *opaque, hwaddr offset, uint64_t data, 60 unsigned size) 61 { 62 MIPSCPCState *s = opaque; 63 64 switch (offset) { 65 case CPC_CL_BASE_OFS + CPC_VP_RUN_OFS: 66 case CPC_CO_BASE_OFS + CPC_VP_RUN_OFS: 67 cpc_run_vp(s, data & cpc_vp_run_mask(s)); 68 break; 69 case CPC_CL_BASE_OFS + CPC_VP_STOP_OFS: 70 case CPC_CO_BASE_OFS + CPC_VP_STOP_OFS: 71 cpc_stop_vp(s, data & cpc_vp_run_mask(s)); 72 break; 73 default: 74 qemu_log_mask(LOG_UNIMP, 75 "%s: Bad offset 0x%x\n", __func__, (int)offset); 76 break; 77 } 78 79 return; 80 } 81 82 static uint64_t cpc_read(void *opaque, hwaddr offset, unsigned size) 83 { 84 MIPSCPCState *s = opaque; 85 86 switch (offset) { 87 case CPC_CL_BASE_OFS + CPC_VP_RUNNING_OFS: 88 case CPC_CO_BASE_OFS + CPC_VP_RUNNING_OFS: 89 return s->vp_running; 90 default: 91 qemu_log_mask(LOG_UNIMP, 92 "%s: Bad offset 0x%x\n", __func__, (int)offset); 93 return 0; 94 } 95 } 96 97 static const MemoryRegionOps cpc_ops = { 98 .read = cpc_read, 99 .write = cpc_write, 100 .endianness = DEVICE_NATIVE_ENDIAN, 101 .impl = { 102 .max_access_size = 8, 103 }, 104 }; 105 106 static void mips_cpc_init(Object *obj) 107 { 108 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 109 MIPSCPCState *s = MIPS_CPC(obj); 110 111 memory_region_init_io(&s->mr, OBJECT(s), &cpc_ops, s, "mips-cpc", 112 CPC_ADDRSPACE_SZ); 113 sysbus_init_mmio(sbd, &s->mr); 114 } 115 116 static void mips_cpc_realize(DeviceState *dev, Error **errp) 117 { 118 MIPSCPCState *s = MIPS_CPC(dev); 119 120 if (s->vp_start_running > cpc_vp_run_mask(s)) { 121 error_setg(errp, 122 "incorrect vp_start_running 0x%" PRIx64 " for num_vp = %d", 123 s->vp_running, s->num_vp); 124 return; 125 } 126 } 127 128 static void mips_cpc_reset(DeviceState *dev) 129 { 130 MIPSCPCState *s = MIPS_CPC(dev); 131 132 /* Reflect the fact that all VPs are halted on reset */ 133 s->vp_running = 0; 134 135 /* Put selected VPs into run state */ 136 cpc_run_vp(s, s->vp_start_running); 137 } 138 139 static const VMStateDescription vmstate_mips_cpc = { 140 .name = "mips-cpc", 141 .version_id = 0, 142 .minimum_version_id = 0, 143 .fields = (VMStateField[]) { 144 VMSTATE_UINT64(vp_running, MIPSCPCState), 145 VMSTATE_END_OF_LIST() 146 }, 147 }; 148 149 static Property mips_cpc_properties[] = { 150 DEFINE_PROP_UINT32("num-vp", MIPSCPCState, num_vp, 0x1), 151 DEFINE_PROP_UINT64("vp-start-running", MIPSCPCState, vp_start_running, 0x1), 152 DEFINE_PROP_END_OF_LIST(), 153 }; 154 155 static void mips_cpc_class_init(ObjectClass *klass, void *data) 156 { 157 DeviceClass *dc = DEVICE_CLASS(klass); 158 159 dc->realize = mips_cpc_realize; 160 dc->reset = mips_cpc_reset; 161 dc->vmsd = &vmstate_mips_cpc; 162 dc->props = mips_cpc_properties; 163 } 164 165 static const TypeInfo mips_cpc_info = { 166 .name = TYPE_MIPS_CPC, 167 .parent = TYPE_SYS_BUS_DEVICE, 168 .instance_size = sizeof(MIPSCPCState), 169 .instance_init = mips_cpc_init, 170 .class_init = mips_cpc_class_init, 171 }; 172 173 static void mips_cpc_register_types(void) 174 { 175 type_register_static(&mips_cpc_info); 176 } 177 178 type_init(mips_cpc_register_types) 179