1 /* 2 * Cluster Power Controller emulation 3 * 4 * Copyright (c) 2016 Imagination Technologies 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "cpu.h" 23 #include "qemu/log.h" 24 #include "qemu/module.h" 25 #include "hw/sysbus.h" 26 27 #include "hw/misc/mips_cpc.h" 28 29 static inline uint64_t cpc_vp_run_mask(MIPSCPCState *cpc) 30 { 31 return (1ULL << cpc->num_vp) - 1; 32 } 33 34 static void mips_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data) 35 { 36 MIPSCPCState *cpc = (MIPSCPCState *) data.host_ptr; 37 38 cpu_reset(cs); 39 cpc->vp_running |= 1ULL << cs->cpu_index; 40 } 41 42 static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run) 43 { 44 CPUState *cs = first_cpu; 45 46 CPU_FOREACH(cs) { 47 uint64_t i = 1ULL << cs->cpu_index; 48 if (i & vp_run & ~cpc->vp_running) { 49 /* 50 * To avoid racing with a CPU we are just kicking off. 51 * We do the final bit of preparation for the work in 52 * the target CPUs context. 53 */ 54 async_safe_run_on_cpu(cs, mips_cpu_reset_async_work, 55 RUN_ON_CPU_HOST_PTR(cpc)); 56 } 57 } 58 } 59 60 static void cpc_stop_vp(MIPSCPCState *cpc, uint64_t vp_stop) 61 { 62 CPUState *cs = first_cpu; 63 64 CPU_FOREACH(cs) { 65 uint64_t i = 1ULL << cs->cpu_index; 66 if (i & vp_stop & cpc->vp_running) { 67 cpu_interrupt(cs, CPU_INTERRUPT_HALT); 68 cpc->vp_running &= ~i; 69 } 70 } 71 } 72 73 static void cpc_write(void *opaque, hwaddr offset, uint64_t data, 74 unsigned size) 75 { 76 MIPSCPCState *s = opaque; 77 78 switch (offset) { 79 case CPC_CL_BASE_OFS + CPC_VP_RUN_OFS: 80 case CPC_CO_BASE_OFS + CPC_VP_RUN_OFS: 81 cpc_run_vp(s, data & cpc_vp_run_mask(s)); 82 break; 83 case CPC_CL_BASE_OFS + CPC_VP_STOP_OFS: 84 case CPC_CO_BASE_OFS + CPC_VP_STOP_OFS: 85 cpc_stop_vp(s, data & cpc_vp_run_mask(s)); 86 break; 87 default: 88 qemu_log_mask(LOG_UNIMP, 89 "%s: Bad offset 0x%x\n", __func__, (int)offset); 90 break; 91 } 92 93 return; 94 } 95 96 static uint64_t cpc_read(void *opaque, hwaddr offset, unsigned size) 97 { 98 MIPSCPCState *s = opaque; 99 100 switch (offset) { 101 case CPC_CL_BASE_OFS + CPC_VP_RUNNING_OFS: 102 case CPC_CO_BASE_OFS + CPC_VP_RUNNING_OFS: 103 return s->vp_running; 104 default: 105 qemu_log_mask(LOG_UNIMP, 106 "%s: Bad offset 0x%x\n", __func__, (int)offset); 107 return 0; 108 } 109 } 110 111 static const MemoryRegionOps cpc_ops = { 112 .read = cpc_read, 113 .write = cpc_write, 114 .endianness = DEVICE_NATIVE_ENDIAN, 115 .impl = { 116 .max_access_size = 8, 117 }, 118 }; 119 120 static void mips_cpc_init(Object *obj) 121 { 122 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 123 MIPSCPCState *s = MIPS_CPC(obj); 124 125 memory_region_init_io(&s->mr, OBJECT(s), &cpc_ops, s, "mips-cpc", 126 CPC_ADDRSPACE_SZ); 127 sysbus_init_mmio(sbd, &s->mr); 128 } 129 130 static void mips_cpc_realize(DeviceState *dev, Error **errp) 131 { 132 MIPSCPCState *s = MIPS_CPC(dev); 133 134 if (s->vp_start_running > cpc_vp_run_mask(s)) { 135 error_setg(errp, 136 "incorrect vp_start_running 0x%" PRIx64 " for num_vp = %d", 137 s->vp_running, s->num_vp); 138 return; 139 } 140 } 141 142 static void mips_cpc_reset(DeviceState *dev) 143 { 144 MIPSCPCState *s = MIPS_CPC(dev); 145 146 /* Reflect the fact that all VPs are halted on reset */ 147 s->vp_running = 0; 148 149 /* Put selected VPs into run state */ 150 cpc_run_vp(s, s->vp_start_running); 151 } 152 153 static const VMStateDescription vmstate_mips_cpc = { 154 .name = "mips-cpc", 155 .version_id = 0, 156 .minimum_version_id = 0, 157 .fields = (VMStateField[]) { 158 VMSTATE_UINT64(vp_running, MIPSCPCState), 159 VMSTATE_END_OF_LIST() 160 }, 161 }; 162 163 static Property mips_cpc_properties[] = { 164 DEFINE_PROP_UINT32("num-vp", MIPSCPCState, num_vp, 0x1), 165 DEFINE_PROP_UINT64("vp-start-running", MIPSCPCState, vp_start_running, 0x1), 166 DEFINE_PROP_END_OF_LIST(), 167 }; 168 169 static void mips_cpc_class_init(ObjectClass *klass, void *data) 170 { 171 DeviceClass *dc = DEVICE_CLASS(klass); 172 173 dc->realize = mips_cpc_realize; 174 dc->reset = mips_cpc_reset; 175 dc->vmsd = &vmstate_mips_cpc; 176 dc->props = mips_cpc_properties; 177 } 178 179 static const TypeInfo mips_cpc_info = { 180 .name = TYPE_MIPS_CPC, 181 .parent = TYPE_SYS_BUS_DEVICE, 182 .instance_size = sizeof(MIPSCPCState), 183 .instance_init = mips_cpc_init, 184 .class_init = mips_cpc_class_init, 185 }; 186 187 static void mips_cpc_register_types(void) 188 { 189 type_register_static(&mips_cpc_info); 190 } 191 192 type_init(mips_cpc_register_types) 193