1 /* 2 * Microchip PolarFire SoC SYSREG module emulation 3 * 4 * Copyright (c) 2020 Wind River Systems, Inc. 5 * 6 * Author: 7 * Bin Meng <bin.meng@windriver.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 or 12 * (at your option) version 3 of the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qemu/bitops.h" 25 #include "qemu/log.h" 26 #include "qapi/error.h" 27 #include "hw/sysbus.h" 28 #include "hw/misc/mchp_pfsoc_sysreg.h" 29 30 #define ENVM_CR 0xb8 31 32 static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset, 33 unsigned size) 34 { 35 uint32_t val = 0; 36 37 switch (offset) { 38 case ENVM_CR: 39 /* Indicate the eNVM is running at the configured divider rate */ 40 val = BIT(6); 41 break; 42 default: 43 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " 44 "(size %d, offset 0x%" HWADDR_PRIx ")\n", 45 __func__, size, offset); 46 break; 47 } 48 49 return val; 50 } 51 52 static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset, 53 uint64_t value, unsigned size) 54 { 55 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " 56 "(size %d, value 0x%" PRIx64 57 ", offset 0x%" HWADDR_PRIx ")\n", 58 __func__, size, value, offset); 59 } 60 61 static const MemoryRegionOps mchp_pfsoc_sysreg_ops = { 62 .read = mchp_pfsoc_sysreg_read, 63 .write = mchp_pfsoc_sysreg_write, 64 .endianness = DEVICE_LITTLE_ENDIAN, 65 }; 66 67 static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp) 68 { 69 MchpPfSoCSysregState *s = MCHP_PFSOC_SYSREG(dev); 70 71 memory_region_init_io(&s->sysreg, OBJECT(dev), 72 &mchp_pfsoc_sysreg_ops, s, 73 "mchp.pfsoc.sysreg", 74 MCHP_PFSOC_SYSREG_REG_SIZE); 75 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg); 76 } 77 78 static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, void *data) 79 { 80 DeviceClass *dc = DEVICE_CLASS(klass); 81 82 dc->desc = "Microchip PolarFire SoC SYSREG module"; 83 dc->realize = mchp_pfsoc_sysreg_realize; 84 } 85 86 static const TypeInfo mchp_pfsoc_sysreg_info = { 87 .name = TYPE_MCHP_PFSOC_SYSREG, 88 .parent = TYPE_SYS_BUS_DEVICE, 89 .instance_size = sizeof(MchpPfSoCSysregState), 90 .class_init = mchp_pfsoc_sysreg_class_init, 91 }; 92 93 static void mchp_pfsoc_sysreg_register_types(void) 94 { 95 type_register_static(&mchp_pfsoc_sysreg_info); 96 } 97 98 type_init(mchp_pfsoc_sysreg_register_types) 99