1 /* 2 * Microchip PolarFire SoC SYSREG module emulation 3 * 4 * Copyright (c) 2020 Wind River Systems, Inc. 5 * 6 * Author: 7 * Bin Meng <bin.meng@windriver.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 or 12 * (at your option) version 3 of the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qemu/bitops.h" 25 #include "qemu/log.h" 26 #include "qapi/error.h" 27 #include "hw/hw.h" 28 #include "hw/sysbus.h" 29 #include "hw/misc/mchp_pfsoc_sysreg.h" 30 31 #define ENVM_CR 0xb8 32 33 static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset, 34 unsigned size) 35 { 36 uint32_t val = 0; 37 38 switch (offset) { 39 case ENVM_CR: 40 /* Indicate the eNVM is running at the configured divider rate */ 41 val = BIT(6); 42 break; 43 default: 44 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " 45 "(size %d, offset 0x%" HWADDR_PRIx ")\n", 46 __func__, size, offset); 47 break; 48 } 49 50 return val; 51 } 52 53 static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset, 54 uint64_t value, unsigned size) 55 { 56 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " 57 "(size %d, value 0x%" PRIx64 58 ", offset 0x%" HWADDR_PRIx ")\n", 59 __func__, size, value, offset); 60 } 61 62 static const MemoryRegionOps mchp_pfsoc_sysreg_ops = { 63 .read = mchp_pfsoc_sysreg_read, 64 .write = mchp_pfsoc_sysreg_write, 65 .endianness = DEVICE_LITTLE_ENDIAN, 66 }; 67 68 static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp) 69 { 70 MchpPfSoCSysregState *s = MCHP_PFSOC_SYSREG(dev); 71 72 memory_region_init_io(&s->sysreg, OBJECT(dev), 73 &mchp_pfsoc_sysreg_ops, s, 74 "mchp.pfsoc.sysreg", 75 MCHP_PFSOC_SYSREG_REG_SIZE); 76 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg); 77 } 78 79 static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, void *data) 80 { 81 DeviceClass *dc = DEVICE_CLASS(klass); 82 83 dc->desc = "Microchip PolarFire SoC SYSREG module"; 84 dc->realize = mchp_pfsoc_sysreg_realize; 85 } 86 87 static const TypeInfo mchp_pfsoc_sysreg_info = { 88 .name = TYPE_MCHP_PFSOC_SYSREG, 89 .parent = TYPE_SYS_BUS_DEVICE, 90 .instance_size = sizeof(MchpPfSoCSysregState), 91 .class_init = mchp_pfsoc_sysreg_class_init, 92 }; 93 94 static void mchp_pfsoc_sysreg_register_types(void) 95 { 96 type_register_static(&mchp_pfsoc_sysreg_info); 97 } 98 99 type_init(mchp_pfsoc_sysreg_register_types) 100