1 /*
2 * Microchip PolarFire SoC IOSCB module emulation
3 *
4 * Copyright (c) 2020 Wind River Systems, Inc.
5 *
6 * Author:
7 * Bin Meng <bin.meng@windriver.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 or
12 * (at your option) version 3 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qemu/bitops.h"
25 #include "qemu/log.h"
26 #include "qapi/error.h"
27 #include "hw/irq.h"
28 #include "hw/sysbus.h"
29 #include "hw/misc/mchp_pfsoc_ioscb.h"
30
31 /*
32 * The whole IOSCB module registers map into the system address at 0x3000_0000,
33 * named as "System Port 0 (AXI-D0)".
34 */
35 #define IOSCB_WHOLE_REG_SIZE 0x10000000
36 #define IOSCB_SUBMOD_REG_SIZE 0x1000
37 #define IOSCB_CCC_REG_SIZE 0x2000000
38 #define IOSCB_CTRL_REG_SIZE 0x800
39 #define IOSCB_QSPIXIP_REG_SIZE 0x200
40
41
42 /*
43 * There are many sub-modules in the IOSCB module.
44 * See Microchip PolarFire SoC documentation (Register_Map.zip),
45 * Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm
46 *
47 * The following are sub-modules offsets that are of concern.
48 */
49 #define IOSCB_LANE01_BASE 0x06500000
50 #define IOSCB_LANE23_BASE 0x06510000
51 #define IOSCB_CTRL_BASE 0x07020000
52 #define IOSCB_QSPIXIP_BASE 0x07020100
53 #define IOSCB_MAILBOX_BASE 0x07020800
54 #define IOSCB_CFG_BASE 0x07080000
55 #define IOSCB_CCC_BASE 0x08000000
56 #define IOSCB_PLL_MSS_BASE 0x0E001000
57 #define IOSCB_CFM_MSS_BASE 0x0E002000
58 #define IOSCB_PLL_DDR_BASE 0x0E010000
59 #define IOSCB_BC_DDR_BASE 0x0E020000
60 #define IOSCB_IO_CALIB_DDR_BASE 0x0E040000
61 #define IOSCB_PLL_SGMII_BASE 0x0E080000
62 #define IOSCB_DLL_SGMII_BASE 0x0E100000
63 #define IOSCB_CFM_SGMII_BASE 0x0E200000
64 #define IOSCB_BC_SGMII_BASE 0x0E400000
65 #define IOSCB_IO_CALIB_SGMII_BASE 0x0E800000
66
mchp_pfsoc_dummy_read(void * opaque,hwaddr offset,unsigned size)67 static uint64_t mchp_pfsoc_dummy_read(void *opaque, hwaddr offset,
68 unsigned size)
69 {
70 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
71 "(size %d, offset 0x%" HWADDR_PRIx ")\n",
72 __func__, size, offset);
73
74 return 0;
75 }
76
mchp_pfsoc_dummy_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)77 static void mchp_pfsoc_dummy_write(void *opaque, hwaddr offset,
78 uint64_t value, unsigned size)
79 {
80 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
81 "(size %d, value 0x%" PRIx64
82 ", offset 0x%" HWADDR_PRIx ")\n",
83 __func__, size, value, offset);
84 }
85
86 static const MemoryRegionOps mchp_pfsoc_dummy_ops = {
87 .read = mchp_pfsoc_dummy_read,
88 .write = mchp_pfsoc_dummy_write,
89 .endianness = DEVICE_LITTLE_ENDIAN,
90 };
91
92 /* All PLL modules in IOSCB have the same register layout */
93
94 #define PLL_CTRL 0x04
95
mchp_pfsoc_pll_read(void * opaque,hwaddr offset,unsigned size)96 static uint64_t mchp_pfsoc_pll_read(void *opaque, hwaddr offset,
97 unsigned size)
98 {
99 uint32_t val = 0;
100
101 switch (offset) {
102 case PLL_CTRL:
103 /* PLL is locked */
104 val = BIT(25);
105 break;
106 default:
107 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
108 "(size %d, offset 0x%" HWADDR_PRIx ")\n",
109 __func__, size, offset);
110 break;
111 }
112
113 return val;
114 }
115
116 static const MemoryRegionOps mchp_pfsoc_pll_ops = {
117 .read = mchp_pfsoc_pll_read,
118 .write = mchp_pfsoc_dummy_write,
119 .endianness = DEVICE_LITTLE_ENDIAN,
120 };
121
122 /* IO_CALIB_DDR submodule */
123
124 #define IO_CALIB_DDR_IOC_REG1 0x08
125
mchp_pfsoc_io_calib_ddr_read(void * opaque,hwaddr offset,unsigned size)126 static uint64_t mchp_pfsoc_io_calib_ddr_read(void *opaque, hwaddr offset,
127 unsigned size)
128 {
129 uint32_t val = 0;
130
131 switch (offset) {
132 case IO_CALIB_DDR_IOC_REG1:
133 /* calibration completed */
134 val = BIT(2);
135 break;
136 default:
137 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
138 "(size %d, offset 0x%" HWADDR_PRIx ")\n",
139 __func__, size, offset);
140 break;
141 }
142
143 return val;
144 }
145
146 static const MemoryRegionOps mchp_pfsoc_io_calib_ddr_ops = {
147 .read = mchp_pfsoc_io_calib_ddr_read,
148 .write = mchp_pfsoc_dummy_write,
149 .endianness = DEVICE_LITTLE_ENDIAN,
150 };
151
152 #define SERVICES_CR 0x50
153 #define SERVICES_SR 0x54
154 #define SERVICES_STATUS_SHIFT 16
155
mchp_pfsoc_ctrl_read(void * opaque,hwaddr offset,unsigned size)156 static uint64_t mchp_pfsoc_ctrl_read(void *opaque, hwaddr offset,
157 unsigned size)
158 {
159 uint32_t val = 0;
160
161 switch (offset) {
162 case SERVICES_SR:
163 /*
164 * Although some services have no error codes, most do. All services
165 * that do implement errors, begin their error codes at 1. Treat all
166 * service requests as failures & return 1.
167 * See the "PolarFire® FPGA and PolarFire SoC FPGA System Services"
168 * user guide for more information on service error codes.
169 */
170 val = 1u << SERVICES_STATUS_SHIFT;
171 break;
172 default:
173 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
174 "(size %d, offset 0x%" HWADDR_PRIx ")\n",
175 __func__, size, offset);
176 }
177
178 return val;
179 }
180
mchp_pfsoc_ctrl_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)181 static void mchp_pfsoc_ctrl_write(void *opaque, hwaddr offset,
182 uint64_t value, unsigned size)
183 {
184 MchpPfSoCIoscbState *s = opaque;
185
186 switch (offset) {
187 case SERVICES_CR:
188 qemu_irq_raise(s->irq);
189 break;
190 default:
191 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
192 "(size %d, value 0x%" PRIx64
193 ", offset 0x%" HWADDR_PRIx ")\n",
194 __func__, size, value, offset);
195 }
196 }
197
198 static const MemoryRegionOps mchp_pfsoc_ctrl_ops = {
199 .read = mchp_pfsoc_ctrl_read,
200 .write = mchp_pfsoc_ctrl_write,
201 .endianness = DEVICE_LITTLE_ENDIAN,
202 };
203
mchp_pfsoc_ioscb_realize(DeviceState * dev,Error ** errp)204 static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
205 {
206 MchpPfSoCIoscbState *s = MCHP_PFSOC_IOSCB(dev);
207 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
208
209 memory_region_init(&s->container, OBJECT(s),
210 "mchp.pfsoc.ioscb", IOSCB_WHOLE_REG_SIZE);
211 sysbus_init_mmio(sbd, &s->container);
212
213 /* add subregions for all sub-modules in IOSCB */
214
215 memory_region_init_io(&s->lane01, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
216 "mchp.pfsoc.ioscb.lane01", IOSCB_SUBMOD_REG_SIZE);
217 memory_region_add_subregion(&s->container, IOSCB_LANE01_BASE, &s->lane01);
218
219 memory_region_init_io(&s->lane23, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
220 "mchp.pfsoc.ioscb.lane23", IOSCB_SUBMOD_REG_SIZE);
221 memory_region_add_subregion(&s->container, IOSCB_LANE23_BASE, &s->lane23);
222
223 memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_ctrl_ops, s,
224 "mchp.pfsoc.ioscb.ctrl", IOSCB_CTRL_REG_SIZE);
225 memory_region_add_subregion(&s->container, IOSCB_CTRL_BASE, &s->ctrl);
226
227 memory_region_init_io(&s->qspixip, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
228 "mchp.pfsoc.ioscb.qspixip", IOSCB_QSPIXIP_REG_SIZE);
229 memory_region_add_subregion(&s->container, IOSCB_QSPIXIP_BASE, &s->qspixip);
230
231 memory_region_init_io(&s->mailbox, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
232 "mchp.pfsoc.ioscb.mailbox", IOSCB_SUBMOD_REG_SIZE);
233 memory_region_add_subregion(&s->container, IOSCB_MAILBOX_BASE, &s->mailbox);
234
235 memory_region_init_io(&s->cfg, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
236 "mchp.pfsoc.ioscb.cfg", IOSCB_SUBMOD_REG_SIZE);
237 memory_region_add_subregion(&s->container, IOSCB_CFG_BASE, &s->cfg);
238
239 memory_region_init_io(&s->ccc, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
240 "mchp.pfsoc.ioscb.ccc", IOSCB_CCC_REG_SIZE);
241 memory_region_add_subregion(&s->container, IOSCB_CCC_BASE, &s->ccc);
242
243 memory_region_init_io(&s->pll_mss, OBJECT(s), &mchp_pfsoc_pll_ops, s,
244 "mchp.pfsoc.ioscb.pll_mss", IOSCB_SUBMOD_REG_SIZE);
245 memory_region_add_subregion(&s->container, IOSCB_PLL_MSS_BASE, &s->pll_mss);
246
247 memory_region_init_io(&s->cfm_mss, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
248 "mchp.pfsoc.ioscb.cfm_mss", IOSCB_SUBMOD_REG_SIZE);
249 memory_region_add_subregion(&s->container, IOSCB_CFM_MSS_BASE, &s->cfm_mss);
250
251 memory_region_init_io(&s->pll_ddr, OBJECT(s), &mchp_pfsoc_pll_ops, s,
252 "mchp.pfsoc.ioscb.pll_ddr", IOSCB_SUBMOD_REG_SIZE);
253 memory_region_add_subregion(&s->container, IOSCB_PLL_DDR_BASE, &s->pll_ddr);
254
255 memory_region_init_io(&s->bc_ddr, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
256 "mchp.pfsoc.ioscb.bc_ddr", IOSCB_SUBMOD_REG_SIZE);
257 memory_region_add_subregion(&s->container, IOSCB_BC_DDR_BASE, &s->bc_ddr);
258
259 memory_region_init_io(&s->io_calib_ddr, OBJECT(s),
260 &mchp_pfsoc_io_calib_ddr_ops, s,
261 "mchp.pfsoc.ioscb.io_calib_ddr",
262 IOSCB_SUBMOD_REG_SIZE);
263 memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_DDR_BASE,
264 &s->io_calib_ddr);
265
266 memory_region_init_io(&s->pll_sgmii, OBJECT(s), &mchp_pfsoc_pll_ops, s,
267 "mchp.pfsoc.ioscb.pll_sgmii", IOSCB_SUBMOD_REG_SIZE);
268 memory_region_add_subregion(&s->container, IOSCB_PLL_SGMII_BASE,
269 &s->pll_sgmii);
270
271 memory_region_init_io(&s->dll_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
272 "mchp.pfsoc.ioscb.dll_sgmii", IOSCB_SUBMOD_REG_SIZE);
273 memory_region_add_subregion(&s->container, IOSCB_DLL_SGMII_BASE,
274 &s->dll_sgmii);
275
276 memory_region_init_io(&s->cfm_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
277 "mchp.pfsoc.ioscb.cfm_sgmii", IOSCB_SUBMOD_REG_SIZE);
278 memory_region_add_subregion(&s->container, IOSCB_CFM_SGMII_BASE,
279 &s->cfm_sgmii);
280
281 memory_region_init_io(&s->bc_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
282 "mchp.pfsoc.ioscb.bc_sgmii", IOSCB_SUBMOD_REG_SIZE);
283 memory_region_add_subregion(&s->container, IOSCB_BC_SGMII_BASE,
284 &s->bc_sgmii);
285
286 memory_region_init_io(&s->io_calib_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops,
287 s, "mchp.pfsoc.ioscb.io_calib_sgmii",
288 IOSCB_SUBMOD_REG_SIZE);
289 memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_SGMII_BASE,
290 &s->io_calib_sgmii);
291
292 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
293 }
294
mchp_pfsoc_ioscb_class_init(ObjectClass * klass,void * data)295 static void mchp_pfsoc_ioscb_class_init(ObjectClass *klass, void *data)
296 {
297 DeviceClass *dc = DEVICE_CLASS(klass);
298
299 dc->desc = "Microchip PolarFire SoC IOSCB modules";
300 dc->realize = mchp_pfsoc_ioscb_realize;
301 }
302
303 static const TypeInfo mchp_pfsoc_ioscb_info = {
304 .name = TYPE_MCHP_PFSOC_IOSCB,
305 .parent = TYPE_SYS_BUS_DEVICE,
306 .instance_size = sizeof(MchpPfSoCIoscbState),
307 .class_init = mchp_pfsoc_ioscb_class_init,
308 };
309
mchp_pfsoc_ioscb_register_types(void)310 static void mchp_pfsoc_ioscb_register_types(void)
311 {
312 type_register_static(&mchp_pfsoc_ioscb_info);
313 }
314
315 type_init(mchp_pfsoc_ioscb_register_types)
316