1 /* 2 * MAX78000 Global Control Registers 3 * 4 * Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/log.h" 11 #include "trace.h" 12 #include "hw/irq.h" 13 #include "system/runstate.h" 14 #include "migration/vmstate.h" 15 #include "hw/qdev-properties.h" 16 #include "hw/char/max78000_uart.h" 17 #include "hw/misc/max78000_trng.h" 18 #include "hw/misc/max78000_gcr.h" 19 20 21 static void max78000_gcr_reset_hold(Object *obj, ResetType type) 22 { 23 DeviceState *dev = DEVICE(obj); 24 Max78000GcrState *s = MAX78000_GCR(dev); 25 s->sysctrl = 0x21002; 26 s->rst0 = 0; 27 /* All clocks are always ready */ 28 s->clkctrl = 0x3e140008; 29 s->pm = 0x3f000; 30 s->pclkdiv = 0; 31 s->pclkdis0 = 0xffffffff; 32 s->memctrl = 0x5; 33 s->memz = 0; 34 s->sysst = 0; 35 s->rst1 = 0; 36 s->pckdis1 = 0xffffffff; 37 s->eventen = 0; 38 s->revision = 0xa1; 39 s->sysie = 0; 40 s->eccerr = 0; 41 s->ecced = 0; 42 s->eccie = 0; 43 s->eccaddr = 0; 44 } 45 46 static uint64_t max78000_gcr_read(void *opaque, hwaddr addr, 47 unsigned int size) 48 { 49 Max78000GcrState *s = opaque; 50 51 switch (addr) { 52 case SYSCTRL: 53 return s->sysctrl; 54 55 case RST0: 56 return s->rst0; 57 58 case CLKCTRL: 59 return s->clkctrl; 60 61 case PM: 62 return s->pm; 63 64 case PCLKDIV: 65 return s->pclkdiv; 66 67 case PCLKDIS0: 68 return s->pclkdis0; 69 70 case MEMCTRL: 71 return s->memctrl; 72 73 case MEMZ: 74 return s->memz; 75 76 case SYSST: 77 return s->sysst; 78 79 case RST1: 80 return s->rst1; 81 82 case PCKDIS1: 83 return s->pckdis1; 84 85 case EVENTEN: 86 return s->eventen; 87 88 case REVISION: 89 return s->revision; 90 91 case SYSIE: 92 return s->sysie; 93 94 case ECCERR: 95 return s->eccerr; 96 97 case ECCED: 98 return s->ecced; 99 100 case ECCIE: 101 return s->eccie; 102 103 case ECCADDR: 104 return s->eccaddr; 105 106 default: 107 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" 108 HWADDR_PRIx "\n", __func__, addr); 109 return 0; 110 111 } 112 } 113 114 static void max78000_gcr_write(void *opaque, hwaddr addr, 115 uint64_t val64, unsigned int size) 116 { 117 Max78000GcrState *s = opaque; 118 uint32_t val = val64; 119 uint8_t zero[0xc000] = {0}; 120 switch (addr) { 121 case SYSCTRL: 122 /* Checksum calculations always pass immediately */ 123 s->sysctrl = (val & 0x30000) | 0x1002; 124 break; 125 126 case RST0: 127 if (val & SYSTEM_RESET) { 128 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 129 } 130 if (val & PERIPHERAL_RESET) { 131 /* 132 * Peripheral reset resets all peripherals. The CPU 133 * retains its state. The GPIO, watchdog timers, AoD, 134 * RAM retention, and general control registers (GCR), 135 * including the clock configuration, are unaffected. 136 */ 137 val = UART2_RESET | UART1_RESET | UART0_RESET | 138 ADC_RESET | CNN_RESET | TRNG_RESET | 139 RTC_RESET | I2C0_RESET | SPI1_RESET | 140 TMR3_RESET | TMR2_RESET | TMR1_RESET | 141 TMR0_RESET | WDT0_RESET | DMA_RESET; 142 } 143 if (val & SOFT_RESET) { 144 /* Soft reset also resets GPIO */ 145 val = UART2_RESET | UART1_RESET | UART0_RESET | 146 ADC_RESET | CNN_RESET | TRNG_RESET | 147 RTC_RESET | I2C0_RESET | SPI1_RESET | 148 TMR3_RESET | TMR2_RESET | TMR1_RESET | 149 TMR0_RESET | GPIO1_RESET | GPIO0_RESET | 150 DMA_RESET; 151 } 152 if (val & UART2_RESET) { 153 device_cold_reset(s->uart2); 154 } 155 if (val & UART1_RESET) { 156 device_cold_reset(s->uart1); 157 } 158 if (val & UART0_RESET) { 159 device_cold_reset(s->uart0); 160 } 161 if (val & TRNG_RESET) { 162 device_cold_reset(s->trng); 163 } 164 /* TODO: As other devices are implemented, add them here */ 165 break; 166 167 case CLKCTRL: 168 s->clkctrl = val | SYSCLK_RDY; 169 break; 170 171 case PM: 172 s->pm = val; 173 break; 174 175 case PCLKDIV: 176 s->pclkdiv = val; 177 break; 178 179 case PCLKDIS0: 180 s->pclkdis0 = val; 181 break; 182 183 case MEMCTRL: 184 s->memctrl = val; 185 break; 186 187 case MEMZ: 188 if (val & ram0) { 189 address_space_write(&s->sram_as, SYSRAM0_START, 190 MEMTXATTRS_UNSPECIFIED, zero, 0x8000); 191 } 192 if (val & ram1) { 193 address_space_write(&s->sram_as, SYSRAM1_START, 194 MEMTXATTRS_UNSPECIFIED, zero, 0x8000); 195 } 196 if (val & ram2) { 197 address_space_write(&s->sram_as, SYSRAM2_START, 198 MEMTXATTRS_UNSPECIFIED, zero, 0xC000); 199 } 200 if (val & ram3) { 201 address_space_write(&s->sram_as, SYSRAM3_START, 202 MEMTXATTRS_UNSPECIFIED, zero, 0x4000); 203 } 204 break; 205 206 case SYSST: 207 s->sysst = val; 208 break; 209 210 case RST1: 211 /* TODO: As other devices are implemented, add them here */ 212 s->rst1 = val; 213 break; 214 215 case PCKDIS1: 216 s->pckdis1 = val; 217 break; 218 219 case EVENTEN: 220 s->eventen = val; 221 break; 222 223 case REVISION: 224 s->revision = val; 225 break; 226 227 case SYSIE: 228 s->sysie = val; 229 break; 230 231 case ECCERR: 232 s->eccerr = val; 233 break; 234 235 case ECCED: 236 s->ecced = val; 237 break; 238 239 case ECCIE: 240 s->eccie = val; 241 break; 242 243 case ECCADDR: 244 s->eccaddr = val; 245 break; 246 247 default: 248 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 249 __func__, addr); 250 break; 251 252 } 253 } 254 255 static const Property max78000_gcr_properties[] = { 256 DEFINE_PROP_LINK("sram", Max78000GcrState, sram, 257 TYPE_MEMORY_REGION, MemoryRegion*), 258 DEFINE_PROP_LINK("uart0", Max78000GcrState, uart0, 259 TYPE_MAX78000_UART, DeviceState*), 260 DEFINE_PROP_LINK("uart1", Max78000GcrState, uart1, 261 TYPE_MAX78000_UART, DeviceState*), 262 DEFINE_PROP_LINK("uart2", Max78000GcrState, uart2, 263 TYPE_MAX78000_UART, DeviceState*), 264 DEFINE_PROP_LINK("trng", Max78000GcrState, trng, 265 TYPE_MAX78000_TRNG, DeviceState*), 266 }; 267 268 static const MemoryRegionOps max78000_gcr_ops = { 269 .read = max78000_gcr_read, 270 .write = max78000_gcr_write, 271 .endianness = DEVICE_LITTLE_ENDIAN, 272 .valid.min_access_size = 4, 273 .valid.max_access_size = 4, 274 }; 275 276 static const VMStateDescription vmstate_max78000_gcr = { 277 .name = TYPE_MAX78000_GCR, 278 .version_id = 1, 279 .minimum_version_id = 1, 280 .fields = (const VMStateField[]) { 281 VMSTATE_UINT32(sysctrl, Max78000GcrState), 282 VMSTATE_UINT32(rst0, Max78000GcrState), 283 VMSTATE_UINT32(clkctrl, Max78000GcrState), 284 VMSTATE_UINT32(pm, Max78000GcrState), 285 VMSTATE_UINT32(pclkdiv, Max78000GcrState), 286 VMSTATE_UINT32(pclkdis0, Max78000GcrState), 287 VMSTATE_UINT32(memctrl, Max78000GcrState), 288 VMSTATE_UINT32(memz, Max78000GcrState), 289 VMSTATE_UINT32(sysst, Max78000GcrState), 290 VMSTATE_UINT32(rst1, Max78000GcrState), 291 VMSTATE_UINT32(pckdis1, Max78000GcrState), 292 VMSTATE_UINT32(eventen, Max78000GcrState), 293 VMSTATE_UINT32(revision, Max78000GcrState), 294 VMSTATE_UINT32(sysie, Max78000GcrState), 295 VMSTATE_UINT32(eccerr, Max78000GcrState), 296 VMSTATE_UINT32(ecced, Max78000GcrState), 297 VMSTATE_UINT32(eccie, Max78000GcrState), 298 VMSTATE_UINT32(eccaddr, Max78000GcrState), 299 VMSTATE_END_OF_LIST() 300 } 301 }; 302 303 static void max78000_gcr_init(Object *obj) 304 { 305 Max78000GcrState *s = MAX78000_GCR(obj); 306 307 memory_region_init_io(&s->mmio, obj, &max78000_gcr_ops, s, 308 TYPE_MAX78000_GCR, 0x400); 309 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 310 311 } 312 313 static void max78000_gcr_realize(DeviceState *dev, Error **errp) 314 { 315 Max78000GcrState *s = MAX78000_GCR(dev); 316 317 address_space_init(&s->sram_as, s->sram, "sram"); 318 } 319 320 static void max78000_gcr_class_init(ObjectClass *klass, const void *data) 321 { 322 DeviceClass *dc = DEVICE_CLASS(klass); 323 ResettableClass *rc = RESETTABLE_CLASS(klass); 324 325 device_class_set_props(dc, max78000_gcr_properties); 326 327 dc->realize = max78000_gcr_realize; 328 dc->vmsd = &vmstate_max78000_gcr; 329 rc->phases.hold = max78000_gcr_reset_hold; 330 } 331 332 static const TypeInfo max78000_gcr_info = { 333 .name = TYPE_MAX78000_GCR, 334 .parent = TYPE_SYS_BUS_DEVICE, 335 .instance_size = sizeof(Max78000GcrState), 336 .instance_init = max78000_gcr_init, 337 .class_init = max78000_gcr_class_init, 338 }; 339 340 static void max78000_gcr_register_types(void) 341 { 342 type_register_static(&max78000_gcr_info); 343 } 344 345 type_init(max78000_gcr_register_types) 346