1 /* 2 * QEMU PowerMac PMU device support 3 * 4 * Copyright (c) 2016 Benjamin Herrenschmidt, IBM Corp. 5 * Copyright (c) 2018 Mark Cave-Ayland 6 * 7 * Based on the CUDA device by: 8 * 9 * Copyright (c) 2004-2007 Fabrice Bellard 10 * Copyright (c) 2007 Jocelyn Mayer 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "hw/ppc/mac.h" 33 #include "hw/qdev-properties.h" 34 #include "migration/vmstate.h" 35 #include "hw/input/adb.h" 36 #include "hw/irq.h" 37 #include "hw/misc/mos6522.h" 38 #include "hw/misc/macio/gpio.h" 39 #include "hw/misc/macio/pmu.h" 40 #include "qapi/error.h" 41 #include "qemu/timer.h" 42 #include "sysemu/runstate.h" 43 #include "sysemu/rtc.h" 44 #include "qapi/error.h" 45 #include "qemu/cutils.h" 46 #include "qemu/log.h" 47 #include "qemu/module.h" 48 #include "trace.h" 49 50 51 /* Bits in B data register: all active low */ 52 #define TACK 0x08 /* Transfer request (input) */ 53 #define TREQ 0x10 /* Transfer acknowledge (output) */ 54 55 /* PMU returns time_t's offset from Jan 1, 1904, not 1970 */ 56 #define RTC_OFFSET 2082844800 57 58 #define VIA_TIMER_FREQ (4700000 / 6) 59 60 static void via_set_sr_int(void *opaque) 61 { 62 PMUState *s = opaque; 63 MOS6522PMUState *mps = MOS6522_PMU(&s->mos6522_pmu); 64 MOS6522State *ms = MOS6522(mps); 65 qemu_irq irq = qdev_get_gpio_in(DEVICE(ms), SR_INT_BIT); 66 67 qemu_set_irq(irq, 1); 68 } 69 70 static void pmu_update_extirq(PMUState *s) 71 { 72 if ((s->intbits & s->intmask) != 0) { 73 macio_set_gpio(s->gpio, 1, false); 74 } else { 75 macio_set_gpio(s->gpio, 1, true); 76 } 77 } 78 79 static void pmu_adb_poll(void *opaque) 80 { 81 PMUState *s = opaque; 82 ADBBusState *adb_bus = &s->adb_bus; 83 int olen; 84 85 if (!(s->intbits & PMU_INT_ADB)) { 86 olen = adb_poll(adb_bus, s->adb_reply, adb_bus->autopoll_mask); 87 trace_pmu_adb_poll(olen); 88 89 if (olen > 0) { 90 s->adb_reply_size = olen; 91 s->intbits |= PMU_INT_ADB | PMU_INT_ADB_AUTO; 92 pmu_update_extirq(s); 93 } 94 } 95 } 96 97 static void pmu_one_sec_timer(void *opaque) 98 { 99 PMUState *s = opaque; 100 101 trace_pmu_one_sec_timer(); 102 103 s->intbits |= PMU_INT_TICK; 104 pmu_update_extirq(s); 105 s->one_sec_target += 1000; 106 107 timer_mod(s->one_sec_timer, s->one_sec_target); 108 } 109 110 static void pmu_cmd_int_ack(PMUState *s, 111 const uint8_t *in_data, uint8_t in_len, 112 uint8_t *out_data, uint8_t *out_len) 113 { 114 if (in_len != 0) { 115 qemu_log_mask(LOG_GUEST_ERROR, 116 "PMU: INT_ACK command, invalid len: %d want: 0\n", 117 in_len); 118 return; 119 } 120 121 /* Make appropriate reply packet */ 122 if (s->intbits & PMU_INT_ADB) { 123 if (!s->adb_reply_size) { 124 qemu_log_mask(LOG_GUEST_ERROR, 125 "Odd, PMU_INT_ADB set with no reply in buffer\n"); 126 } 127 128 memcpy(out_data + 1, s->adb_reply, s->adb_reply_size); 129 out_data[0] = s->intbits & (PMU_INT_ADB | PMU_INT_ADB_AUTO); 130 *out_len = s->adb_reply_size + 1; 131 s->intbits &= ~(PMU_INT_ADB | PMU_INT_ADB_AUTO); 132 s->adb_reply_size = 0; 133 } else { 134 out_data[0] = s->intbits; 135 s->intbits = 0; 136 *out_len = 1; 137 } 138 139 pmu_update_extirq(s); 140 } 141 142 static void pmu_cmd_set_int_mask(PMUState *s, 143 const uint8_t *in_data, uint8_t in_len, 144 uint8_t *out_data, uint8_t *out_len) 145 { 146 if (in_len != 1) { 147 qemu_log_mask(LOG_GUEST_ERROR, 148 "PMU: SET_INT_MASK command, invalid len: %d want: 1\n", 149 in_len); 150 return; 151 } 152 153 trace_pmu_cmd_set_int_mask(s->intmask); 154 s->intmask = in_data[0]; 155 156 pmu_update_extirq(s); 157 } 158 159 static void pmu_cmd_set_adb_autopoll(PMUState *s, uint16_t mask) 160 { 161 ADBBusState *adb_bus = &s->adb_bus; 162 163 trace_pmu_cmd_set_adb_autopoll(mask); 164 165 if (mask) { 166 adb_set_autopoll_mask(adb_bus, mask); 167 adb_set_autopoll_enabled(adb_bus, true); 168 } else { 169 adb_set_autopoll_enabled(adb_bus, false); 170 } 171 } 172 173 static void pmu_cmd_adb(PMUState *s, 174 const uint8_t *in_data, uint8_t in_len, 175 uint8_t *out_data, uint8_t *out_len) 176 { 177 int len, adblen; 178 uint8_t adb_cmd[255]; 179 180 if (in_len < 2) { 181 qemu_log_mask(LOG_GUEST_ERROR, 182 "PMU: ADB PACKET, invalid len: %d want at least 2\n", 183 in_len); 184 return; 185 } 186 187 *out_len = 0; 188 189 if (!s->has_adb) { 190 trace_pmu_cmd_adb_nobus(); 191 return; 192 } 193 194 /* Set autopoll is a special form of the command */ 195 if (in_data[0] == 0 && in_data[1] == 0x86) { 196 uint16_t mask = in_data[2]; 197 mask = (mask << 8) | in_data[3]; 198 if (in_len != 4) { 199 qemu_log_mask(LOG_GUEST_ERROR, 200 "PMU: ADB Autopoll requires 4 bytes, got %d\n", 201 in_len); 202 return; 203 } 204 205 pmu_cmd_set_adb_autopoll(s, mask); 206 return; 207 } 208 209 trace_pmu_cmd_adb_request(in_len, in_data[0], in_data[1], in_data[2], 210 in_data[3], in_data[4]); 211 212 *out_len = 0; 213 214 /* Check ADB len */ 215 adblen = in_data[2]; 216 if (adblen > (in_len - 3)) { 217 qemu_log_mask(LOG_GUEST_ERROR, 218 "PMU: ADB len is %d > %d (in_len -3)...erroring\n", 219 adblen, in_len - 3); 220 len = -1; 221 } else if (adblen > 252) { 222 qemu_log_mask(LOG_GUEST_ERROR, "PMU: ADB command too big!\n"); 223 len = -1; 224 } else { 225 /* Format command */ 226 adb_cmd[0] = in_data[0]; 227 memcpy(&adb_cmd[1], &in_data[3], in_len - 3); 228 len = adb_request(&s->adb_bus, s->adb_reply + 2, adb_cmd, in_len - 2); 229 230 trace_pmu_cmd_adb_reply(len); 231 } 232 233 if (len > 0) { 234 /* XXX Check this */ 235 s->adb_reply_size = len + 2; 236 s->adb_reply[0] = 0x01; 237 s->adb_reply[1] = len; 238 } else { 239 /* XXX Check this */ 240 s->adb_reply_size = 1; 241 s->adb_reply[0] = 0x00; 242 } 243 244 s->intbits |= PMU_INT_ADB; 245 pmu_update_extirq(s); 246 } 247 248 static void pmu_cmd_adb_poll_off(PMUState *s, 249 const uint8_t *in_data, uint8_t in_len, 250 uint8_t *out_data, uint8_t *out_len) 251 { 252 ADBBusState *adb_bus = &s->adb_bus; 253 254 if (in_len != 0) { 255 qemu_log_mask(LOG_GUEST_ERROR, 256 "PMU: ADB POLL OFF command, invalid len: %d want: 0\n", 257 in_len); 258 return; 259 } 260 261 if (s->has_adb) { 262 adb_set_autopoll_enabled(adb_bus, false); 263 } 264 } 265 266 static void pmu_cmd_shutdown(PMUState *s, 267 const uint8_t *in_data, uint8_t in_len, 268 uint8_t *out_data, uint8_t *out_len) 269 { 270 if (in_len != 4) { 271 qemu_log_mask(LOG_GUEST_ERROR, 272 "PMU: SHUTDOWN command, invalid len: %d want: 4\n", 273 in_len); 274 return; 275 } 276 277 *out_len = 1; 278 out_data[0] = 0; 279 280 if (in_data[0] != 'M' || in_data[1] != 'A' || in_data[2] != 'T' || 281 in_data[3] != 'T') { 282 283 qemu_log_mask(LOG_GUEST_ERROR, 284 "PMU: SHUTDOWN command, Bad MATT signature\n"); 285 return; 286 } 287 288 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 289 } 290 291 static void pmu_cmd_reset(PMUState *s, 292 const uint8_t *in_data, uint8_t in_len, 293 uint8_t *out_data, uint8_t *out_len) 294 { 295 if (in_len != 0) { 296 qemu_log_mask(LOG_GUEST_ERROR, 297 "PMU: RESET command, invalid len: %d want: 0\n", 298 in_len); 299 return; 300 } 301 302 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 303 } 304 305 static void pmu_cmd_get_rtc(PMUState *s, 306 const uint8_t *in_data, uint8_t in_len, 307 uint8_t *out_data, uint8_t *out_len) 308 { 309 uint32_t ti; 310 311 if (in_len != 0) { 312 qemu_log_mask(LOG_GUEST_ERROR, 313 "PMU: GET_RTC command, invalid len: %d want: 0\n", 314 in_len); 315 return; 316 } 317 318 ti = s->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) 319 / NANOSECONDS_PER_SECOND); 320 out_data[0] = ti >> 24; 321 out_data[1] = ti >> 16; 322 out_data[2] = ti >> 8; 323 out_data[3] = ti; 324 *out_len = 4; 325 } 326 327 static void pmu_cmd_set_rtc(PMUState *s, 328 const uint8_t *in_data, uint8_t in_len, 329 uint8_t *out_data, uint8_t *out_len) 330 { 331 uint32_t ti; 332 333 if (in_len != 4) { 334 qemu_log_mask(LOG_GUEST_ERROR, 335 "PMU: SET_RTC command, invalid len: %d want: 4\n", 336 in_len); 337 return; 338 } 339 340 ti = (((uint32_t)in_data[0]) << 24) + (((uint32_t)in_data[1]) << 16) 341 + (((uint32_t)in_data[2]) << 8) + in_data[3]; 342 343 s->tick_offset = ti - (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) 344 / NANOSECONDS_PER_SECOND); 345 } 346 347 static void pmu_cmd_system_ready(PMUState *s, 348 const uint8_t *in_data, uint8_t in_len, 349 uint8_t *out_data, uint8_t *out_len) 350 { 351 /* Do nothing */ 352 } 353 354 static void pmu_cmd_get_version(PMUState *s, 355 const uint8_t *in_data, uint8_t in_len, 356 uint8_t *out_data, uint8_t *out_len) 357 { 358 *out_len = 1; 359 *out_data = 1; /* ??? Check what Apple does */ 360 } 361 362 static void pmu_cmd_power_events(PMUState *s, 363 const uint8_t *in_data, uint8_t in_len, 364 uint8_t *out_data, uint8_t *out_len) 365 { 366 if (in_len < 1) { 367 qemu_log_mask(LOG_GUEST_ERROR, 368 "PMU: POWER EVENTS command, invalid len %d, want at least 1\n", 369 in_len); 370 return; 371 } 372 373 switch (in_data[0]) { 374 /* Dummies for now */ 375 case PMU_PWR_GET_POWERUP_EVENTS: 376 *out_len = 2; 377 out_data[0] = 0; 378 out_data[1] = 0; 379 break; 380 case PMU_PWR_SET_POWERUP_EVENTS: 381 case PMU_PWR_CLR_POWERUP_EVENTS: 382 break; 383 case PMU_PWR_GET_WAKEUP_EVENTS: 384 *out_len = 2; 385 out_data[0] = 0; 386 out_data[1] = 0; 387 break; 388 case PMU_PWR_SET_WAKEUP_EVENTS: 389 case PMU_PWR_CLR_WAKEUP_EVENTS: 390 break; 391 default: 392 qemu_log_mask(LOG_GUEST_ERROR, 393 "PMU: POWER EVENTS unknown subcommand 0x%02x\n", 394 in_data[0]); 395 } 396 } 397 398 static void pmu_cmd_get_cover(PMUState *s, 399 const uint8_t *in_data, uint8_t in_len, 400 uint8_t *out_data, uint8_t *out_len) 401 { 402 /* Not 100% sure here, will have to check what a real Mac 403 * returns other than byte 0 bit 0 is LID closed on laptops 404 */ 405 *out_len = 1; 406 *out_data = 0x00; 407 } 408 409 static void pmu_cmd_download_status(PMUState *s, 410 const uint8_t *in_data, uint8_t in_len, 411 uint8_t *out_data, uint8_t *out_len) 412 { 413 /* This has to do with PMU firmware updates as far as I can tell. 414 * 415 * We return 0x62 which is what OpenPMU expects 416 */ 417 *out_len = 1; 418 *out_data = 0x62; 419 } 420 421 static void pmu_cmd_read_pmu_ram(PMUState *s, 422 const uint8_t *in_data, uint8_t in_len, 423 uint8_t *out_data, uint8_t *out_len) 424 { 425 if (in_len < 3) { 426 qemu_log_mask(LOG_GUEST_ERROR, 427 "PMU: READ_PMU_RAM command, invalid len %d, expected 3\n", 428 in_len); 429 return; 430 } 431 432 qemu_log_mask(LOG_GUEST_ERROR, 433 "PMU: Unsupported READ_PMU_RAM, args: %02x %02x %02x\n", 434 in_data[0], in_data[1], in_data[2]); 435 436 *out_len = 0; 437 } 438 439 /* description of commands */ 440 typedef struct PMUCmdHandler { 441 uint8_t command; 442 const char *name; 443 void (*handler)(PMUState *s, 444 const uint8_t *in_args, uint8_t in_len, 445 uint8_t *out_args, uint8_t *out_len); 446 } PMUCmdHandler; 447 448 static const PMUCmdHandler PMUCmdHandlers[] = { 449 { PMU_INT_ACK, "INT ACK", pmu_cmd_int_ack }, 450 { PMU_SET_INTR_MASK, "SET INT MASK", pmu_cmd_set_int_mask }, 451 { PMU_ADB_CMD, "ADB COMMAND", pmu_cmd_adb }, 452 { PMU_ADB_POLL_OFF, "ADB POLL OFF", pmu_cmd_adb_poll_off }, 453 { PMU_RESET, "REBOOT", pmu_cmd_reset }, 454 { PMU_SHUTDOWN, "SHUTDOWN", pmu_cmd_shutdown }, 455 { PMU_READ_RTC, "GET RTC", pmu_cmd_get_rtc }, 456 { PMU_SET_RTC, "SET RTC", pmu_cmd_set_rtc }, 457 { PMU_SYSTEM_READY, "SYSTEM READY", pmu_cmd_system_ready }, 458 { PMU_GET_VERSION, "GET VERSION", pmu_cmd_get_version }, 459 { PMU_POWER_EVENTS, "POWER EVENTS", pmu_cmd_power_events }, 460 { PMU_GET_COVER, "GET_COVER", pmu_cmd_get_cover }, 461 { PMU_DOWNLOAD_STATUS, "DOWNLOAD STATUS", pmu_cmd_download_status }, 462 { PMU_READ_PMU_RAM, "READ PMGR RAM", pmu_cmd_read_pmu_ram }, 463 }; 464 465 static void pmu_dispatch_cmd(PMUState *s) 466 { 467 unsigned int i; 468 469 /* No response by default */ 470 s->cmd_rsp_sz = 0; 471 472 for (i = 0; i < ARRAY_SIZE(PMUCmdHandlers); i++) { 473 const PMUCmdHandler *desc = &PMUCmdHandlers[i]; 474 475 if (desc->command != s->cmd) { 476 continue; 477 } 478 479 trace_pmu_dispatch_cmd(desc->name); 480 desc->handler(s, s->cmd_buf, s->cmd_buf_pos, 481 s->cmd_rsp, &s->cmd_rsp_sz); 482 483 if (s->rsplen != -1 && s->rsplen != s->cmd_rsp_sz) { 484 trace_pmu_debug_protocol_string("QEMU internal cmd resp mismatch!"); 485 } else { 486 trace_pmu_debug_protocol_resp_size(s->cmd_rsp_sz); 487 } 488 489 return; 490 } 491 492 trace_pmu_dispatch_unknown_cmd(s->cmd); 493 494 /* Manufacture fake response with 0's */ 495 if (s->rsplen == -1) { 496 s->cmd_rsp_sz = 0; 497 } else { 498 s->cmd_rsp_sz = s->rsplen; 499 memset(s->cmd_rsp, 0, s->rsplen); 500 } 501 } 502 503 static void pmu_update(PMUState *s) 504 { 505 MOS6522PMUState *mps = &s->mos6522_pmu; 506 MOS6522State *ms = MOS6522(mps); 507 ADBBusState *adb_bus = &s->adb_bus; 508 509 /* Only react to changes in reg B */ 510 if (ms->b == s->last_b) { 511 return; 512 } 513 s->last_b = ms->b; 514 515 /* Check the TREQ / TACK state */ 516 switch (ms->b & (TREQ | TACK)) { 517 case TREQ: 518 /* This is an ack release, handle it and bail out */ 519 ms->b |= TACK; 520 s->last_b = ms->b; 521 522 trace_pmu_debug_protocol_string("handshake: TREQ high, setting TACK"); 523 return; 524 case TACK: 525 /* This is a valid request, handle below */ 526 break; 527 case TREQ | TACK: 528 /* This is an idle state */ 529 return; 530 default: 531 /* Invalid state, log and ignore */ 532 trace_pmu_debug_protocol_error(ms->b); 533 return; 534 } 535 536 /* If we wanted to handle commands asynchronously, this is where 537 * we would delay the clearing of TACK until we are ready to send 538 * the response 539 */ 540 541 /* We have a request, handshake TACK so we don't stay in 542 * an invalid state. If we were concurrent with the OS we 543 * should only do this after we grabbed the SR but that isn't 544 * a problem here. 545 */ 546 547 trace_pmu_debug_protocol_clear_treq(s->cmd_state); 548 549 ms->b &= ~TACK; 550 s->last_b = ms->b; 551 552 /* Act according to state */ 553 switch (s->cmd_state) { 554 case pmu_state_idle: 555 if (!(ms->acr & SR_OUT)) { 556 trace_pmu_debug_protocol_string("protocol error! " 557 "state idle, ACR reading"); 558 break; 559 } 560 561 s->cmd = ms->sr; 562 via_set_sr_int(s); 563 s->cmdlen = pmu_data_len[s->cmd][0]; 564 s->rsplen = pmu_data_len[s->cmd][1]; 565 s->cmd_buf_pos = 0; 566 s->cmd_rsp_pos = 0; 567 s->cmd_state = pmu_state_cmd; 568 569 adb_autopoll_block(adb_bus); 570 trace_pmu_debug_protocol_cmd(s->cmd, s->cmdlen, s->rsplen); 571 break; 572 573 case pmu_state_cmd: 574 if (!(ms->acr & SR_OUT)) { 575 trace_pmu_debug_protocol_string("protocol error! " 576 "state cmd, ACR reading"); 577 break; 578 } 579 580 if (s->cmdlen == -1) { 581 trace_pmu_debug_protocol_cmdlen(ms->sr); 582 583 s->cmdlen = ms->sr; 584 if (s->cmdlen > sizeof(s->cmd_buf)) { 585 trace_pmu_debug_protocol_cmd_toobig(s->cmdlen); 586 } 587 } else if (s->cmd_buf_pos < sizeof(s->cmd_buf)) { 588 s->cmd_buf[s->cmd_buf_pos++] = ms->sr; 589 } 590 591 via_set_sr_int(s); 592 break; 593 594 case pmu_state_rsp: 595 if (ms->acr & SR_OUT) { 596 trace_pmu_debug_protocol_string("protocol error! " 597 "state resp, ACR writing"); 598 break; 599 } 600 601 if (s->rsplen == -1) { 602 trace_pmu_debug_protocol_cmd_send_resp_size(s->cmd_rsp_sz); 603 604 ms->sr = s->cmd_rsp_sz; 605 s->rsplen = s->cmd_rsp_sz; 606 } else if (s->cmd_rsp_pos < s->cmd_rsp_sz) { 607 trace_pmu_debug_protocol_cmd_send_resp(s->cmd_rsp_pos, s->rsplen); 608 609 ms->sr = s->cmd_rsp[s->cmd_rsp_pos++]; 610 } 611 612 via_set_sr_int(s); 613 break; 614 } 615 616 /* Check for state completion */ 617 if (s->cmd_state == pmu_state_cmd && s->cmdlen == s->cmd_buf_pos) { 618 trace_pmu_debug_protocol_string("Command reception complete, " 619 "dispatching..."); 620 621 pmu_dispatch_cmd(s); 622 s->cmd_state = pmu_state_rsp; 623 } 624 625 if (s->cmd_state == pmu_state_rsp && s->rsplen == s->cmd_rsp_pos) { 626 trace_pmu_debug_protocol_cmd_resp_complete(ms->ier); 627 628 adb_autopoll_unblock(adb_bus); 629 s->cmd_state = pmu_state_idle; 630 } 631 } 632 633 static uint64_t mos6522_pmu_read(void *opaque, hwaddr addr, unsigned size) 634 { 635 PMUState *s = opaque; 636 MOS6522PMUState *mps = &s->mos6522_pmu; 637 MOS6522State *ms = MOS6522(mps); 638 639 addr = (addr >> 9) & 0xf; 640 return mos6522_read(ms, addr, size); 641 } 642 643 static void mos6522_pmu_write(void *opaque, hwaddr addr, uint64_t val, 644 unsigned size) 645 { 646 PMUState *s = opaque; 647 MOS6522PMUState *mps = &s->mos6522_pmu; 648 MOS6522State *ms = MOS6522(mps); 649 650 addr = (addr >> 9) & 0xf; 651 mos6522_write(ms, addr, val, size); 652 } 653 654 static const MemoryRegionOps mos6522_pmu_ops = { 655 .read = mos6522_pmu_read, 656 .write = mos6522_pmu_write, 657 .endianness = DEVICE_BIG_ENDIAN, 658 .impl = { 659 .min_access_size = 1, 660 .max_access_size = 1, 661 }, 662 }; 663 664 static bool pmu_adb_state_needed(void *opaque) 665 { 666 PMUState *s = opaque; 667 668 return s->has_adb; 669 } 670 671 static const VMStateDescription vmstate_pmu_adb = { 672 .name = "pmu/adb", 673 .version_id = 1, 674 .minimum_version_id = 1, 675 .needed = pmu_adb_state_needed, 676 .fields = (VMStateField[]) { 677 VMSTATE_UINT8(adb_reply_size, PMUState), 678 VMSTATE_BUFFER(adb_reply, PMUState), 679 VMSTATE_END_OF_LIST() 680 } 681 }; 682 683 static const VMStateDescription vmstate_pmu = { 684 .name = "pmu", 685 .version_id = 1, 686 .minimum_version_id = 1, 687 .fields = (VMStateField[]) { 688 VMSTATE_STRUCT(mos6522_pmu.parent_obj, PMUState, 0, vmstate_mos6522, 689 MOS6522State), 690 VMSTATE_UINT8(last_b, PMUState), 691 VMSTATE_UINT8(cmd, PMUState), 692 VMSTATE_UINT32(cmdlen, PMUState), 693 VMSTATE_UINT32(rsplen, PMUState), 694 VMSTATE_UINT8(cmd_buf_pos, PMUState), 695 VMSTATE_BUFFER(cmd_buf, PMUState), 696 VMSTATE_UINT8(cmd_rsp_pos, PMUState), 697 VMSTATE_UINT8(cmd_rsp_sz, PMUState), 698 VMSTATE_BUFFER(cmd_rsp, PMUState), 699 VMSTATE_UINT8(intbits, PMUState), 700 VMSTATE_UINT8(intmask, PMUState), 701 VMSTATE_UINT32(tick_offset, PMUState), 702 VMSTATE_TIMER_PTR(one_sec_timer, PMUState), 703 VMSTATE_INT64(one_sec_target, PMUState), 704 VMSTATE_END_OF_LIST() 705 }, 706 .subsections = (const VMStateDescription * []) { 707 &vmstate_pmu_adb, 708 NULL 709 } 710 }; 711 712 static void pmu_reset(DeviceState *dev) 713 { 714 PMUState *s = VIA_PMU(dev); 715 716 /* OpenBIOS needs to do this? MacOS 9 needs it */ 717 s->intmask = PMU_INT_ADB | PMU_INT_TICK; 718 s->intbits = 0; 719 720 s->cmd_state = pmu_state_idle; 721 } 722 723 static void pmu_realize(DeviceState *dev, Error **errp) 724 { 725 PMUState *s = VIA_PMU(dev); 726 SysBusDevice *sbd; 727 ADBBusState *adb_bus = &s->adb_bus; 728 struct tm tm; 729 730 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mos6522_pmu), errp)) { 731 return; 732 } 733 734 /* Pass IRQ from 6522 */ 735 sbd = SYS_BUS_DEVICE(s); 736 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->mos6522_pmu)); 737 738 qemu_get_timedate(&tm, 0); 739 s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; 740 s->one_sec_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, pmu_one_sec_timer, s); 741 s->one_sec_target = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000; 742 timer_mod(s->one_sec_timer, s->one_sec_target); 743 744 if (s->has_adb) { 745 qbus_init(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS, 746 dev, "adb.0"); 747 adb_register_autopoll_callback(adb_bus, pmu_adb_poll, s); 748 } 749 } 750 751 static void pmu_init(Object *obj) 752 { 753 SysBusDevice *d = SYS_BUS_DEVICE(obj); 754 PMUState *s = VIA_PMU(obj); 755 756 object_property_add_link(obj, "gpio", TYPE_MACIO_GPIO, 757 (Object **) &s->gpio, 758 qdev_prop_allow_set_link_before_realize, 759 0); 760 761 object_initialize_child(obj, "mos6522-pmu", &s->mos6522_pmu, 762 TYPE_MOS6522_PMU); 763 764 memory_region_init_io(&s->mem, obj, &mos6522_pmu_ops, s, "via-pmu", 765 0x2000); 766 sysbus_init_mmio(d, &s->mem); 767 } 768 769 static Property pmu_properties[] = { 770 DEFINE_PROP_BOOL("has-adb", PMUState, has_adb, true), 771 DEFINE_PROP_END_OF_LIST() 772 }; 773 774 static void pmu_class_init(ObjectClass *oc, void *data) 775 { 776 DeviceClass *dc = DEVICE_CLASS(oc); 777 778 dc->realize = pmu_realize; 779 dc->reset = pmu_reset; 780 dc->vmsd = &vmstate_pmu; 781 device_class_set_props(dc, pmu_properties); 782 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 783 } 784 785 static const TypeInfo pmu_type_info = { 786 .name = TYPE_VIA_PMU, 787 .parent = TYPE_SYS_BUS_DEVICE, 788 .instance_size = sizeof(PMUState), 789 .instance_init = pmu_init, 790 .class_init = pmu_class_init, 791 }; 792 793 static void mos6522_pmu_portB_write(MOS6522State *s) 794 { 795 MOS6522PMUState *mps = container_of(s, MOS6522PMUState, parent_obj); 796 PMUState *ps = container_of(mps, PMUState, mos6522_pmu); 797 798 pmu_update(ps); 799 } 800 801 static void mos6522_pmu_reset(DeviceState *dev) 802 { 803 MOS6522State *ms = MOS6522(dev); 804 MOS6522PMUState *mps = container_of(ms, MOS6522PMUState, parent_obj); 805 PMUState *s = container_of(mps, PMUState, mos6522_pmu); 806 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); 807 808 mdc->parent_reset(dev); 809 810 ms->timers[0].frequency = VIA_TIMER_FREQ; 811 ms->timers[1].frequency = (SCALE_US * 6000) / 4700; 812 813 s->last_b = ms->b = TACK | TREQ; 814 } 815 816 static void mos6522_pmu_class_init(ObjectClass *oc, void *data) 817 { 818 DeviceClass *dc = DEVICE_CLASS(oc); 819 MOS6522DeviceClass *mdc = MOS6522_CLASS(oc); 820 821 device_class_set_parent_reset(dc, mos6522_pmu_reset, 822 &mdc->parent_reset); 823 mdc->portB_write = mos6522_pmu_portB_write; 824 } 825 826 static const TypeInfo mos6522_pmu_type_info = { 827 .name = TYPE_MOS6522_PMU, 828 .parent = TYPE_MOS6522, 829 .instance_size = sizeof(MOS6522PMUState), 830 .class_init = mos6522_pmu_class_init, 831 }; 832 833 static void pmu_register_types(void) 834 { 835 type_register_static(&pmu_type_info); 836 type_register_static(&mos6522_pmu_type_info); 837 } 838 839 type_init(pmu_register_types) 840