1 /* 2 * QEMU PowerMac PMU device support 3 * 4 * Copyright (c) 2016 Benjamin Herrenschmidt, IBM Corp. 5 * Copyright (c) 2018 Mark Cave-Ayland 6 * 7 * Based on the CUDA device by: 8 * 9 * Copyright (c) 2004-2007 Fabrice Bellard 10 * Copyright (c) 2007 Jocelyn Mayer 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu-common.h" 33 #include "hw/hw.h" 34 #include "hw/ppc/mac.h" 35 #include "hw/input/adb.h" 36 #include "hw/irq.h" 37 #include "hw/misc/mos6522.h" 38 #include "hw/misc/macio/gpio.h" 39 #include "hw/misc/macio/pmu.h" 40 #include "qemu/timer.h" 41 #include "sysemu/sysemu.h" 42 #include "qemu/cutils.h" 43 #include "qemu/log.h" 44 #include "qemu/module.h" 45 #include "trace.h" 46 47 48 /* Bits in B data register: all active low */ 49 #define TACK 0x08 /* Transfer request (input) */ 50 #define TREQ 0x10 /* Transfer acknowledge (output) */ 51 52 /* PMU returns time_t's offset from Jan 1, 1904, not 1970 */ 53 #define RTC_OFFSET 2082844800 54 55 #define VIA_TIMER_FREQ (4700000 / 6) 56 57 static void via_update_irq(PMUState *s) 58 { 59 MOS6522PMUState *mps = MOS6522_PMU(&s->mos6522_pmu); 60 MOS6522State *ms = MOS6522(mps); 61 62 bool new_state = !!(ms->ifr & ms->ier & (SR_INT | T1_INT | T2_INT)); 63 64 if (new_state != s->via_irq_state) { 65 s->via_irq_state = new_state; 66 qemu_set_irq(s->via_irq, new_state); 67 } 68 } 69 70 static void via_set_sr_int(void *opaque) 71 { 72 PMUState *s = opaque; 73 MOS6522PMUState *mps = MOS6522_PMU(&s->mos6522_pmu); 74 MOS6522State *ms = MOS6522(mps); 75 MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(ms); 76 77 mdc->set_sr_int(ms); 78 } 79 80 static void pmu_update_extirq(PMUState *s) 81 { 82 if ((s->intbits & s->intmask) != 0) { 83 macio_set_gpio(s->gpio, 1, false); 84 } else { 85 macio_set_gpio(s->gpio, 1, true); 86 } 87 } 88 89 static void pmu_adb_poll(void *opaque) 90 { 91 PMUState *s = opaque; 92 int olen; 93 94 if (!(s->intbits & PMU_INT_ADB)) { 95 olen = adb_poll(&s->adb_bus, s->adb_reply, s->adb_poll_mask); 96 trace_pmu_adb_poll(olen); 97 98 if (olen > 0) { 99 s->adb_reply_size = olen; 100 s->intbits |= PMU_INT_ADB | PMU_INT_ADB_AUTO; 101 pmu_update_extirq(s); 102 } 103 } 104 105 timer_mod(s->adb_poll_timer, 106 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 30); 107 } 108 109 static void pmu_one_sec_timer(void *opaque) 110 { 111 PMUState *s = opaque; 112 113 trace_pmu_one_sec_timer(); 114 115 s->intbits |= PMU_INT_TICK; 116 pmu_update_extirq(s); 117 s->one_sec_target += 1000; 118 119 timer_mod(s->one_sec_timer, s->one_sec_target); 120 } 121 122 static void pmu_cmd_int_ack(PMUState *s, 123 const uint8_t *in_data, uint8_t in_len, 124 uint8_t *out_data, uint8_t *out_len) 125 { 126 if (in_len != 0) { 127 qemu_log_mask(LOG_GUEST_ERROR, 128 "PMU: INT_ACK command, invalid len: %d want: 0\n", 129 in_len); 130 return; 131 } 132 133 /* Make appropriate reply packet */ 134 if (s->intbits & PMU_INT_ADB) { 135 if (!s->adb_reply_size) { 136 qemu_log_mask(LOG_GUEST_ERROR, 137 "Odd, PMU_INT_ADB set with no reply in buffer\n"); 138 } 139 140 memcpy(out_data + 1, s->adb_reply, s->adb_reply_size); 141 out_data[0] = s->intbits & (PMU_INT_ADB | PMU_INT_ADB_AUTO); 142 *out_len = s->adb_reply_size + 1; 143 s->intbits &= ~(PMU_INT_ADB | PMU_INT_ADB_AUTO); 144 s->adb_reply_size = 0; 145 } else { 146 out_data[0] = s->intbits; 147 s->intbits = 0; 148 *out_len = 1; 149 } 150 151 pmu_update_extirq(s); 152 } 153 154 static void pmu_cmd_set_int_mask(PMUState *s, 155 const uint8_t *in_data, uint8_t in_len, 156 uint8_t *out_data, uint8_t *out_len) 157 { 158 if (in_len != 1) { 159 qemu_log_mask(LOG_GUEST_ERROR, 160 "PMU: SET_INT_MASK command, invalid len: %d want: 1\n", 161 in_len); 162 return; 163 } 164 165 trace_pmu_cmd_set_int_mask(s->intmask); 166 s->intmask = in_data[0]; 167 168 pmu_update_extirq(s); 169 } 170 171 static void pmu_cmd_set_adb_autopoll(PMUState *s, uint16_t mask) 172 { 173 trace_pmu_cmd_set_adb_autopoll(mask); 174 175 if (s->autopoll_mask == mask) { 176 return; 177 } 178 179 s->autopoll_mask = mask; 180 if (mask) { 181 timer_mod(s->adb_poll_timer, 182 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 30); 183 } else { 184 timer_del(s->adb_poll_timer); 185 } 186 } 187 188 static void pmu_cmd_adb(PMUState *s, 189 const uint8_t *in_data, uint8_t in_len, 190 uint8_t *out_data, uint8_t *out_len) 191 { 192 int len, adblen; 193 uint8_t adb_cmd[255]; 194 195 if (in_len < 2) { 196 qemu_log_mask(LOG_GUEST_ERROR, 197 "PMU: ADB PACKET, invalid len: %d want at least 2\n", 198 in_len); 199 return; 200 } 201 202 *out_len = 0; 203 204 if (!s->has_adb) { 205 trace_pmu_cmd_adb_nobus(); 206 return; 207 } 208 209 /* Set autopoll is a special form of the command */ 210 if (in_data[0] == 0 && in_data[1] == 0x86) { 211 uint16_t mask = in_data[2]; 212 mask = (mask << 8) | in_data[3]; 213 if (in_len != 4) { 214 qemu_log_mask(LOG_GUEST_ERROR, 215 "PMU: ADB Autopoll requires 4 bytes, got %d\n", 216 in_len); 217 return; 218 } 219 220 pmu_cmd_set_adb_autopoll(s, mask); 221 return; 222 } 223 224 trace_pmu_cmd_adb_request(in_len, in_data[0], in_data[1], in_data[2], 225 in_data[3], in_data[4]); 226 227 *out_len = 0; 228 229 /* Check ADB len */ 230 adblen = in_data[2]; 231 if (adblen > (in_len - 3)) { 232 qemu_log_mask(LOG_GUEST_ERROR, 233 "PMU: ADB len is %d > %d (in_len -3)...erroring\n", 234 adblen, in_len - 3); 235 len = -1; 236 } else if (adblen > 252) { 237 qemu_log_mask(LOG_GUEST_ERROR, "PMU: ADB command too big!\n"); 238 len = -1; 239 } else { 240 /* Format command */ 241 adb_cmd[0] = in_data[0]; 242 memcpy(&adb_cmd[1], &in_data[3], in_len - 3); 243 len = adb_request(&s->adb_bus, s->adb_reply + 2, adb_cmd, in_len - 2); 244 245 trace_pmu_cmd_adb_reply(len); 246 } 247 248 if (len > 0) { 249 /* XXX Check this */ 250 s->adb_reply_size = len + 2; 251 s->adb_reply[0] = 0x01; 252 s->adb_reply[1] = len; 253 } else { 254 /* XXX Check this */ 255 s->adb_reply_size = 1; 256 s->adb_reply[0] = 0x00; 257 } 258 259 s->intbits |= PMU_INT_ADB; 260 pmu_update_extirq(s); 261 } 262 263 static void pmu_cmd_adb_poll_off(PMUState *s, 264 const uint8_t *in_data, uint8_t in_len, 265 uint8_t *out_data, uint8_t *out_len) 266 { 267 if (in_len != 0) { 268 qemu_log_mask(LOG_GUEST_ERROR, 269 "PMU: ADB POLL OFF command, invalid len: %d want: 0\n", 270 in_len); 271 return; 272 } 273 274 if (s->has_adb && s->autopoll_mask) { 275 timer_del(s->adb_poll_timer); 276 s->autopoll_mask = false; 277 } 278 } 279 280 static void pmu_cmd_shutdown(PMUState *s, 281 const uint8_t *in_data, uint8_t in_len, 282 uint8_t *out_data, uint8_t *out_len) 283 { 284 if (in_len != 4) { 285 qemu_log_mask(LOG_GUEST_ERROR, 286 "PMU: SHUTDOWN command, invalid len: %d want: 4\n", 287 in_len); 288 return; 289 } 290 291 *out_len = 1; 292 out_data[0] = 0; 293 294 if (in_data[0] != 'M' || in_data[1] != 'A' || in_data[2] != 'T' || 295 in_data[3] != 'T') { 296 297 qemu_log_mask(LOG_GUEST_ERROR, 298 "PMU: SHUTDOWN command, Bad MATT signature\n"); 299 return; 300 } 301 302 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 303 } 304 305 static void pmu_cmd_reset(PMUState *s, 306 const uint8_t *in_data, uint8_t in_len, 307 uint8_t *out_data, uint8_t *out_len) 308 { 309 if (in_len != 0) { 310 qemu_log_mask(LOG_GUEST_ERROR, 311 "PMU: RESET command, invalid len: %d want: 0\n", 312 in_len); 313 return; 314 } 315 316 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 317 } 318 319 static void pmu_cmd_get_rtc(PMUState *s, 320 const uint8_t *in_data, uint8_t in_len, 321 uint8_t *out_data, uint8_t *out_len) 322 { 323 uint32_t ti; 324 325 if (in_len != 0) { 326 qemu_log_mask(LOG_GUEST_ERROR, 327 "PMU: GET_RTC command, invalid len: %d want: 0\n", 328 in_len); 329 return; 330 } 331 332 ti = s->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) 333 / NANOSECONDS_PER_SECOND); 334 out_data[0] = ti >> 24; 335 out_data[1] = ti >> 16; 336 out_data[2] = ti >> 8; 337 out_data[3] = ti; 338 *out_len = 4; 339 } 340 341 static void pmu_cmd_set_rtc(PMUState *s, 342 const uint8_t *in_data, uint8_t in_len, 343 uint8_t *out_data, uint8_t *out_len) 344 { 345 uint32_t ti; 346 347 if (in_len != 4) { 348 qemu_log_mask(LOG_GUEST_ERROR, 349 "PMU: SET_RTC command, invalid len: %d want: 4\n", 350 in_len); 351 return; 352 } 353 354 ti = (((uint32_t)in_data[0]) << 24) + (((uint32_t)in_data[1]) << 16) 355 + (((uint32_t)in_data[2]) << 8) + in_data[3]; 356 357 s->tick_offset = ti - (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) 358 / NANOSECONDS_PER_SECOND); 359 } 360 361 static void pmu_cmd_system_ready(PMUState *s, 362 const uint8_t *in_data, uint8_t in_len, 363 uint8_t *out_data, uint8_t *out_len) 364 { 365 /* Do nothing */ 366 } 367 368 static void pmu_cmd_get_version(PMUState *s, 369 const uint8_t *in_data, uint8_t in_len, 370 uint8_t *out_data, uint8_t *out_len) 371 { 372 *out_len = 1; 373 *out_data = 1; /* ??? Check what Apple does */ 374 } 375 376 static void pmu_cmd_power_events(PMUState *s, 377 const uint8_t *in_data, uint8_t in_len, 378 uint8_t *out_data, uint8_t *out_len) 379 { 380 if (in_len < 1) { 381 qemu_log_mask(LOG_GUEST_ERROR, 382 "PMU: POWER EVENTS command, invalid len %d, want at least 1\n", 383 in_len); 384 return; 385 } 386 387 switch (in_data[0]) { 388 /* Dummies for now */ 389 case PMU_PWR_GET_POWERUP_EVENTS: 390 *out_len = 2; 391 out_data[0] = 0; 392 out_data[1] = 0; 393 break; 394 case PMU_PWR_SET_POWERUP_EVENTS: 395 case PMU_PWR_CLR_POWERUP_EVENTS: 396 break; 397 case PMU_PWR_GET_WAKEUP_EVENTS: 398 *out_len = 2; 399 out_data[0] = 0; 400 out_data[1] = 0; 401 break; 402 case PMU_PWR_SET_WAKEUP_EVENTS: 403 case PMU_PWR_CLR_WAKEUP_EVENTS: 404 break; 405 default: 406 qemu_log_mask(LOG_GUEST_ERROR, 407 "PMU: POWER EVENTS unknown subcommand 0x%02x\n", 408 in_data[0]); 409 } 410 } 411 412 static void pmu_cmd_get_cover(PMUState *s, 413 const uint8_t *in_data, uint8_t in_len, 414 uint8_t *out_data, uint8_t *out_len) 415 { 416 /* Not 100% sure here, will have to check what a real Mac 417 * returns other than byte 0 bit 0 is LID closed on laptops 418 */ 419 *out_len = 1; 420 *out_data = 0x00; 421 } 422 423 static void pmu_cmd_download_status(PMUState *s, 424 const uint8_t *in_data, uint8_t in_len, 425 uint8_t *out_data, uint8_t *out_len) 426 { 427 /* This has to do with PMU firmware updates as far as I can tell. 428 * 429 * We return 0x62 which is what OpenPMU expects 430 */ 431 *out_len = 1; 432 *out_data = 0x62; 433 } 434 435 static void pmu_cmd_read_pmu_ram(PMUState *s, 436 const uint8_t *in_data, uint8_t in_len, 437 uint8_t *out_data, uint8_t *out_len) 438 { 439 if (in_len < 3) { 440 qemu_log_mask(LOG_GUEST_ERROR, 441 "PMU: READ_PMU_RAM command, invalid len %d, expected 3\n", 442 in_len); 443 return; 444 } 445 446 qemu_log_mask(LOG_GUEST_ERROR, 447 "PMU: Unsupported READ_PMU_RAM, args: %02x %02x %02x\n", 448 in_data[0], in_data[1], in_data[2]); 449 450 *out_len = 0; 451 } 452 453 /* description of commands */ 454 typedef struct PMUCmdHandler { 455 uint8_t command; 456 const char *name; 457 void (*handler)(PMUState *s, 458 const uint8_t *in_args, uint8_t in_len, 459 uint8_t *out_args, uint8_t *out_len); 460 } PMUCmdHandler; 461 462 static const PMUCmdHandler PMUCmdHandlers[] = { 463 { PMU_INT_ACK, "INT ACK", pmu_cmd_int_ack }, 464 { PMU_SET_INTR_MASK, "SET INT MASK", pmu_cmd_set_int_mask }, 465 { PMU_ADB_CMD, "ADB COMMAND", pmu_cmd_adb }, 466 { PMU_ADB_POLL_OFF, "ADB POLL OFF", pmu_cmd_adb_poll_off }, 467 { PMU_RESET, "REBOOT", pmu_cmd_reset }, 468 { PMU_SHUTDOWN, "SHUTDOWN", pmu_cmd_shutdown }, 469 { PMU_READ_RTC, "GET RTC", pmu_cmd_get_rtc }, 470 { PMU_SET_RTC, "SET RTC", pmu_cmd_set_rtc }, 471 { PMU_SYSTEM_READY, "SYSTEM READY", pmu_cmd_system_ready }, 472 { PMU_GET_VERSION, "GET VERSION", pmu_cmd_get_version }, 473 { PMU_POWER_EVENTS, "POWER EVENTS", pmu_cmd_power_events }, 474 { PMU_GET_COVER, "GET_COVER", pmu_cmd_get_cover }, 475 { PMU_DOWNLOAD_STATUS, "DOWNLOAD STATUS", pmu_cmd_download_status }, 476 { PMU_READ_PMU_RAM, "READ PMGR RAM", pmu_cmd_read_pmu_ram }, 477 }; 478 479 static void pmu_dispatch_cmd(PMUState *s) 480 { 481 unsigned int i; 482 483 /* No response by default */ 484 s->cmd_rsp_sz = 0; 485 486 for (i = 0; i < ARRAY_SIZE(PMUCmdHandlers); i++) { 487 const PMUCmdHandler *desc = &PMUCmdHandlers[i]; 488 489 if (desc->command != s->cmd) { 490 continue; 491 } 492 493 trace_pmu_dispatch_cmd(desc->name); 494 desc->handler(s, s->cmd_buf, s->cmd_buf_pos, 495 s->cmd_rsp, &s->cmd_rsp_sz); 496 497 if (s->rsplen != -1 && s->rsplen != s->cmd_rsp_sz) { 498 trace_pmu_debug_protocol_string("QEMU internal cmd resp mismatch!"); 499 } else { 500 trace_pmu_debug_protocol_resp_size(s->cmd_rsp_sz); 501 } 502 503 return; 504 } 505 506 trace_pmu_dispatch_unknown_cmd(s->cmd); 507 508 /* Manufacture fake response with 0's */ 509 if (s->rsplen == -1) { 510 s->cmd_rsp_sz = 0; 511 } else { 512 s->cmd_rsp_sz = s->rsplen; 513 memset(s->cmd_rsp, 0, s->rsplen); 514 } 515 } 516 517 static void pmu_update(PMUState *s) 518 { 519 MOS6522PMUState *mps = &s->mos6522_pmu; 520 MOS6522State *ms = MOS6522(mps); 521 522 /* Only react to changes in reg B */ 523 if (ms->b == s->last_b) { 524 return; 525 } 526 s->last_b = ms->b; 527 528 /* Check the TREQ / TACK state */ 529 switch (ms->b & (TREQ | TACK)) { 530 case TREQ: 531 /* This is an ack release, handle it and bail out */ 532 ms->b |= TACK; 533 s->last_b = ms->b; 534 535 trace_pmu_debug_protocol_string("handshake: TREQ high, setting TACK"); 536 return; 537 case TACK: 538 /* This is a valid request, handle below */ 539 break; 540 case TREQ | TACK: 541 /* This is an idle state */ 542 return; 543 default: 544 /* Invalid state, log and ignore */ 545 trace_pmu_debug_protocol_error(ms->b); 546 return; 547 } 548 549 /* If we wanted to handle commands asynchronously, this is where 550 * we would delay the clearing of TACK until we are ready to send 551 * the response 552 */ 553 554 /* We have a request, handshake TACK so we don't stay in 555 * an invalid state. If we were concurrent with the OS we 556 * should only do this after we grabbed the SR but that isn't 557 * a problem here. 558 */ 559 560 trace_pmu_debug_protocol_clear_treq(s->cmd_state); 561 562 ms->b &= ~TACK; 563 s->last_b = ms->b; 564 565 /* Act according to state */ 566 switch (s->cmd_state) { 567 case pmu_state_idle: 568 if (!(ms->acr & SR_OUT)) { 569 trace_pmu_debug_protocol_string("protocol error! " 570 "state idle, ACR reading"); 571 break; 572 } 573 574 s->cmd = ms->sr; 575 via_set_sr_int(s); 576 s->cmdlen = pmu_data_len[s->cmd][0]; 577 s->rsplen = pmu_data_len[s->cmd][1]; 578 s->cmd_buf_pos = 0; 579 s->cmd_rsp_pos = 0; 580 s->cmd_state = pmu_state_cmd; 581 582 trace_pmu_debug_protocol_cmd(s->cmd, s->cmdlen, s->rsplen); 583 break; 584 585 case pmu_state_cmd: 586 if (!(ms->acr & SR_OUT)) { 587 trace_pmu_debug_protocol_string("protocol error! " 588 "state cmd, ACR reading"); 589 break; 590 } 591 592 if (s->cmdlen == -1) { 593 trace_pmu_debug_protocol_cmdlen(ms->sr); 594 595 s->cmdlen = ms->sr; 596 if (s->cmdlen > sizeof(s->cmd_buf)) { 597 trace_pmu_debug_protocol_cmd_toobig(s->cmdlen); 598 } 599 } else if (s->cmd_buf_pos < sizeof(s->cmd_buf)) { 600 s->cmd_buf[s->cmd_buf_pos++] = ms->sr; 601 } 602 603 via_set_sr_int(s); 604 break; 605 606 case pmu_state_rsp: 607 if (ms->acr & SR_OUT) { 608 trace_pmu_debug_protocol_string("protocol error! " 609 "state resp, ACR writing"); 610 break; 611 } 612 613 if (s->rsplen == -1) { 614 trace_pmu_debug_protocol_cmd_send_resp_size(s->cmd_rsp_sz); 615 616 ms->sr = s->cmd_rsp_sz; 617 s->rsplen = s->cmd_rsp_sz; 618 } else if (s->cmd_rsp_pos < s->cmd_rsp_sz) { 619 trace_pmu_debug_protocol_cmd_send_resp(s->cmd_rsp_pos, s->rsplen); 620 621 ms->sr = s->cmd_rsp[s->cmd_rsp_pos++]; 622 } 623 624 via_set_sr_int(s); 625 break; 626 } 627 628 /* Check for state completion */ 629 if (s->cmd_state == pmu_state_cmd && s->cmdlen == s->cmd_buf_pos) { 630 trace_pmu_debug_protocol_string("Command reception complete, " 631 "dispatching..."); 632 633 pmu_dispatch_cmd(s); 634 s->cmd_state = pmu_state_rsp; 635 } 636 637 if (s->cmd_state == pmu_state_rsp && s->rsplen == s->cmd_rsp_pos) { 638 trace_pmu_debug_protocol_cmd_resp_complete(ms->ier); 639 640 s->cmd_state = pmu_state_idle; 641 } 642 } 643 644 static uint64_t mos6522_pmu_read(void *opaque, hwaddr addr, unsigned size) 645 { 646 PMUState *s = opaque; 647 MOS6522PMUState *mps = &s->mos6522_pmu; 648 MOS6522State *ms = MOS6522(mps); 649 650 addr = (addr >> 9) & 0xf; 651 return mos6522_read(ms, addr, size); 652 } 653 654 static void mos6522_pmu_write(void *opaque, hwaddr addr, uint64_t val, 655 unsigned size) 656 { 657 PMUState *s = opaque; 658 MOS6522PMUState *mps = &s->mos6522_pmu; 659 MOS6522State *ms = MOS6522(mps); 660 661 addr = (addr >> 9) & 0xf; 662 mos6522_write(ms, addr, val, size); 663 } 664 665 static const MemoryRegionOps mos6522_pmu_ops = { 666 .read = mos6522_pmu_read, 667 .write = mos6522_pmu_write, 668 .endianness = DEVICE_BIG_ENDIAN, 669 .impl = { 670 .min_access_size = 1, 671 .max_access_size = 1, 672 }, 673 }; 674 675 static bool pmu_adb_state_needed(void *opaque) 676 { 677 PMUState *s = opaque; 678 679 return s->has_adb; 680 } 681 682 static const VMStateDescription vmstate_pmu_adb = { 683 .name = "pmu/adb", 684 .version_id = 0, 685 .minimum_version_id = 0, 686 .needed = pmu_adb_state_needed, 687 .fields = (VMStateField[]) { 688 VMSTATE_UINT16(adb_poll_mask, PMUState), 689 VMSTATE_TIMER_PTR(adb_poll_timer, PMUState), 690 VMSTATE_UINT8(adb_reply_size, PMUState), 691 VMSTATE_BUFFER(adb_reply, PMUState), 692 VMSTATE_END_OF_LIST() 693 } 694 }; 695 696 static const VMStateDescription vmstate_pmu = { 697 .name = "pmu", 698 .version_id = 0, 699 .minimum_version_id = 0, 700 .fields = (VMStateField[]) { 701 VMSTATE_STRUCT(mos6522_pmu.parent_obj, PMUState, 0, vmstate_mos6522, 702 MOS6522State), 703 VMSTATE_UINT8(last_b, PMUState), 704 VMSTATE_UINT8(cmd, PMUState), 705 VMSTATE_UINT32(cmdlen, PMUState), 706 VMSTATE_UINT32(rsplen, PMUState), 707 VMSTATE_UINT8(cmd_buf_pos, PMUState), 708 VMSTATE_BUFFER(cmd_buf, PMUState), 709 VMSTATE_UINT8(cmd_rsp_pos, PMUState), 710 VMSTATE_UINT8(cmd_rsp_sz, PMUState), 711 VMSTATE_BUFFER(cmd_rsp, PMUState), 712 VMSTATE_UINT8(intbits, PMUState), 713 VMSTATE_UINT8(intmask, PMUState), 714 VMSTATE_UINT8(autopoll_rate_ms, PMUState), 715 VMSTATE_UINT8(autopoll_mask, PMUState), 716 VMSTATE_UINT32(tick_offset, PMUState), 717 VMSTATE_TIMER_PTR(one_sec_timer, PMUState), 718 VMSTATE_INT64(one_sec_target, PMUState), 719 VMSTATE_END_OF_LIST() 720 }, 721 .subsections = (const VMStateDescription * []) { 722 &vmstate_pmu_adb, 723 } 724 }; 725 726 static void pmu_reset(DeviceState *dev) 727 { 728 PMUState *s = VIA_PMU(dev); 729 730 /* OpenBIOS needs to do this? MacOS 9 needs it */ 731 s->intmask = PMU_INT_ADB | PMU_INT_TICK; 732 s->intbits = 0; 733 734 s->cmd_state = pmu_state_idle; 735 s->autopoll_mask = 0; 736 } 737 738 static void pmu_realize(DeviceState *dev, Error **errp) 739 { 740 PMUState *s = VIA_PMU(dev); 741 SysBusDevice *sbd; 742 MOS6522State *ms; 743 DeviceState *d; 744 struct tm tm; 745 746 /* Pass IRQ from 6522 */ 747 d = DEVICE(&s->mos6522_pmu); 748 ms = MOS6522(d); 749 sbd = SYS_BUS_DEVICE(s); 750 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(ms)); 751 752 qemu_get_timedate(&tm, 0); 753 s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; 754 s->one_sec_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, pmu_one_sec_timer, s); 755 s->one_sec_target = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000; 756 timer_mod(s->one_sec_timer, s->one_sec_target); 757 758 if (s->has_adb) { 759 qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS, 760 DEVICE(dev), "adb.0"); 761 s->adb_poll_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, pmu_adb_poll, s); 762 s->adb_poll_mask = 0xffff; 763 s->autopoll_rate_ms = 20; 764 } 765 } 766 767 static void pmu_init(Object *obj) 768 { 769 SysBusDevice *d = SYS_BUS_DEVICE(obj); 770 PMUState *s = VIA_PMU(obj); 771 772 object_property_add_link(obj, "gpio", TYPE_MACIO_GPIO, 773 (Object **) &s->gpio, 774 qdev_prop_allow_set_link_before_realize, 775 0, NULL); 776 777 sysbus_init_child_obj(obj, "mos6522-pmu", &s->mos6522_pmu, 778 sizeof(s->mos6522_pmu), TYPE_MOS6522_PMU); 779 780 memory_region_init_io(&s->mem, obj, &mos6522_pmu_ops, s, "via-pmu", 781 0x2000); 782 sysbus_init_mmio(d, &s->mem); 783 } 784 785 static Property pmu_properties[] = { 786 DEFINE_PROP_BOOL("has-adb", PMUState, has_adb, true), 787 DEFINE_PROP_END_OF_LIST() 788 }; 789 790 static void pmu_class_init(ObjectClass *oc, void *data) 791 { 792 DeviceClass *dc = DEVICE_CLASS(oc); 793 794 dc->realize = pmu_realize; 795 dc->reset = pmu_reset; 796 dc->vmsd = &vmstate_pmu; 797 dc->props = pmu_properties; 798 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 799 } 800 801 static const TypeInfo pmu_type_info = { 802 .name = TYPE_VIA_PMU, 803 .parent = TYPE_SYS_BUS_DEVICE, 804 .instance_size = sizeof(PMUState), 805 .instance_init = pmu_init, 806 .class_init = pmu_class_init, 807 }; 808 809 static void mos6522_pmu_portB_write(MOS6522State *s) 810 { 811 MOS6522PMUState *mps = container_of(s, MOS6522PMUState, parent_obj); 812 PMUState *ps = container_of(mps, PMUState, mos6522_pmu); 813 814 if ((s->pcr & 0xe0) == 0x20 || (s->pcr & 0xe0) == 0x60) { 815 s->ifr &= ~CB2_INT; 816 } 817 s->ifr &= ~CB1_INT; 818 819 via_update_irq(ps); 820 pmu_update(ps); 821 } 822 823 static void mos6522_pmu_portA_write(MOS6522State *s) 824 { 825 MOS6522PMUState *mps = container_of(s, MOS6522PMUState, parent_obj); 826 PMUState *ps = container_of(mps, PMUState, mos6522_pmu); 827 828 if ((s->pcr & 0x0e) == 0x02 || (s->pcr & 0x0e) == 0x06) { 829 s->ifr &= ~CA2_INT; 830 } 831 s->ifr &= ~CA1_INT; 832 833 via_update_irq(ps); 834 } 835 836 static void mos6522_pmu_reset(DeviceState *dev) 837 { 838 MOS6522State *ms = MOS6522(dev); 839 MOS6522PMUState *mps = container_of(ms, MOS6522PMUState, parent_obj); 840 PMUState *s = container_of(mps, PMUState, mos6522_pmu); 841 MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(ms); 842 843 mdc->parent_reset(dev); 844 845 ms->timers[0].frequency = VIA_TIMER_FREQ; 846 ms->timers[1].frequency = (SCALE_US * 6000) / 4700; 847 848 s->last_b = ms->b = TACK | TREQ; 849 } 850 851 static void mos6522_pmu_class_init(ObjectClass *oc, void *data) 852 { 853 DeviceClass *dc = DEVICE_CLASS(oc); 854 MOS6522DeviceClass *mdc = MOS6522_DEVICE_CLASS(oc); 855 856 dc->reset = mos6522_pmu_reset; 857 mdc->portB_write = mos6522_pmu_portB_write; 858 mdc->portA_write = mos6522_pmu_portA_write; 859 } 860 861 static const TypeInfo mos6522_pmu_type_info = { 862 .name = TYPE_MOS6522_PMU, 863 .parent = TYPE_MOS6522, 864 .instance_size = sizeof(MOS6522PMUState), 865 .class_init = mos6522_pmu_class_init, 866 }; 867 868 static void pmu_register_types(void) 869 { 870 type_register_static(&pmu_type_info); 871 type_register_static(&mos6522_pmu_type_info); 872 } 873 874 type_init(pmu_register_types) 875