1 /* 2 * QEMU PowerMac PMU device support 3 * 4 * Copyright (c) 2016 Benjamin Herrenschmidt, IBM Corp. 5 * Copyright (c) 2018 Mark Cave-Ayland 6 * 7 * Based on the CUDA device by: 8 * 9 * Copyright (c) 2004-2007 Fabrice Bellard 10 * Copyright (c) 2007 Jocelyn Mayer 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "hw/qdev-properties.h" 33 #include "migration/vmstate.h" 34 #include "hw/irq.h" 35 #include "hw/misc/macio/pmu.h" 36 #include "qapi/error.h" 37 #include "qemu/timer.h" 38 #include "sysemu/runstate.h" 39 #include "sysemu/rtc.h" 40 #include "qapi/error.h" 41 #include "qemu/cutils.h" 42 #include "qemu/log.h" 43 #include "qemu/module.h" 44 #include "trace.h" 45 46 47 /* Bits in B data register: all active low */ 48 #define TACK 0x08 /* Transfer request (input) */ 49 #define TREQ 0x10 /* Transfer acknowledge (output) */ 50 51 /* PMU returns time_t's offset from Jan 1, 1904, not 1970 */ 52 #define RTC_OFFSET 2082844800 53 54 #define VIA_TIMER_FREQ (4700000 / 6) 55 56 static void via_set_sr_int(void *opaque) 57 { 58 PMUState *s = opaque; 59 MOS6522PMUState *mps = MOS6522_PMU(&s->mos6522_pmu); 60 MOS6522State *ms = MOS6522(mps); 61 qemu_irq irq = qdev_get_gpio_in(DEVICE(ms), SR_INT_BIT); 62 63 qemu_set_irq(irq, 1); 64 } 65 66 static void pmu_update_extirq(PMUState *s) 67 { 68 if ((s->intbits & s->intmask) != 0) { 69 macio_set_gpio(s->gpio, 1, false); 70 } else { 71 macio_set_gpio(s->gpio, 1, true); 72 } 73 } 74 75 static void pmu_adb_poll(void *opaque) 76 { 77 PMUState *s = opaque; 78 ADBBusState *adb_bus = &s->adb_bus; 79 int olen; 80 81 if (!(s->intbits & PMU_INT_ADB)) { 82 olen = adb_poll(adb_bus, s->adb_reply, adb_bus->autopoll_mask); 83 trace_pmu_adb_poll(olen); 84 85 if (olen > 0) { 86 s->adb_reply_size = olen; 87 s->intbits |= PMU_INT_ADB | PMU_INT_ADB_AUTO; 88 pmu_update_extirq(s); 89 } 90 } 91 } 92 93 static void pmu_one_sec_timer(void *opaque) 94 { 95 PMUState *s = opaque; 96 97 trace_pmu_one_sec_timer(); 98 99 s->intbits |= PMU_INT_TICK; 100 pmu_update_extirq(s); 101 s->one_sec_target += 1000; 102 103 timer_mod(s->one_sec_timer, s->one_sec_target); 104 } 105 106 static void pmu_cmd_int_ack(PMUState *s, 107 const uint8_t *in_data, uint8_t in_len, 108 uint8_t *out_data, uint8_t *out_len) 109 { 110 if (in_len != 0) { 111 qemu_log_mask(LOG_GUEST_ERROR, 112 "PMU: INT_ACK command, invalid len: %d want: 0\n", 113 in_len); 114 return; 115 } 116 117 /* Make appropriate reply packet */ 118 if (s->intbits & PMU_INT_ADB) { 119 if (!s->adb_reply_size) { 120 qemu_log_mask(LOG_GUEST_ERROR, 121 "Odd, PMU_INT_ADB set with no reply in buffer\n"); 122 } 123 124 memcpy(out_data + 1, s->adb_reply, s->adb_reply_size); 125 out_data[0] = s->intbits & (PMU_INT_ADB | PMU_INT_ADB_AUTO); 126 *out_len = s->adb_reply_size + 1; 127 s->intbits &= ~(PMU_INT_ADB | PMU_INT_ADB_AUTO); 128 s->adb_reply_size = 0; 129 } else { 130 out_data[0] = s->intbits; 131 s->intbits = 0; 132 *out_len = 1; 133 } 134 135 pmu_update_extirq(s); 136 } 137 138 static void pmu_cmd_set_int_mask(PMUState *s, 139 const uint8_t *in_data, uint8_t in_len, 140 uint8_t *out_data, uint8_t *out_len) 141 { 142 if (in_len != 1) { 143 qemu_log_mask(LOG_GUEST_ERROR, 144 "PMU: SET_INT_MASK command, invalid len: %d want: 1\n", 145 in_len); 146 return; 147 } 148 149 trace_pmu_cmd_set_int_mask(s->intmask); 150 s->intmask = in_data[0]; 151 152 pmu_update_extirq(s); 153 } 154 155 static void pmu_cmd_set_adb_autopoll(PMUState *s, uint16_t mask) 156 { 157 ADBBusState *adb_bus = &s->adb_bus; 158 159 trace_pmu_cmd_set_adb_autopoll(mask); 160 161 if (mask) { 162 adb_set_autopoll_mask(adb_bus, mask); 163 adb_set_autopoll_enabled(adb_bus, true); 164 } else { 165 adb_set_autopoll_enabled(adb_bus, false); 166 } 167 } 168 169 static void pmu_cmd_adb(PMUState *s, 170 const uint8_t *in_data, uint8_t in_len, 171 uint8_t *out_data, uint8_t *out_len) 172 { 173 int len, adblen; 174 uint8_t adb_cmd[255]; 175 176 if (in_len < 2) { 177 qemu_log_mask(LOG_GUEST_ERROR, 178 "PMU: ADB PACKET, invalid len: %d want at least 2\n", 179 in_len); 180 return; 181 } 182 183 *out_len = 0; 184 185 if (!s->has_adb) { 186 trace_pmu_cmd_adb_nobus(); 187 return; 188 } 189 190 /* Set autopoll is a special form of the command */ 191 if (in_data[0] == 0 && in_data[1] == 0x86) { 192 uint16_t mask = in_data[2]; 193 mask = (mask << 8) | in_data[3]; 194 if (in_len != 4) { 195 qemu_log_mask(LOG_GUEST_ERROR, 196 "PMU: ADB Autopoll requires 4 bytes, got %d\n", 197 in_len); 198 return; 199 } 200 201 pmu_cmd_set_adb_autopoll(s, mask); 202 return; 203 } 204 205 trace_pmu_cmd_adb_request(in_len, in_data[0], in_data[1], in_data[2], 206 in_data[3], in_data[4]); 207 208 *out_len = 0; 209 210 /* Check ADB len */ 211 adblen = in_data[2]; 212 if (adblen > (in_len - 3)) { 213 qemu_log_mask(LOG_GUEST_ERROR, 214 "PMU: ADB len is %d > %d (in_len -3)...erroring\n", 215 adblen, in_len - 3); 216 len = -1; 217 } else if (adblen > 252) { 218 qemu_log_mask(LOG_GUEST_ERROR, "PMU: ADB command too big!\n"); 219 len = -1; 220 } else { 221 /* Format command */ 222 adb_cmd[0] = in_data[0]; 223 memcpy(&adb_cmd[1], &in_data[3], in_len - 3); 224 len = adb_request(&s->adb_bus, s->adb_reply + 2, adb_cmd, in_len - 2); 225 226 trace_pmu_cmd_adb_reply(len); 227 } 228 229 if (len > 0) { 230 /* XXX Check this */ 231 s->adb_reply_size = len + 2; 232 s->adb_reply[0] = 0x01; 233 s->adb_reply[1] = len; 234 } else { 235 /* XXX Check this */ 236 s->adb_reply_size = 1; 237 s->adb_reply[0] = 0x00; 238 } 239 240 s->intbits |= PMU_INT_ADB; 241 pmu_update_extirq(s); 242 } 243 244 static void pmu_cmd_adb_poll_off(PMUState *s, 245 const uint8_t *in_data, uint8_t in_len, 246 uint8_t *out_data, uint8_t *out_len) 247 { 248 ADBBusState *adb_bus = &s->adb_bus; 249 250 if (in_len != 0) { 251 qemu_log_mask(LOG_GUEST_ERROR, 252 "PMU: ADB POLL OFF command, invalid len: %d want: 0\n", 253 in_len); 254 return; 255 } 256 257 if (s->has_adb) { 258 adb_set_autopoll_enabled(adb_bus, false); 259 } 260 } 261 262 static void pmu_cmd_shutdown(PMUState *s, 263 const uint8_t *in_data, uint8_t in_len, 264 uint8_t *out_data, uint8_t *out_len) 265 { 266 if (in_len != 4) { 267 qemu_log_mask(LOG_GUEST_ERROR, 268 "PMU: SHUTDOWN command, invalid len: %d want: 4\n", 269 in_len); 270 return; 271 } 272 273 *out_len = 1; 274 out_data[0] = 0; 275 276 if (in_data[0] != 'M' || in_data[1] != 'A' || in_data[2] != 'T' || 277 in_data[3] != 'T') { 278 279 qemu_log_mask(LOG_GUEST_ERROR, 280 "PMU: SHUTDOWN command, Bad MATT signature\n"); 281 return; 282 } 283 284 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 285 } 286 287 static void pmu_cmd_reset(PMUState *s, 288 const uint8_t *in_data, uint8_t in_len, 289 uint8_t *out_data, uint8_t *out_len) 290 { 291 if (in_len != 0) { 292 qemu_log_mask(LOG_GUEST_ERROR, 293 "PMU: RESET command, invalid len: %d want: 0\n", 294 in_len); 295 return; 296 } 297 298 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 299 } 300 301 static void pmu_cmd_get_rtc(PMUState *s, 302 const uint8_t *in_data, uint8_t in_len, 303 uint8_t *out_data, uint8_t *out_len) 304 { 305 uint32_t ti; 306 307 if (in_len != 0) { 308 qemu_log_mask(LOG_GUEST_ERROR, 309 "PMU: GET_RTC command, invalid len: %d want: 0\n", 310 in_len); 311 return; 312 } 313 314 ti = s->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) 315 / NANOSECONDS_PER_SECOND); 316 out_data[0] = ti >> 24; 317 out_data[1] = ti >> 16; 318 out_data[2] = ti >> 8; 319 out_data[3] = ti; 320 *out_len = 4; 321 } 322 323 static void pmu_cmd_set_rtc(PMUState *s, 324 const uint8_t *in_data, uint8_t in_len, 325 uint8_t *out_data, uint8_t *out_len) 326 { 327 uint32_t ti; 328 329 if (in_len != 4) { 330 qemu_log_mask(LOG_GUEST_ERROR, 331 "PMU: SET_RTC command, invalid len: %d want: 4\n", 332 in_len); 333 return; 334 } 335 336 ti = (((uint32_t)in_data[0]) << 24) + (((uint32_t)in_data[1]) << 16) 337 + (((uint32_t)in_data[2]) << 8) + in_data[3]; 338 339 s->tick_offset = ti - (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) 340 / NANOSECONDS_PER_SECOND); 341 } 342 343 static void pmu_cmd_system_ready(PMUState *s, 344 const uint8_t *in_data, uint8_t in_len, 345 uint8_t *out_data, uint8_t *out_len) 346 { 347 /* Do nothing */ 348 } 349 350 static void pmu_cmd_get_version(PMUState *s, 351 const uint8_t *in_data, uint8_t in_len, 352 uint8_t *out_data, uint8_t *out_len) 353 { 354 *out_len = 1; 355 *out_data = 1; /* ??? Check what Apple does */ 356 } 357 358 static void pmu_cmd_power_events(PMUState *s, 359 const uint8_t *in_data, uint8_t in_len, 360 uint8_t *out_data, uint8_t *out_len) 361 { 362 if (in_len < 1) { 363 qemu_log_mask(LOG_GUEST_ERROR, 364 "PMU: POWER EVENTS command, invalid len %d, want at least 1\n", 365 in_len); 366 return; 367 } 368 369 switch (in_data[0]) { 370 /* Dummies for now */ 371 case PMU_PWR_GET_POWERUP_EVENTS: 372 *out_len = 2; 373 out_data[0] = 0; 374 out_data[1] = 0; 375 break; 376 case PMU_PWR_SET_POWERUP_EVENTS: 377 case PMU_PWR_CLR_POWERUP_EVENTS: 378 break; 379 case PMU_PWR_GET_WAKEUP_EVENTS: 380 *out_len = 2; 381 out_data[0] = 0; 382 out_data[1] = 0; 383 break; 384 case PMU_PWR_SET_WAKEUP_EVENTS: 385 case PMU_PWR_CLR_WAKEUP_EVENTS: 386 break; 387 default: 388 qemu_log_mask(LOG_GUEST_ERROR, 389 "PMU: POWER EVENTS unknown subcommand 0x%02x\n", 390 in_data[0]); 391 } 392 } 393 394 static void pmu_cmd_get_cover(PMUState *s, 395 const uint8_t *in_data, uint8_t in_len, 396 uint8_t *out_data, uint8_t *out_len) 397 { 398 /* Not 100% sure here, will have to check what a real Mac 399 * returns other than byte 0 bit 0 is LID closed on laptops 400 */ 401 *out_len = 1; 402 *out_data = 0x00; 403 } 404 405 static void pmu_cmd_download_status(PMUState *s, 406 const uint8_t *in_data, uint8_t in_len, 407 uint8_t *out_data, uint8_t *out_len) 408 { 409 /* This has to do with PMU firmware updates as far as I can tell. 410 * 411 * We return 0x62 which is what OpenPMU expects 412 */ 413 *out_len = 1; 414 *out_data = 0x62; 415 } 416 417 static void pmu_cmd_read_pmu_ram(PMUState *s, 418 const uint8_t *in_data, uint8_t in_len, 419 uint8_t *out_data, uint8_t *out_len) 420 { 421 if (in_len < 3) { 422 qemu_log_mask(LOG_GUEST_ERROR, 423 "PMU: READ_PMU_RAM command, invalid len %d, expected 3\n", 424 in_len); 425 return; 426 } 427 428 qemu_log_mask(LOG_GUEST_ERROR, 429 "PMU: Unsupported READ_PMU_RAM, args: %02x %02x %02x\n", 430 in_data[0], in_data[1], in_data[2]); 431 432 *out_len = 0; 433 } 434 435 /* description of commands */ 436 typedef struct PMUCmdHandler { 437 uint8_t command; 438 const char *name; 439 void (*handler)(PMUState *s, 440 const uint8_t *in_args, uint8_t in_len, 441 uint8_t *out_args, uint8_t *out_len); 442 } PMUCmdHandler; 443 444 static const PMUCmdHandler PMUCmdHandlers[] = { 445 { PMU_INT_ACK, "INT ACK", pmu_cmd_int_ack }, 446 { PMU_SET_INTR_MASK, "SET INT MASK", pmu_cmd_set_int_mask }, 447 { PMU_ADB_CMD, "ADB COMMAND", pmu_cmd_adb }, 448 { PMU_ADB_POLL_OFF, "ADB POLL OFF", pmu_cmd_adb_poll_off }, 449 { PMU_RESET, "REBOOT", pmu_cmd_reset }, 450 { PMU_SHUTDOWN, "SHUTDOWN", pmu_cmd_shutdown }, 451 { PMU_READ_RTC, "GET RTC", pmu_cmd_get_rtc }, 452 { PMU_SET_RTC, "SET RTC", pmu_cmd_set_rtc }, 453 { PMU_SYSTEM_READY, "SYSTEM READY", pmu_cmd_system_ready }, 454 { PMU_GET_VERSION, "GET VERSION", pmu_cmd_get_version }, 455 { PMU_POWER_EVENTS, "POWER EVENTS", pmu_cmd_power_events }, 456 { PMU_GET_COVER, "GET_COVER", pmu_cmd_get_cover }, 457 { PMU_DOWNLOAD_STATUS, "DOWNLOAD STATUS", pmu_cmd_download_status }, 458 { PMU_READ_PMU_RAM, "READ PMGR RAM", pmu_cmd_read_pmu_ram }, 459 }; 460 461 static void pmu_dispatch_cmd(PMUState *s) 462 { 463 unsigned int i; 464 465 /* No response by default */ 466 s->cmd_rsp_sz = 0; 467 468 for (i = 0; i < ARRAY_SIZE(PMUCmdHandlers); i++) { 469 const PMUCmdHandler *desc = &PMUCmdHandlers[i]; 470 471 if (desc->command != s->cmd) { 472 continue; 473 } 474 475 trace_pmu_dispatch_cmd(desc->name); 476 desc->handler(s, s->cmd_buf, s->cmd_buf_pos, 477 s->cmd_rsp, &s->cmd_rsp_sz); 478 479 if (s->rsplen != -1 && s->rsplen != s->cmd_rsp_sz) { 480 trace_pmu_debug_protocol_string("QEMU internal cmd resp mismatch!"); 481 } else { 482 trace_pmu_debug_protocol_resp_size(s->cmd_rsp_sz); 483 } 484 485 return; 486 } 487 488 trace_pmu_dispatch_unknown_cmd(s->cmd); 489 490 /* Manufacture fake response with 0's */ 491 if (s->rsplen == -1) { 492 s->cmd_rsp_sz = 0; 493 } else { 494 s->cmd_rsp_sz = s->rsplen; 495 memset(s->cmd_rsp, 0, s->rsplen); 496 } 497 } 498 499 static void pmu_update(PMUState *s) 500 { 501 MOS6522PMUState *mps = &s->mos6522_pmu; 502 MOS6522State *ms = MOS6522(mps); 503 ADBBusState *adb_bus = &s->adb_bus; 504 505 /* Only react to changes in reg B */ 506 if (ms->b == s->last_b) { 507 return; 508 } 509 s->last_b = ms->b; 510 511 /* Check the TREQ / TACK state */ 512 switch (ms->b & (TREQ | TACK)) { 513 case TREQ: 514 /* This is an ack release, handle it and bail out */ 515 ms->b |= TACK; 516 s->last_b = ms->b; 517 518 trace_pmu_debug_protocol_string("handshake: TREQ high, setting TACK"); 519 return; 520 case TACK: 521 /* This is a valid request, handle below */ 522 break; 523 case TREQ | TACK: 524 /* This is an idle state */ 525 return; 526 default: 527 /* Invalid state, log and ignore */ 528 trace_pmu_debug_protocol_error(ms->b); 529 return; 530 } 531 532 /* If we wanted to handle commands asynchronously, this is where 533 * we would delay the clearing of TACK until we are ready to send 534 * the response 535 */ 536 537 /* We have a request, handshake TACK so we don't stay in 538 * an invalid state. If we were concurrent with the OS we 539 * should only do this after we grabbed the SR but that isn't 540 * a problem here. 541 */ 542 543 trace_pmu_debug_protocol_clear_treq(s->cmd_state); 544 545 ms->b &= ~TACK; 546 s->last_b = ms->b; 547 548 /* Act according to state */ 549 switch (s->cmd_state) { 550 case pmu_state_idle: 551 if (!(ms->acr & SR_OUT)) { 552 trace_pmu_debug_protocol_string("protocol error! " 553 "state idle, ACR reading"); 554 break; 555 } 556 557 s->cmd = ms->sr; 558 via_set_sr_int(s); 559 s->cmdlen = pmu_data_len[s->cmd][0]; 560 s->rsplen = pmu_data_len[s->cmd][1]; 561 s->cmd_buf_pos = 0; 562 s->cmd_rsp_pos = 0; 563 s->cmd_state = pmu_state_cmd; 564 565 adb_autopoll_block(adb_bus); 566 trace_pmu_debug_protocol_cmd(s->cmd, s->cmdlen, s->rsplen); 567 break; 568 569 case pmu_state_cmd: 570 if (!(ms->acr & SR_OUT)) { 571 trace_pmu_debug_protocol_string("protocol error! " 572 "state cmd, ACR reading"); 573 break; 574 } 575 576 if (s->cmdlen == -1) { 577 trace_pmu_debug_protocol_cmdlen(ms->sr); 578 579 s->cmdlen = ms->sr; 580 if (s->cmdlen > sizeof(s->cmd_buf)) { 581 trace_pmu_debug_protocol_cmd_toobig(s->cmdlen); 582 } 583 } else if (s->cmd_buf_pos < sizeof(s->cmd_buf)) { 584 s->cmd_buf[s->cmd_buf_pos++] = ms->sr; 585 } 586 587 via_set_sr_int(s); 588 break; 589 590 case pmu_state_rsp: 591 if (ms->acr & SR_OUT) { 592 trace_pmu_debug_protocol_string("protocol error! " 593 "state resp, ACR writing"); 594 break; 595 } 596 597 if (s->rsplen == -1) { 598 trace_pmu_debug_protocol_cmd_send_resp_size(s->cmd_rsp_sz); 599 600 ms->sr = s->cmd_rsp_sz; 601 s->rsplen = s->cmd_rsp_sz; 602 } else if (s->cmd_rsp_pos < s->cmd_rsp_sz) { 603 trace_pmu_debug_protocol_cmd_send_resp(s->cmd_rsp_pos, s->rsplen); 604 605 ms->sr = s->cmd_rsp[s->cmd_rsp_pos++]; 606 } 607 608 via_set_sr_int(s); 609 break; 610 } 611 612 /* Check for state completion */ 613 if (s->cmd_state == pmu_state_cmd && s->cmdlen == s->cmd_buf_pos) { 614 trace_pmu_debug_protocol_string("Command reception complete, " 615 "dispatching..."); 616 617 pmu_dispatch_cmd(s); 618 s->cmd_state = pmu_state_rsp; 619 } 620 621 if (s->cmd_state == pmu_state_rsp && s->rsplen == s->cmd_rsp_pos) { 622 trace_pmu_debug_protocol_cmd_resp_complete(ms->ier); 623 624 adb_autopoll_unblock(adb_bus); 625 s->cmd_state = pmu_state_idle; 626 } 627 } 628 629 static uint64_t mos6522_pmu_read(void *opaque, hwaddr addr, unsigned size) 630 { 631 PMUState *s = opaque; 632 MOS6522PMUState *mps = &s->mos6522_pmu; 633 MOS6522State *ms = MOS6522(mps); 634 635 addr = (addr >> 9) & 0xf; 636 return mos6522_read(ms, addr, size); 637 } 638 639 static void mos6522_pmu_write(void *opaque, hwaddr addr, uint64_t val, 640 unsigned size) 641 { 642 PMUState *s = opaque; 643 MOS6522PMUState *mps = &s->mos6522_pmu; 644 MOS6522State *ms = MOS6522(mps); 645 646 addr = (addr >> 9) & 0xf; 647 mos6522_write(ms, addr, val, size); 648 } 649 650 static const MemoryRegionOps mos6522_pmu_ops = { 651 .read = mos6522_pmu_read, 652 .write = mos6522_pmu_write, 653 .endianness = DEVICE_BIG_ENDIAN, 654 .impl = { 655 .min_access_size = 1, 656 .max_access_size = 1, 657 }, 658 }; 659 660 static bool pmu_adb_state_needed(void *opaque) 661 { 662 PMUState *s = opaque; 663 664 return s->has_adb; 665 } 666 667 static const VMStateDescription vmstate_pmu_adb = { 668 .name = "pmu/adb", 669 .version_id = 1, 670 .minimum_version_id = 1, 671 .needed = pmu_adb_state_needed, 672 .fields = (VMStateField[]) { 673 VMSTATE_UINT8(adb_reply_size, PMUState), 674 VMSTATE_BUFFER(adb_reply, PMUState), 675 VMSTATE_END_OF_LIST() 676 } 677 }; 678 679 static const VMStateDescription vmstate_pmu = { 680 .name = "pmu", 681 .version_id = 1, 682 .minimum_version_id = 1, 683 .fields = (VMStateField[]) { 684 VMSTATE_STRUCT(mos6522_pmu.parent_obj, PMUState, 0, vmstate_mos6522, 685 MOS6522State), 686 VMSTATE_UINT8(last_b, PMUState), 687 VMSTATE_UINT8(cmd, PMUState), 688 VMSTATE_UINT32(cmdlen, PMUState), 689 VMSTATE_UINT32(rsplen, PMUState), 690 VMSTATE_UINT8(cmd_buf_pos, PMUState), 691 VMSTATE_BUFFER(cmd_buf, PMUState), 692 VMSTATE_UINT8(cmd_rsp_pos, PMUState), 693 VMSTATE_UINT8(cmd_rsp_sz, PMUState), 694 VMSTATE_BUFFER(cmd_rsp, PMUState), 695 VMSTATE_UINT8(intbits, PMUState), 696 VMSTATE_UINT8(intmask, PMUState), 697 VMSTATE_UINT32(tick_offset, PMUState), 698 VMSTATE_TIMER_PTR(one_sec_timer, PMUState), 699 VMSTATE_INT64(one_sec_target, PMUState), 700 VMSTATE_END_OF_LIST() 701 }, 702 .subsections = (const VMStateDescription * []) { 703 &vmstate_pmu_adb, 704 NULL 705 } 706 }; 707 708 static void pmu_reset(DeviceState *dev) 709 { 710 PMUState *s = VIA_PMU(dev); 711 712 /* OpenBIOS needs to do this? MacOS 9 needs it */ 713 s->intmask = PMU_INT_ADB | PMU_INT_TICK; 714 s->intbits = 0; 715 716 s->cmd_state = pmu_state_idle; 717 } 718 719 static void pmu_realize(DeviceState *dev, Error **errp) 720 { 721 PMUState *s = VIA_PMU(dev); 722 SysBusDevice *sbd; 723 ADBBusState *adb_bus = &s->adb_bus; 724 struct tm tm; 725 726 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mos6522_pmu), errp)) { 727 return; 728 } 729 730 /* Pass IRQ from 6522 */ 731 sbd = SYS_BUS_DEVICE(s); 732 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->mos6522_pmu)); 733 734 qemu_get_timedate(&tm, 0); 735 s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; 736 s->one_sec_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, pmu_one_sec_timer, s); 737 s->one_sec_target = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000; 738 timer_mod(s->one_sec_timer, s->one_sec_target); 739 740 if (s->has_adb) { 741 qbus_init(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS, 742 dev, "adb.0"); 743 adb_register_autopoll_callback(adb_bus, pmu_adb_poll, s); 744 } 745 } 746 747 static void pmu_init(Object *obj) 748 { 749 SysBusDevice *d = SYS_BUS_DEVICE(obj); 750 PMUState *s = VIA_PMU(obj); 751 752 object_property_add_link(obj, "gpio", TYPE_MACIO_GPIO, 753 (Object **) &s->gpio, 754 qdev_prop_allow_set_link_before_realize, 755 0); 756 757 object_initialize_child(obj, "mos6522-pmu", &s->mos6522_pmu, 758 TYPE_MOS6522_PMU); 759 760 memory_region_init_io(&s->mem, obj, &mos6522_pmu_ops, s, "via-pmu", 761 0x2000); 762 sysbus_init_mmio(d, &s->mem); 763 } 764 765 static Property pmu_properties[] = { 766 DEFINE_PROP_BOOL("has-adb", PMUState, has_adb, true), 767 DEFINE_PROP_END_OF_LIST() 768 }; 769 770 static void pmu_class_init(ObjectClass *oc, void *data) 771 { 772 DeviceClass *dc = DEVICE_CLASS(oc); 773 774 dc->realize = pmu_realize; 775 dc->reset = pmu_reset; 776 dc->vmsd = &vmstate_pmu; 777 device_class_set_props(dc, pmu_properties); 778 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 779 } 780 781 static const TypeInfo pmu_type_info = { 782 .name = TYPE_VIA_PMU, 783 .parent = TYPE_SYS_BUS_DEVICE, 784 .instance_size = sizeof(PMUState), 785 .instance_init = pmu_init, 786 .class_init = pmu_class_init, 787 }; 788 789 static void mos6522_pmu_portB_write(MOS6522State *s) 790 { 791 MOS6522PMUState *mps = container_of(s, MOS6522PMUState, parent_obj); 792 PMUState *ps = container_of(mps, PMUState, mos6522_pmu); 793 794 pmu_update(ps); 795 } 796 797 static void mos6522_pmu_reset_hold(Object *obj) 798 { 799 MOS6522State *ms = MOS6522(obj); 800 MOS6522PMUState *mps = container_of(ms, MOS6522PMUState, parent_obj); 801 PMUState *s = container_of(mps, PMUState, mos6522_pmu); 802 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); 803 804 if (mdc->parent_phases.hold) { 805 mdc->parent_phases.hold(obj); 806 } 807 808 ms->timers[0].frequency = VIA_TIMER_FREQ; 809 ms->timers[1].frequency = (SCALE_US * 6000) / 4700; 810 811 s->last_b = ms->b = TACK | TREQ; 812 } 813 814 static void mos6522_pmu_class_init(ObjectClass *oc, void *data) 815 { 816 ResettableClass *rc = RESETTABLE_CLASS(oc); 817 MOS6522DeviceClass *mdc = MOS6522_CLASS(oc); 818 819 resettable_class_set_parent_phases(rc, NULL, mos6522_pmu_reset_hold, 820 NULL, &mdc->parent_phases); 821 mdc->portB_write = mos6522_pmu_portB_write; 822 } 823 824 static const TypeInfo mos6522_pmu_type_info = { 825 .name = TYPE_MOS6522_PMU, 826 .parent = TYPE_MOS6522, 827 .instance_size = sizeof(MOS6522PMUState), 828 .class_init = mos6522_pmu_class_init, 829 }; 830 831 static void pmu_register_types(void) 832 { 833 type_register_static(&pmu_type_info); 834 type_register_static(&mos6522_pmu_type_info); 835 } 836 837 type_init(pmu_register_types) 838