1 /* 2 * PowerMac MacIO device emulation 3 * 4 * Copyright (c) 2005-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "qemu/module.h" 29 #include "hw/ppc/mac.h" 30 #include "hw/misc/macio/cuda.h" 31 #include "hw/pci/pci.h" 32 #include "hw/ppc/mac_dbdma.h" 33 #include "hw/qdev-properties.h" 34 #include "migration/vmstate.h" 35 #include "hw/char/escc.h" 36 #include "hw/misc/macio/macio.h" 37 #include "hw/intc/heathrow_pic.h" 38 #include "sysemu/sysemu.h" 39 #include "trace.h" 40 41 /* Note: this code is strongly inspirated from the corresponding code 42 * in PearPC */ 43 44 /* 45 * The mac-io has two interfaces to the ESCC. One is called "escc-legacy", 46 * while the other one is the normal, current ESCC interface. 47 * 48 * The magic below creates memory aliases to spawn the escc-legacy device 49 * purely by rerouting the respective registers to our escc region. This 50 * works because the only difference between the two memory regions is the 51 * register layout, not their semantics. 52 * 53 * Reference: ftp://ftp.software.ibm.com/rs6000/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf 54 */ 55 static void macio_escc_legacy_setup(MacIOState *s) 56 { 57 ESCCState *escc = ESCC(&s->escc); 58 SysBusDevice *sbd = SYS_BUS_DEVICE(escc); 59 MemoryRegion *escc_legacy = g_new(MemoryRegion, 1); 60 MemoryRegion *bar = &s->bar; 61 int i; 62 static const int maps[] = { 63 0x00, 0x00, /* Command B */ 64 0x02, 0x20, /* Command A */ 65 0x04, 0x10, /* Data B */ 66 0x06, 0x30, /* Data A */ 67 0x08, 0x40, /* Enhancement B */ 68 0x0A, 0x50, /* Enhancement A */ 69 0x80, 0x80, /* Recovery count */ 70 0x90, 0x90, /* Start A */ 71 0xa0, 0xa0, /* Start B */ 72 0xb0, 0xb0, /* Detect AB */ 73 }; 74 75 memory_region_init(escc_legacy, OBJECT(s), "escc-legacy", 256); 76 for (i = 0; i < ARRAY_SIZE(maps); i += 2) { 77 MemoryRegion *port = g_new(MemoryRegion, 1); 78 memory_region_init_alias(port, OBJECT(s), "escc-legacy-port", 79 sysbus_mmio_get_region(sbd, 0), 80 maps[i + 1], 0x2); 81 memory_region_add_subregion(escc_legacy, maps[i], port); 82 } 83 84 memory_region_add_subregion(bar, 0x12000, escc_legacy); 85 } 86 87 static void macio_bar_setup(MacIOState *s) 88 { 89 ESCCState *escc = ESCC(&s->escc); 90 SysBusDevice *sbd = SYS_BUS_DEVICE(escc); 91 MemoryRegion *bar = &s->bar; 92 93 memory_region_add_subregion(bar, 0x13000, sysbus_mmio_get_region(sbd, 0)); 94 macio_escc_legacy_setup(s); 95 } 96 97 static void macio_common_realize(PCIDevice *d, Error **errp) 98 { 99 MacIOState *s = MACIO(d); 100 SysBusDevice *sysbus_dev; 101 102 if (!qdev_realize(DEVICE(&s->dbdma), BUS(&s->macio_bus), errp)) { 103 return; 104 } 105 sysbus_dev = SYS_BUS_DEVICE(&s->dbdma); 106 memory_region_add_subregion(&s->bar, 0x08000, 107 sysbus_mmio_get_region(sysbus_dev, 0)); 108 109 qdev_prop_set_uint32(DEVICE(&s->escc), "disabled", 0); 110 qdev_prop_set_uint32(DEVICE(&s->escc), "frequency", ESCC_CLOCK); 111 qdev_prop_set_uint32(DEVICE(&s->escc), "it_shift", 4); 112 qdev_prop_set_uint32(DEVICE(&s->escc), "chnBtype", escc_serial); 113 qdev_prop_set_uint32(DEVICE(&s->escc), "chnAtype", escc_serial); 114 if (!qdev_realize(DEVICE(&s->escc), BUS(&s->macio_bus), errp)) { 115 return; 116 } 117 118 macio_bar_setup(s); 119 pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar); 120 } 121 122 static void macio_realize_ide(MacIOState *s, MACIOIDEState *ide, 123 qemu_irq irq0, qemu_irq irq1, int dmaid, 124 Error **errp) 125 { 126 SysBusDevice *sysbus_dev; 127 128 sysbus_dev = SYS_BUS_DEVICE(ide); 129 sysbus_connect_irq(sysbus_dev, 0, irq0); 130 sysbus_connect_irq(sysbus_dev, 1, irq1); 131 qdev_prop_set_uint32(DEVICE(ide), "channel", dmaid); 132 object_property_set_link(OBJECT(ide), "dbdma", OBJECT(&s->dbdma), 133 &error_abort); 134 macio_ide_register_dma(ide); 135 136 qdev_realize(DEVICE(ide), BUS(&s->macio_bus), errp); 137 } 138 139 static void macio_oldworld_realize(PCIDevice *d, Error **errp) 140 { 141 MacIOState *s = MACIO(d); 142 OldWorldMacIOState *os = OLDWORLD_MACIO(d); 143 DeviceState *pic_dev = DEVICE(os->pic); 144 Error *err = NULL; 145 SysBusDevice *sysbus_dev; 146 147 macio_common_realize(d, &err); 148 if (err) { 149 error_propagate(errp, err); 150 return; 151 } 152 153 qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency", 154 s->frequency); 155 if (!qdev_realize(DEVICE(&s->cuda), BUS(&s->macio_bus), errp)) { 156 return; 157 } 158 sysbus_dev = SYS_BUS_DEVICE(&s->cuda); 159 memory_region_add_subregion(&s->bar, 0x16000, 160 sysbus_mmio_get_region(sysbus_dev, 0)); 161 sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev, 162 OLDWORLD_CUDA_IRQ)); 163 164 sysbus_dev = SYS_BUS_DEVICE(&s->escc); 165 sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev, 166 OLDWORLD_ESCCB_IRQ)); 167 sysbus_connect_irq(sysbus_dev, 1, qdev_get_gpio_in(pic_dev, 168 OLDWORLD_ESCCA_IRQ)); 169 170 if (!qdev_realize(DEVICE(&os->nvram), BUS(&s->macio_bus), errp)) { 171 return; 172 } 173 sysbus_dev = SYS_BUS_DEVICE(&os->nvram); 174 memory_region_add_subregion(&s->bar, 0x60000, 175 sysbus_mmio_get_region(sysbus_dev, 0)); 176 pmac_format_nvram_partition(&os->nvram, os->nvram.size); 177 178 /* Heathrow PIC */ 179 sysbus_dev = SYS_BUS_DEVICE(os->pic); 180 memory_region_add_subregion(&s->bar, 0x0, 181 sysbus_mmio_get_region(sysbus_dev, 0)); 182 183 /* IDE buses */ 184 macio_realize_ide(s, &os->ide[0], 185 qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_IRQ), 186 qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_DMA_IRQ), 187 0x16, &err); 188 if (err) { 189 error_propagate(errp, err); 190 return; 191 } 192 193 macio_realize_ide(s, &os->ide[1], 194 qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_IRQ), 195 qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_DMA_IRQ), 196 0x1a, &err); 197 if (err) { 198 error_propagate(errp, err); 199 return; 200 } 201 } 202 203 static void macio_init_ide(MacIOState *s, MACIOIDEState *ide, int index) 204 { 205 gchar *name = g_strdup_printf("ide[%i]", index); 206 uint32_t addr = 0x1f000 + ((index + 1) * 0x1000); 207 208 object_initialize_child(OBJECT(s), name, ide, TYPE_MACIO_IDE); 209 qdev_prop_set_uint32(DEVICE(ide), "addr", addr); 210 memory_region_add_subregion(&s->bar, addr, &ide->mem); 211 g_free(name); 212 } 213 214 static void macio_oldworld_init(Object *obj) 215 { 216 MacIOState *s = MACIO(obj); 217 OldWorldMacIOState *os = OLDWORLD_MACIO(obj); 218 DeviceState *dev; 219 int i; 220 221 object_property_add_link(obj, "pic", TYPE_HEATHROW, 222 (Object **) &os->pic, 223 qdev_prop_allow_set_link_before_realize, 224 0); 225 226 object_initialize_child(OBJECT(s), "cuda", &s->cuda, TYPE_CUDA); 227 228 object_initialize_child(OBJECT(s), "nvram", &os->nvram, TYPE_MACIO_NVRAM); 229 dev = DEVICE(&os->nvram); 230 qdev_prop_set_uint32(dev, "size", 0x2000); 231 qdev_prop_set_uint32(dev, "it_shift", 4); 232 233 for (i = 0; i < 2; i++) { 234 macio_init_ide(s, &os->ide[i], i); 235 } 236 } 237 238 static void timer_write(void *opaque, hwaddr addr, uint64_t value, 239 unsigned size) 240 { 241 trace_macio_timer_write(addr, size, value); 242 } 243 244 static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size) 245 { 246 uint32_t value = 0; 247 uint64_t systime = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 248 uint64_t kltime; 249 250 kltime = muldiv64(systime, 4194300, NANOSECONDS_PER_SECOND * 4); 251 kltime = muldiv64(kltime, 18432000, 1048575); 252 253 switch (addr) { 254 case 0x38: 255 value = kltime; 256 break; 257 case 0x3c: 258 value = kltime >> 32; 259 break; 260 } 261 262 trace_macio_timer_read(addr, size, value); 263 return value; 264 } 265 266 static const MemoryRegionOps timer_ops = { 267 .read = timer_read, 268 .write = timer_write, 269 .endianness = DEVICE_LITTLE_ENDIAN, 270 }; 271 272 static void macio_newworld_realize(PCIDevice *d, Error **errp) 273 { 274 MacIOState *s = MACIO(d); 275 NewWorldMacIOState *ns = NEWWORLD_MACIO(d); 276 DeviceState *pic_dev = DEVICE(ns->pic); 277 Error *err = NULL; 278 SysBusDevice *sysbus_dev; 279 MemoryRegion *timer_memory = NULL; 280 281 macio_common_realize(d, &err); 282 if (err) { 283 error_propagate(errp, err); 284 return; 285 } 286 287 sysbus_dev = SYS_BUS_DEVICE(&s->escc); 288 sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev, 289 NEWWORLD_ESCCB_IRQ)); 290 sysbus_connect_irq(sysbus_dev, 1, qdev_get_gpio_in(pic_dev, 291 NEWWORLD_ESCCA_IRQ)); 292 293 /* OpenPIC */ 294 sysbus_dev = SYS_BUS_DEVICE(ns->pic); 295 memory_region_add_subregion(&s->bar, 0x40000, 296 sysbus_mmio_get_region(sysbus_dev, 0)); 297 298 /* IDE buses */ 299 macio_realize_ide(s, &ns->ide[0], 300 qdev_get_gpio_in(pic_dev, NEWWORLD_IDE0_IRQ), 301 qdev_get_gpio_in(pic_dev, NEWWORLD_IDE0_DMA_IRQ), 302 0x16, &err); 303 if (err) { 304 error_propagate(errp, err); 305 return; 306 } 307 308 macio_realize_ide(s, &ns->ide[1], 309 qdev_get_gpio_in(pic_dev, NEWWORLD_IDE1_IRQ), 310 qdev_get_gpio_in(pic_dev, NEWWORLD_IDE1_DMA_IRQ), 311 0x1a, &err); 312 if (err) { 313 error_propagate(errp, err); 314 return; 315 } 316 317 /* Timer */ 318 timer_memory = g_new(MemoryRegion, 1); 319 memory_region_init_io(timer_memory, OBJECT(s), &timer_ops, NULL, "timer", 320 0x1000); 321 memory_region_add_subregion(&s->bar, 0x15000, timer_memory); 322 323 if (ns->has_pmu) { 324 /* GPIOs */ 325 sysbus_dev = SYS_BUS_DEVICE(&ns->gpio); 326 object_property_set_link(OBJECT(&ns->gpio), "pic", OBJECT(pic_dev), 327 &error_abort); 328 memory_region_add_subregion(&s->bar, 0x50, 329 sysbus_mmio_get_region(sysbus_dev, 0)); 330 if (!qdev_realize(DEVICE(&ns->gpio), BUS(&s->macio_bus), errp)) { 331 return; 332 } 333 334 /* PMU */ 335 object_initialize_child(OBJECT(s), "pmu", &s->pmu, TYPE_VIA_PMU); 336 object_property_set_link(OBJECT(&s->pmu), "gpio", OBJECT(sysbus_dev), 337 &error_abort); 338 qdev_prop_set_bit(DEVICE(&s->pmu), "has-adb", ns->has_adb); 339 if (!qdev_realize(DEVICE(&s->pmu), BUS(&s->macio_bus), errp)) { 340 return; 341 } 342 sysbus_dev = SYS_BUS_DEVICE(&s->pmu); 343 sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev, 344 NEWWORLD_PMU_IRQ)); 345 memory_region_add_subregion(&s->bar, 0x16000, 346 sysbus_mmio_get_region(sysbus_dev, 0)); 347 } else { 348 object_unparent(OBJECT(&ns->gpio)); 349 350 /* CUDA */ 351 object_initialize_child(OBJECT(s), "cuda", &s->cuda, TYPE_CUDA); 352 qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency", 353 s->frequency); 354 355 if (!qdev_realize(DEVICE(&s->cuda), BUS(&s->macio_bus), errp)) { 356 return; 357 } 358 sysbus_dev = SYS_BUS_DEVICE(&s->cuda); 359 sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev, 360 NEWWORLD_CUDA_IRQ)); 361 memory_region_add_subregion(&s->bar, 0x16000, 362 sysbus_mmio_get_region(sysbus_dev, 0)); 363 } 364 } 365 366 static void macio_newworld_init(Object *obj) 367 { 368 MacIOState *s = MACIO(obj); 369 NewWorldMacIOState *ns = NEWWORLD_MACIO(obj); 370 int i; 371 372 object_property_add_link(obj, "pic", TYPE_OPENPIC, 373 (Object **) &ns->pic, 374 qdev_prop_allow_set_link_before_realize, 375 0); 376 377 object_initialize_child(OBJECT(s), "gpio", &ns->gpio, TYPE_MACIO_GPIO); 378 379 for (i = 0; i < 2; i++) { 380 macio_init_ide(s, &ns->ide[i], i); 381 } 382 } 383 384 static void macio_instance_init(Object *obj) 385 { 386 MacIOState *s = MACIO(obj); 387 388 memory_region_init(&s->bar, obj, "macio", 0x80000); 389 390 qbus_create_inplace(&s->macio_bus, sizeof(s->macio_bus), TYPE_MACIO_BUS, 391 DEVICE(obj), "macio.0"); 392 393 object_initialize_child(OBJECT(s), "dbdma", &s->dbdma, TYPE_MAC_DBDMA); 394 395 object_initialize_child(OBJECT(s), "escc", &s->escc, TYPE_ESCC); 396 } 397 398 static const VMStateDescription vmstate_macio_oldworld = { 399 .name = "macio-oldworld", 400 .version_id = 0, 401 .minimum_version_id = 0, 402 .fields = (VMStateField[]) { 403 VMSTATE_PCI_DEVICE(parent_obj.parent, OldWorldMacIOState), 404 VMSTATE_END_OF_LIST() 405 } 406 }; 407 408 static void macio_oldworld_class_init(ObjectClass *oc, void *data) 409 { 410 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(oc); 411 DeviceClass *dc = DEVICE_CLASS(oc); 412 413 pdc->realize = macio_oldworld_realize; 414 pdc->device_id = PCI_DEVICE_ID_APPLE_343S1201; 415 dc->vmsd = &vmstate_macio_oldworld; 416 } 417 418 static const VMStateDescription vmstate_macio_newworld = { 419 .name = "macio-newworld", 420 .version_id = 0, 421 .minimum_version_id = 0, 422 .fields = (VMStateField[]) { 423 VMSTATE_PCI_DEVICE(parent_obj.parent, NewWorldMacIOState), 424 VMSTATE_END_OF_LIST() 425 } 426 }; 427 428 static Property macio_newworld_properties[] = { 429 DEFINE_PROP_BOOL("has-pmu", NewWorldMacIOState, has_pmu, false), 430 DEFINE_PROP_BOOL("has-adb", NewWorldMacIOState, has_adb, false), 431 DEFINE_PROP_END_OF_LIST() 432 }; 433 434 static void macio_newworld_class_init(ObjectClass *oc, void *data) 435 { 436 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(oc); 437 DeviceClass *dc = DEVICE_CLASS(oc); 438 439 pdc->realize = macio_newworld_realize; 440 pdc->device_id = PCI_DEVICE_ID_APPLE_UNI_N_KEYL; 441 dc->vmsd = &vmstate_macio_newworld; 442 device_class_set_props(dc, macio_newworld_properties); 443 } 444 445 static Property macio_properties[] = { 446 DEFINE_PROP_UINT64("frequency", MacIOState, frequency, 0), 447 DEFINE_PROP_END_OF_LIST() 448 }; 449 450 static void macio_class_init(ObjectClass *klass, void *data) 451 { 452 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 453 DeviceClass *dc = DEVICE_CLASS(klass); 454 455 k->vendor_id = PCI_VENDOR_ID_APPLE; 456 k->class_id = PCI_CLASS_OTHERS << 8; 457 device_class_set_props(dc, macio_properties); 458 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 459 /* Reason: requires PIC property links to be set in macio_*_realize() */ 460 dc->user_creatable = false; 461 } 462 463 static const TypeInfo macio_bus_info = { 464 .name = TYPE_MACIO_BUS, 465 .parent = TYPE_SYSTEM_BUS, 466 .instance_size = sizeof(MacIOBusState), 467 }; 468 469 static const TypeInfo macio_oldworld_type_info = { 470 .name = TYPE_OLDWORLD_MACIO, 471 .parent = TYPE_MACIO, 472 .instance_size = sizeof(OldWorldMacIOState), 473 .instance_init = macio_oldworld_init, 474 .class_init = macio_oldworld_class_init, 475 }; 476 477 static const TypeInfo macio_newworld_type_info = { 478 .name = TYPE_NEWWORLD_MACIO, 479 .parent = TYPE_MACIO, 480 .instance_size = sizeof(NewWorldMacIOState), 481 .instance_init = macio_newworld_init, 482 .class_init = macio_newworld_class_init, 483 }; 484 485 static const TypeInfo macio_type_info = { 486 .name = TYPE_MACIO, 487 .parent = TYPE_PCI_DEVICE, 488 .instance_size = sizeof(MacIOState), 489 .instance_init = macio_instance_init, 490 .abstract = true, 491 .class_init = macio_class_init, 492 .interfaces = (InterfaceInfo[]) { 493 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 494 { }, 495 }, 496 }; 497 498 static void macio_register_types(void) 499 { 500 type_register_static(&macio_bus_info); 501 type_register_static(&macio_type_info); 502 type_register_static(&macio_oldworld_type_info); 503 type_register_static(&macio_newworld_type_info); 504 } 505 506 type_init(macio_register_types) 507