1 /* 2 * PowerMac MacIO device emulation 3 * 4 * Copyright (c) 2005-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "qemu/module.h" 29 #include "hw/ppc/mac.h" 30 #include "hw/misc/macio/cuda.h" 31 #include "hw/pci/pci.h" 32 #include "hw/ppc/mac_dbdma.h" 33 #include "hw/qdev-properties.h" 34 #include "migration/vmstate.h" 35 #include "hw/char/escc.h" 36 #include "hw/misc/macio/macio.h" 37 #include "hw/intc/heathrow_pic.h" 38 #include "sysemu/sysemu.h" 39 #include "trace.h" 40 41 /* Note: this code is strongly inspirated from the corresponding code 42 * in PearPC */ 43 44 /* 45 * The mac-io has two interfaces to the ESCC. One is called "escc-legacy", 46 * while the other one is the normal, current ESCC interface. 47 * 48 * The magic below creates memory aliases to spawn the escc-legacy device 49 * purely by rerouting the respective registers to our escc region. This 50 * works because the only difference between the two memory regions is the 51 * register layout, not their semantics. 52 * 53 * Reference: ftp://ftp.software.ibm.com/rs6000/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf 54 */ 55 static void macio_escc_legacy_setup(MacIOState *s) 56 { 57 ESCCState *escc = ESCC(&s->escc); 58 SysBusDevice *sbd = SYS_BUS_DEVICE(escc); 59 MemoryRegion *escc_legacy = g_new(MemoryRegion, 1); 60 MemoryRegion *bar = &s->bar; 61 int i; 62 static const int maps[] = { 63 0x00, 0x00, /* Command B */ 64 0x02, 0x20, /* Command A */ 65 0x04, 0x10, /* Data B */ 66 0x06, 0x30, /* Data A */ 67 0x08, 0x40, /* Enhancement B */ 68 0x0A, 0x50, /* Enhancement A */ 69 0x80, 0x80, /* Recovery count */ 70 0x90, 0x90, /* Start A */ 71 0xa0, 0xa0, /* Start B */ 72 0xb0, 0xb0, /* Detect AB */ 73 }; 74 75 memory_region_init(escc_legacy, OBJECT(s), "escc-legacy", 256); 76 for (i = 0; i < ARRAY_SIZE(maps); i += 2) { 77 MemoryRegion *port = g_new(MemoryRegion, 1); 78 memory_region_init_alias(port, OBJECT(s), "escc-legacy-port", 79 sysbus_mmio_get_region(sbd, 0), 80 maps[i + 1], 0x2); 81 memory_region_add_subregion(escc_legacy, maps[i], port); 82 } 83 84 memory_region_add_subregion(bar, 0x12000, escc_legacy); 85 } 86 87 static void macio_bar_setup(MacIOState *s) 88 { 89 ESCCState *escc = ESCC(&s->escc); 90 SysBusDevice *sbd = SYS_BUS_DEVICE(escc); 91 MemoryRegion *bar = &s->bar; 92 93 memory_region_add_subregion(bar, 0x13000, sysbus_mmio_get_region(sbd, 0)); 94 macio_escc_legacy_setup(s); 95 } 96 97 static void macio_common_realize(PCIDevice *d, Error **errp) 98 { 99 MacIOState *s = MACIO(d); 100 SysBusDevice *sysbus_dev; 101 102 if (!qdev_realize(DEVICE(&s->dbdma), BUS(&s->macio_bus), errp)) { 103 return; 104 } 105 sysbus_dev = SYS_BUS_DEVICE(&s->dbdma); 106 memory_region_add_subregion(&s->bar, 0x08000, 107 sysbus_mmio_get_region(sysbus_dev, 0)); 108 109 qdev_prop_set_uint32(DEVICE(&s->escc), "disabled", 0); 110 qdev_prop_set_uint32(DEVICE(&s->escc), "frequency", ESCC_CLOCK); 111 qdev_prop_set_uint32(DEVICE(&s->escc), "it_shift", 4); 112 qdev_prop_set_uint32(DEVICE(&s->escc), "chnBtype", escc_serial); 113 qdev_prop_set_uint32(DEVICE(&s->escc), "chnAtype", escc_serial); 114 if (!qdev_realize(DEVICE(&s->escc), BUS(&s->macio_bus), errp)) { 115 return; 116 } 117 118 macio_bar_setup(s); 119 pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar); 120 } 121 122 static void macio_realize_ide(MacIOState *s, MACIOIDEState *ide, 123 qemu_irq irq0, qemu_irq irq1, int dmaid, 124 Error **errp) 125 { 126 SysBusDevice *sysbus_dev; 127 128 sysbus_dev = SYS_BUS_DEVICE(ide); 129 sysbus_connect_irq(sysbus_dev, 0, irq0); 130 sysbus_connect_irq(sysbus_dev, 1, irq1); 131 qdev_prop_set_uint32(DEVICE(ide), "channel", dmaid); 132 object_property_set_link(OBJECT(ide), "dbdma", OBJECT(&s->dbdma), 133 &error_abort); 134 macio_ide_register_dma(ide); 135 136 qdev_realize(DEVICE(ide), BUS(&s->macio_bus), errp); 137 } 138 139 static void macio_oldworld_realize(PCIDevice *d, Error **errp) 140 { 141 MacIOState *s = MACIO(d); 142 OldWorldMacIOState *os = OLDWORLD_MACIO(d); 143 DeviceState *pic_dev = DEVICE(&os->pic); 144 Error *err = NULL; 145 SysBusDevice *sysbus_dev; 146 147 macio_common_realize(d, &err); 148 if (err) { 149 error_propagate(errp, err); 150 return; 151 } 152 153 /* Heathrow PIC */ 154 if (!qdev_realize(DEVICE(&os->pic), BUS(&s->macio_bus), errp)) { 155 return; 156 } 157 sysbus_dev = SYS_BUS_DEVICE(&os->pic); 158 memory_region_add_subregion(&s->bar, 0x0, 159 sysbus_mmio_get_region(sysbus_dev, 0)); 160 161 qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency", 162 s->frequency); 163 if (!qdev_realize(DEVICE(&s->cuda), BUS(&s->macio_bus), errp)) { 164 return; 165 } 166 sysbus_dev = SYS_BUS_DEVICE(&s->cuda); 167 memory_region_add_subregion(&s->bar, 0x16000, 168 sysbus_mmio_get_region(sysbus_dev, 0)); 169 sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev, 170 OLDWORLD_CUDA_IRQ)); 171 172 sysbus_dev = SYS_BUS_DEVICE(&s->escc); 173 sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev, 174 OLDWORLD_ESCCB_IRQ)); 175 sysbus_connect_irq(sysbus_dev, 1, qdev_get_gpio_in(pic_dev, 176 OLDWORLD_ESCCA_IRQ)); 177 178 if (!qdev_realize(DEVICE(&os->nvram), BUS(&s->macio_bus), errp)) { 179 return; 180 } 181 sysbus_dev = SYS_BUS_DEVICE(&os->nvram); 182 memory_region_add_subregion(&s->bar, 0x60000, 183 sysbus_mmio_get_region(sysbus_dev, 0)); 184 pmac_format_nvram_partition(&os->nvram, os->nvram.size); 185 186 /* IDE buses */ 187 macio_realize_ide(s, &os->ide[0], 188 qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_IRQ), 189 qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_DMA_IRQ), 190 0x16, &err); 191 if (err) { 192 error_propagate(errp, err); 193 return; 194 } 195 196 macio_realize_ide(s, &os->ide[1], 197 qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_IRQ), 198 qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_DMA_IRQ), 199 0x1a, &err); 200 if (err) { 201 error_propagate(errp, err); 202 return; 203 } 204 } 205 206 static void macio_init_ide(MacIOState *s, MACIOIDEState *ide, int index) 207 { 208 gchar *name = g_strdup_printf("ide[%i]", index); 209 uint32_t addr = 0x1f000 + ((index + 1) * 0x1000); 210 211 object_initialize_child(OBJECT(s), name, ide, TYPE_MACIO_IDE); 212 qdev_prop_set_uint32(DEVICE(ide), "addr", addr); 213 memory_region_add_subregion(&s->bar, addr, &ide->mem); 214 g_free(name); 215 } 216 217 static void macio_oldworld_init(Object *obj) 218 { 219 MacIOState *s = MACIO(obj); 220 OldWorldMacIOState *os = OLDWORLD_MACIO(obj); 221 DeviceState *dev; 222 int i; 223 224 object_initialize_child(OBJECT(s), "pic", &os->pic, TYPE_HEATHROW); 225 226 object_initialize_child(OBJECT(s), "cuda", &s->cuda, TYPE_CUDA); 227 228 object_initialize_child(OBJECT(s), "nvram", &os->nvram, TYPE_MACIO_NVRAM); 229 dev = DEVICE(&os->nvram); 230 qdev_prop_set_uint32(dev, "size", 0x2000); 231 qdev_prop_set_uint32(dev, "it_shift", 4); 232 233 for (i = 0; i < 2; i++) { 234 macio_init_ide(s, &os->ide[i], i); 235 } 236 } 237 238 static void timer_write(void *opaque, hwaddr addr, uint64_t value, 239 unsigned size) 240 { 241 trace_macio_timer_write(addr, size, value); 242 } 243 244 static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size) 245 { 246 uint32_t value = 0; 247 uint64_t systime = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 248 uint64_t kltime; 249 250 kltime = muldiv64(systime, 4194300, NANOSECONDS_PER_SECOND * 4); 251 kltime = muldiv64(kltime, 18432000, 1048575); 252 253 switch (addr) { 254 case 0x38: 255 value = kltime; 256 break; 257 case 0x3c: 258 value = kltime >> 32; 259 break; 260 } 261 262 trace_macio_timer_read(addr, size, value); 263 return value; 264 } 265 266 static const MemoryRegionOps timer_ops = { 267 .read = timer_read, 268 .write = timer_write, 269 .endianness = DEVICE_LITTLE_ENDIAN, 270 }; 271 272 static void macio_newworld_realize(PCIDevice *d, Error **errp) 273 { 274 MacIOState *s = MACIO(d); 275 NewWorldMacIOState *ns = NEWWORLD_MACIO(d); 276 DeviceState *pic_dev = DEVICE(&ns->pic); 277 Error *err = NULL; 278 SysBusDevice *sysbus_dev; 279 MemoryRegion *timer_memory = NULL; 280 281 macio_common_realize(d, &err); 282 if (err) { 283 error_propagate(errp, err); 284 return; 285 } 286 287 /* OpenPIC */ 288 qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO); 289 sysbus_dev = SYS_BUS_DEVICE(&ns->pic); 290 sysbus_realize_and_unref(sysbus_dev, &error_fatal); 291 memory_region_add_subregion(&s->bar, 0x40000, 292 sysbus_mmio_get_region(sysbus_dev, 0)); 293 294 sysbus_dev = SYS_BUS_DEVICE(&s->escc); 295 sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev, 296 NEWWORLD_ESCCB_IRQ)); 297 sysbus_connect_irq(sysbus_dev, 1, qdev_get_gpio_in(pic_dev, 298 NEWWORLD_ESCCA_IRQ)); 299 300 /* IDE buses */ 301 macio_realize_ide(s, &ns->ide[0], 302 qdev_get_gpio_in(pic_dev, NEWWORLD_IDE0_IRQ), 303 qdev_get_gpio_in(pic_dev, NEWWORLD_IDE0_DMA_IRQ), 304 0x16, &err); 305 if (err) { 306 error_propagate(errp, err); 307 return; 308 } 309 310 macio_realize_ide(s, &ns->ide[1], 311 qdev_get_gpio_in(pic_dev, NEWWORLD_IDE1_IRQ), 312 qdev_get_gpio_in(pic_dev, NEWWORLD_IDE1_DMA_IRQ), 313 0x1a, &err); 314 if (err) { 315 error_propagate(errp, err); 316 return; 317 } 318 319 /* Timer */ 320 timer_memory = g_new(MemoryRegion, 1); 321 memory_region_init_io(timer_memory, OBJECT(s), &timer_ops, NULL, "timer", 322 0x1000); 323 memory_region_add_subregion(&s->bar, 0x15000, timer_memory); 324 325 if (ns->has_pmu) { 326 /* GPIOs */ 327 if (!qdev_realize(DEVICE(&ns->gpio), BUS(&s->macio_bus), errp)) { 328 return; 329 } 330 sysbus_dev = SYS_BUS_DEVICE(&ns->gpio); 331 sysbus_connect_irq(sysbus_dev, 1, qdev_get_gpio_in(pic_dev, 332 NEWWORLD_EXTING_GPIO1)); 333 sysbus_connect_irq(sysbus_dev, 9, qdev_get_gpio_in(pic_dev, 334 NEWWORLD_EXTING_GPIO9)); 335 memory_region_add_subregion(&s->bar, 0x50, 336 sysbus_mmio_get_region(sysbus_dev, 0)); 337 338 /* PMU */ 339 object_initialize_child(OBJECT(s), "pmu", &s->pmu, TYPE_VIA_PMU); 340 object_property_set_link(OBJECT(&s->pmu), "gpio", OBJECT(sysbus_dev), 341 &error_abort); 342 qdev_prop_set_bit(DEVICE(&s->pmu), "has-adb", ns->has_adb); 343 if (!qdev_realize(DEVICE(&s->pmu), BUS(&s->macio_bus), errp)) { 344 return; 345 } 346 sysbus_dev = SYS_BUS_DEVICE(&s->pmu); 347 sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev, 348 NEWWORLD_PMU_IRQ)); 349 memory_region_add_subregion(&s->bar, 0x16000, 350 sysbus_mmio_get_region(sysbus_dev, 0)); 351 } else { 352 object_unparent(OBJECT(&ns->gpio)); 353 354 /* CUDA */ 355 object_initialize_child(OBJECT(s), "cuda", &s->cuda, TYPE_CUDA); 356 qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency", 357 s->frequency); 358 359 if (!qdev_realize(DEVICE(&s->cuda), BUS(&s->macio_bus), errp)) { 360 return; 361 } 362 sysbus_dev = SYS_BUS_DEVICE(&s->cuda); 363 sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev, 364 NEWWORLD_CUDA_IRQ)); 365 memory_region_add_subregion(&s->bar, 0x16000, 366 sysbus_mmio_get_region(sysbus_dev, 0)); 367 } 368 } 369 370 static void macio_newworld_init(Object *obj) 371 { 372 MacIOState *s = MACIO(obj); 373 NewWorldMacIOState *ns = NEWWORLD_MACIO(obj); 374 int i; 375 376 object_initialize_child(OBJECT(s), "pic", &ns->pic, TYPE_OPENPIC); 377 378 object_initialize_child(OBJECT(s), "gpio", &ns->gpio, TYPE_MACIO_GPIO); 379 380 for (i = 0; i < 2; i++) { 381 macio_init_ide(s, &ns->ide[i], i); 382 } 383 } 384 385 static void macio_instance_init(Object *obj) 386 { 387 MacIOState *s = MACIO(obj); 388 389 memory_region_init(&s->bar, obj, "macio", 0x80000); 390 391 qbus_create_inplace(&s->macio_bus, sizeof(s->macio_bus), TYPE_MACIO_BUS, 392 DEVICE(obj), "macio.0"); 393 394 object_initialize_child(OBJECT(s), "dbdma", &s->dbdma, TYPE_MAC_DBDMA); 395 396 object_initialize_child(OBJECT(s), "escc", &s->escc, TYPE_ESCC); 397 } 398 399 static const VMStateDescription vmstate_macio_oldworld = { 400 .name = "macio-oldworld", 401 .version_id = 0, 402 .minimum_version_id = 0, 403 .fields = (VMStateField[]) { 404 VMSTATE_PCI_DEVICE(parent_obj.parent, OldWorldMacIOState), 405 VMSTATE_END_OF_LIST() 406 } 407 }; 408 409 static void macio_oldworld_class_init(ObjectClass *oc, void *data) 410 { 411 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(oc); 412 DeviceClass *dc = DEVICE_CLASS(oc); 413 414 pdc->realize = macio_oldworld_realize; 415 pdc->device_id = PCI_DEVICE_ID_APPLE_343S1201; 416 dc->vmsd = &vmstate_macio_oldworld; 417 } 418 419 static const VMStateDescription vmstate_macio_newworld = { 420 .name = "macio-newworld", 421 .version_id = 0, 422 .minimum_version_id = 0, 423 .fields = (VMStateField[]) { 424 VMSTATE_PCI_DEVICE(parent_obj.parent, NewWorldMacIOState), 425 VMSTATE_END_OF_LIST() 426 } 427 }; 428 429 static Property macio_newworld_properties[] = { 430 DEFINE_PROP_BOOL("has-pmu", NewWorldMacIOState, has_pmu, false), 431 DEFINE_PROP_BOOL("has-adb", NewWorldMacIOState, has_adb, false), 432 DEFINE_PROP_END_OF_LIST() 433 }; 434 435 static void macio_newworld_class_init(ObjectClass *oc, void *data) 436 { 437 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(oc); 438 DeviceClass *dc = DEVICE_CLASS(oc); 439 440 pdc->realize = macio_newworld_realize; 441 pdc->device_id = PCI_DEVICE_ID_APPLE_UNI_N_KEYL; 442 dc->vmsd = &vmstate_macio_newworld; 443 device_class_set_props(dc, macio_newworld_properties); 444 } 445 446 static Property macio_properties[] = { 447 DEFINE_PROP_UINT64("frequency", MacIOState, frequency, 0), 448 DEFINE_PROP_END_OF_LIST() 449 }; 450 451 static void macio_class_init(ObjectClass *klass, void *data) 452 { 453 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 454 DeviceClass *dc = DEVICE_CLASS(klass); 455 456 k->vendor_id = PCI_VENDOR_ID_APPLE; 457 k->class_id = PCI_CLASS_OTHERS << 8; 458 device_class_set_props(dc, macio_properties); 459 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 460 } 461 462 static const TypeInfo macio_bus_info = { 463 .name = TYPE_MACIO_BUS, 464 .parent = TYPE_SYSTEM_BUS, 465 .instance_size = sizeof(MacIOBusState), 466 }; 467 468 static const TypeInfo macio_oldworld_type_info = { 469 .name = TYPE_OLDWORLD_MACIO, 470 .parent = TYPE_MACIO, 471 .instance_size = sizeof(OldWorldMacIOState), 472 .instance_init = macio_oldworld_init, 473 .class_init = macio_oldworld_class_init, 474 }; 475 476 static const TypeInfo macio_newworld_type_info = { 477 .name = TYPE_NEWWORLD_MACIO, 478 .parent = TYPE_MACIO, 479 .instance_size = sizeof(NewWorldMacIOState), 480 .instance_init = macio_newworld_init, 481 .class_init = macio_newworld_class_init, 482 }; 483 484 static const TypeInfo macio_type_info = { 485 .name = TYPE_MACIO, 486 .parent = TYPE_PCI_DEVICE, 487 .instance_size = sizeof(MacIOState), 488 .instance_init = macio_instance_init, 489 .abstract = true, 490 .class_init = macio_class_init, 491 .interfaces = (InterfaceInfo[]) { 492 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 493 { }, 494 }, 495 }; 496 497 static void macio_register_types(void) 498 { 499 type_register_static(&macio_bus_info); 500 type_register_static(&macio_type_info); 501 type_register_static(&macio_oldworld_type_info); 502 type_register_static(&macio_newworld_type_info); 503 } 504 505 type_init(macio_register_types) 506