1 /* 2 * PowerMac descriptor-based DMA emulation 3 * 4 * Copyright (c) 2005-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2009 Laurent Vivier 7 * 8 * some parts from linux-2.6.28, arch/powerpc/include/asm/dbdma.h 9 * 10 * Definitions for using the Apple Descriptor-Based DMA controller 11 * in Power Macintosh computers. 12 * 13 * Copyright (C) 1996 Paul Mackerras. 14 * 15 * some parts from mol 0.9.71 16 * 17 * Descriptor based DMA emulation 18 * 19 * Copyright (C) 1998-2004 Samuel Rydh (samuel@ibrium.se) 20 * 21 * Permission is hereby granted, free of charge, to any person obtaining a copy 22 * of this software and associated documentation files (the "Software"), to deal 23 * in the Software without restriction, including without limitation the rights 24 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 25 * copies of the Software, and to permit persons to whom the Software is 26 * furnished to do so, subject to the following conditions: 27 * 28 * The above copyright notice and this permission notice shall be included in 29 * all copies or substantial portions of the Software. 30 * 31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 32 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 33 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 34 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 35 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 36 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 37 * THE SOFTWARE. 38 */ 39 #include "qemu/osdep.h" 40 #include "hw/hw.h" 41 #include "hw/isa/isa.h" 42 #include "hw/ppc/mac_dbdma.h" 43 #include "qemu/main-loop.h" 44 #include "qemu/log.h" 45 #include "sysemu/dma.h" 46 47 /* debug DBDMA */ 48 #define DEBUG_DBDMA 0 49 #define DEBUG_DBDMA_CHANMASK ((1ull << DBDMA_CHANNELS) - 1) 50 51 #define DBDMA_DPRINTF(fmt, ...) do { \ 52 if (DEBUG_DBDMA) { \ 53 printf("DBDMA: " fmt , ## __VA_ARGS__); \ 54 } \ 55 } while (0); 56 57 #define DBDMA_DPRINTFCH(ch, fmt, ...) do { \ 58 if (DEBUG_DBDMA) { \ 59 if ((1ul << (ch)->channel) & DEBUG_DBDMA_CHANMASK) { \ 60 printf("DBDMA[%02x]: " fmt , (ch)->channel, ## __VA_ARGS__); \ 61 } \ 62 } \ 63 } while (0); 64 65 /* 66 */ 67 68 static DBDMAState *dbdma_from_ch(DBDMA_channel *ch) 69 { 70 return container_of(ch, DBDMAState, channels[ch->channel]); 71 } 72 73 #if DEBUG_DBDMA 74 static void dump_dbdma_cmd(dbdma_cmd *cmd) 75 { 76 printf("dbdma_cmd %p\n", cmd); 77 printf(" req_count 0x%04x\n", le16_to_cpu(cmd->req_count)); 78 printf(" command 0x%04x\n", le16_to_cpu(cmd->command)); 79 printf(" phy_addr 0x%08x\n", le32_to_cpu(cmd->phy_addr)); 80 printf(" cmd_dep 0x%08x\n", le32_to_cpu(cmd->cmd_dep)); 81 printf(" res_count 0x%04x\n", le16_to_cpu(cmd->res_count)); 82 printf(" xfer_status 0x%04x\n", le16_to_cpu(cmd->xfer_status)); 83 } 84 #else 85 static void dump_dbdma_cmd(dbdma_cmd *cmd) 86 { 87 } 88 #endif 89 static void dbdma_cmdptr_load(DBDMA_channel *ch) 90 { 91 DBDMA_DPRINTFCH(ch, "dbdma_cmdptr_load 0x%08x\n", 92 ch->regs[DBDMA_CMDPTR_LO]); 93 dma_memory_read(&address_space_memory, ch->regs[DBDMA_CMDPTR_LO], 94 &ch->current, sizeof(dbdma_cmd)); 95 } 96 97 static void dbdma_cmdptr_save(DBDMA_channel *ch) 98 { 99 DBDMA_DPRINTFCH(ch, "dbdma_cmdptr_save 0x%08x\n", 100 ch->regs[DBDMA_CMDPTR_LO]); 101 DBDMA_DPRINTFCH(ch, "xfer_status 0x%08x res_count 0x%04x\n", 102 le16_to_cpu(ch->current.xfer_status), 103 le16_to_cpu(ch->current.res_count)); 104 dma_memory_write(&address_space_memory, ch->regs[DBDMA_CMDPTR_LO], 105 &ch->current, sizeof(dbdma_cmd)); 106 } 107 108 static void kill_channel(DBDMA_channel *ch) 109 { 110 DBDMA_DPRINTFCH(ch, "kill_channel\n"); 111 112 ch->regs[DBDMA_STATUS] |= DEAD; 113 ch->regs[DBDMA_STATUS] &= ~ACTIVE; 114 115 qemu_irq_raise(ch->irq); 116 } 117 118 static void conditional_interrupt(DBDMA_channel *ch) 119 { 120 dbdma_cmd *current = &ch->current; 121 uint16_t intr; 122 uint16_t sel_mask, sel_value; 123 uint32_t status; 124 int cond; 125 126 DBDMA_DPRINTFCH(ch, "%s\n", __func__); 127 128 intr = le16_to_cpu(current->command) & INTR_MASK; 129 130 switch(intr) { 131 case INTR_NEVER: /* don't interrupt */ 132 return; 133 case INTR_ALWAYS: /* always interrupt */ 134 qemu_irq_raise(ch->irq); 135 DBDMA_DPRINTFCH(ch, "%s: raise\n", __func__); 136 return; 137 } 138 139 status = ch->regs[DBDMA_STATUS] & DEVSTAT; 140 141 sel_mask = (ch->regs[DBDMA_INTR_SEL] >> 16) & 0x0f; 142 sel_value = ch->regs[DBDMA_INTR_SEL] & 0x0f; 143 144 cond = (status & sel_mask) == (sel_value & sel_mask); 145 146 switch(intr) { 147 case INTR_IFSET: /* intr if condition bit is 1 */ 148 if (cond) { 149 qemu_irq_raise(ch->irq); 150 DBDMA_DPRINTFCH(ch, "%s: raise\n", __func__); 151 } 152 return; 153 case INTR_IFCLR: /* intr if condition bit is 0 */ 154 if (!cond) { 155 qemu_irq_raise(ch->irq); 156 DBDMA_DPRINTFCH(ch, "%s: raise\n", __func__); 157 } 158 return; 159 } 160 } 161 162 static int conditional_wait(DBDMA_channel *ch) 163 { 164 dbdma_cmd *current = &ch->current; 165 uint16_t wait; 166 uint16_t sel_mask, sel_value; 167 uint32_t status; 168 int cond; 169 170 DBDMA_DPRINTFCH(ch, "conditional_wait\n"); 171 172 wait = le16_to_cpu(current->command) & WAIT_MASK; 173 174 switch(wait) { 175 case WAIT_NEVER: /* don't wait */ 176 return 0; 177 case WAIT_ALWAYS: /* always wait */ 178 return 1; 179 } 180 181 status = ch->regs[DBDMA_STATUS] & DEVSTAT; 182 183 sel_mask = (ch->regs[DBDMA_WAIT_SEL] >> 16) & 0x0f; 184 sel_value = ch->regs[DBDMA_WAIT_SEL] & 0x0f; 185 186 cond = (status & sel_mask) == (sel_value & sel_mask); 187 188 switch(wait) { 189 case WAIT_IFSET: /* wait if condition bit is 1 */ 190 if (cond) 191 return 1; 192 return 0; 193 case WAIT_IFCLR: /* wait if condition bit is 0 */ 194 if (!cond) 195 return 1; 196 return 0; 197 } 198 return 0; 199 } 200 201 static void next(DBDMA_channel *ch) 202 { 203 uint32_t cp; 204 205 ch->regs[DBDMA_STATUS] &= ~BT; 206 207 cp = ch->regs[DBDMA_CMDPTR_LO]; 208 ch->regs[DBDMA_CMDPTR_LO] = cp + sizeof(dbdma_cmd); 209 dbdma_cmdptr_load(ch); 210 } 211 212 static void branch(DBDMA_channel *ch) 213 { 214 dbdma_cmd *current = &ch->current; 215 216 ch->regs[DBDMA_CMDPTR_LO] = current->cmd_dep; 217 ch->regs[DBDMA_STATUS] |= BT; 218 dbdma_cmdptr_load(ch); 219 } 220 221 static void conditional_branch(DBDMA_channel *ch) 222 { 223 dbdma_cmd *current = &ch->current; 224 uint16_t br; 225 uint16_t sel_mask, sel_value; 226 uint32_t status; 227 int cond; 228 229 DBDMA_DPRINTFCH(ch, "conditional_branch\n"); 230 231 /* check if we must branch */ 232 233 br = le16_to_cpu(current->command) & BR_MASK; 234 235 switch(br) { 236 case BR_NEVER: /* don't branch */ 237 next(ch); 238 return; 239 case BR_ALWAYS: /* always branch */ 240 branch(ch); 241 return; 242 } 243 244 status = ch->regs[DBDMA_STATUS] & DEVSTAT; 245 246 sel_mask = (ch->regs[DBDMA_BRANCH_SEL] >> 16) & 0x0f; 247 sel_value = ch->regs[DBDMA_BRANCH_SEL] & 0x0f; 248 249 cond = (status & sel_mask) == (sel_value & sel_mask); 250 251 switch(br) { 252 case BR_IFSET: /* branch if condition bit is 1 */ 253 if (cond) 254 branch(ch); 255 else 256 next(ch); 257 return; 258 case BR_IFCLR: /* branch if condition bit is 0 */ 259 if (!cond) 260 branch(ch); 261 else 262 next(ch); 263 return; 264 } 265 } 266 267 static void channel_run(DBDMA_channel *ch); 268 269 static void dbdma_end(DBDMA_io *io) 270 { 271 DBDMA_channel *ch = io->channel; 272 dbdma_cmd *current = &ch->current; 273 274 DBDMA_DPRINTFCH(ch, "%s\n", __func__); 275 276 if (conditional_wait(ch)) 277 goto wait; 278 279 current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]); 280 current->res_count = cpu_to_le16(io->len); 281 dbdma_cmdptr_save(ch); 282 if (io->is_last) 283 ch->regs[DBDMA_STATUS] &= ~FLUSH; 284 285 conditional_interrupt(ch); 286 conditional_branch(ch); 287 288 wait: 289 /* Indicate that we're ready for a new DMA round */ 290 ch->io.processing = false; 291 292 if ((ch->regs[DBDMA_STATUS] & RUN) && 293 (ch->regs[DBDMA_STATUS] & ACTIVE)) 294 channel_run(ch); 295 } 296 297 static void start_output(DBDMA_channel *ch, int key, uint32_t addr, 298 uint16_t req_count, int is_last) 299 { 300 DBDMA_DPRINTFCH(ch, "start_output\n"); 301 302 /* KEY_REGS, KEY_DEVICE and KEY_STREAM 303 * are not implemented in the mac-io chip 304 */ 305 306 DBDMA_DPRINTFCH(ch, "addr 0x%x key 0x%x\n", addr, key); 307 if (!addr || key > KEY_STREAM3) { 308 kill_channel(ch); 309 return; 310 } 311 312 ch->io.addr = addr; 313 ch->io.len = req_count; 314 ch->io.is_last = is_last; 315 ch->io.dma_end = dbdma_end; 316 ch->io.is_dma_out = 1; 317 ch->io.processing = true; 318 if (ch->rw) { 319 ch->rw(&ch->io); 320 } 321 } 322 323 static void start_input(DBDMA_channel *ch, int key, uint32_t addr, 324 uint16_t req_count, int is_last) 325 { 326 DBDMA_DPRINTFCH(ch, "start_input\n"); 327 328 /* KEY_REGS, KEY_DEVICE and KEY_STREAM 329 * are not implemented in the mac-io chip 330 */ 331 332 DBDMA_DPRINTFCH(ch, "addr 0x%x key 0x%x\n", addr, key); 333 if (!addr || key > KEY_STREAM3) { 334 kill_channel(ch); 335 return; 336 } 337 338 ch->io.addr = addr; 339 ch->io.len = req_count; 340 ch->io.is_last = is_last; 341 ch->io.dma_end = dbdma_end; 342 ch->io.is_dma_out = 0; 343 ch->io.processing = true; 344 if (ch->rw) { 345 ch->rw(&ch->io); 346 } 347 } 348 349 static void load_word(DBDMA_channel *ch, int key, uint32_t addr, 350 uint16_t len) 351 { 352 dbdma_cmd *current = &ch->current; 353 uint32_t val; 354 355 DBDMA_DPRINTFCH(ch, "load_word\n"); 356 357 /* only implements KEY_SYSTEM */ 358 359 if (key != KEY_SYSTEM) { 360 printf("DBDMA: LOAD_WORD, unimplemented key %x\n", key); 361 kill_channel(ch); 362 return; 363 } 364 365 dma_memory_read(&address_space_memory, addr, &val, len); 366 367 if (len == 2) 368 val = (val << 16) | (current->cmd_dep & 0x0000ffff); 369 else if (len == 1) 370 val = (val << 24) | (current->cmd_dep & 0x00ffffff); 371 372 current->cmd_dep = val; 373 374 if (conditional_wait(ch)) 375 goto wait; 376 377 current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]); 378 dbdma_cmdptr_save(ch); 379 ch->regs[DBDMA_STATUS] &= ~FLUSH; 380 381 conditional_interrupt(ch); 382 next(ch); 383 384 wait: 385 DBDMA_kick(dbdma_from_ch(ch)); 386 } 387 388 static void store_word(DBDMA_channel *ch, int key, uint32_t addr, 389 uint16_t len) 390 { 391 dbdma_cmd *current = &ch->current; 392 uint32_t val; 393 394 DBDMA_DPRINTFCH(ch, "store_word\n"); 395 396 /* only implements KEY_SYSTEM */ 397 398 if (key != KEY_SYSTEM) { 399 printf("DBDMA: STORE_WORD, unimplemented key %x\n", key); 400 kill_channel(ch); 401 return; 402 } 403 404 val = current->cmd_dep; 405 if (len == 2) 406 val >>= 16; 407 else if (len == 1) 408 val >>= 24; 409 410 dma_memory_write(&address_space_memory, addr, &val, len); 411 412 if (conditional_wait(ch)) 413 goto wait; 414 415 current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]); 416 dbdma_cmdptr_save(ch); 417 ch->regs[DBDMA_STATUS] &= ~FLUSH; 418 419 conditional_interrupt(ch); 420 next(ch); 421 422 wait: 423 DBDMA_kick(dbdma_from_ch(ch)); 424 } 425 426 static void nop(DBDMA_channel *ch) 427 { 428 dbdma_cmd *current = &ch->current; 429 430 if (conditional_wait(ch)) 431 goto wait; 432 433 current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]); 434 dbdma_cmdptr_save(ch); 435 436 conditional_interrupt(ch); 437 conditional_branch(ch); 438 439 wait: 440 DBDMA_kick(dbdma_from_ch(ch)); 441 } 442 443 static void stop(DBDMA_channel *ch) 444 { 445 ch->regs[DBDMA_STATUS] &= ~(ACTIVE|DEAD|FLUSH); 446 447 /* the stop command does not increment command pointer */ 448 } 449 450 static void channel_run(DBDMA_channel *ch) 451 { 452 dbdma_cmd *current = &ch->current; 453 uint16_t cmd, key; 454 uint16_t req_count; 455 uint32_t phy_addr; 456 457 DBDMA_DPRINTFCH(ch, "channel_run\n"); 458 dump_dbdma_cmd(current); 459 460 /* clear WAKE flag at command fetch */ 461 462 ch->regs[DBDMA_STATUS] &= ~WAKE; 463 464 cmd = le16_to_cpu(current->command) & COMMAND_MASK; 465 466 switch (cmd) { 467 case DBDMA_NOP: 468 nop(ch); 469 return; 470 471 case DBDMA_STOP: 472 stop(ch); 473 return; 474 } 475 476 key = le16_to_cpu(current->command) & 0x0700; 477 req_count = le16_to_cpu(current->req_count); 478 phy_addr = le32_to_cpu(current->phy_addr); 479 480 if (key == KEY_STREAM4) { 481 printf("command %x, invalid key 4\n", cmd); 482 kill_channel(ch); 483 return; 484 } 485 486 switch (cmd) { 487 case OUTPUT_MORE: 488 start_output(ch, key, phy_addr, req_count, 0); 489 return; 490 491 case OUTPUT_LAST: 492 start_output(ch, key, phy_addr, req_count, 1); 493 return; 494 495 case INPUT_MORE: 496 start_input(ch, key, phy_addr, req_count, 0); 497 return; 498 499 case INPUT_LAST: 500 start_input(ch, key, phy_addr, req_count, 1); 501 return; 502 } 503 504 if (key < KEY_REGS) { 505 printf("command %x, invalid key %x\n", cmd, key); 506 key = KEY_SYSTEM; 507 } 508 509 /* for LOAD_WORD and STORE_WORD, req_count is on 3 bits 510 * and BRANCH is invalid 511 */ 512 513 req_count = req_count & 0x0007; 514 if (req_count & 0x4) { 515 req_count = 4; 516 phy_addr &= ~3; 517 } else if (req_count & 0x2) { 518 req_count = 2; 519 phy_addr &= ~1; 520 } else 521 req_count = 1; 522 523 switch (cmd) { 524 case LOAD_WORD: 525 load_word(ch, key, phy_addr, req_count); 526 return; 527 528 case STORE_WORD: 529 store_word(ch, key, phy_addr, req_count); 530 return; 531 } 532 } 533 534 static void DBDMA_run(DBDMAState *s) 535 { 536 int channel; 537 538 for (channel = 0; channel < DBDMA_CHANNELS; channel++) { 539 DBDMA_channel *ch = &s->channels[channel]; 540 uint32_t status = ch->regs[DBDMA_STATUS]; 541 if (!ch->io.processing && (status & RUN) && (status & ACTIVE)) { 542 channel_run(ch); 543 } 544 } 545 } 546 547 static void DBDMA_run_bh(void *opaque) 548 { 549 DBDMAState *s = opaque; 550 551 DBDMA_DPRINTF("-> DBDMA_run_bh\n"); 552 DBDMA_run(s); 553 DBDMA_DPRINTF("<- DBDMA_run_bh\n"); 554 } 555 556 void DBDMA_kick(DBDMAState *dbdma) 557 { 558 qemu_bh_schedule(dbdma->bh); 559 } 560 561 void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq, 562 DBDMA_rw rw, DBDMA_flush flush, 563 void *opaque) 564 { 565 DBDMAState *s = dbdma; 566 DBDMA_channel *ch = &s->channels[nchan]; 567 568 DBDMA_DPRINTFCH(ch, "DBDMA_register_channel 0x%x\n", nchan); 569 570 assert(rw); 571 assert(flush); 572 573 ch->irq = irq; 574 ch->rw = rw; 575 ch->flush = flush; 576 ch->io.opaque = opaque; 577 } 578 579 static void 580 dbdma_control_write(DBDMA_channel *ch) 581 { 582 uint16_t mask, value; 583 uint32_t status; 584 585 mask = (ch->regs[DBDMA_CONTROL] >> 16) & 0xffff; 586 value = ch->regs[DBDMA_CONTROL] & 0xffff; 587 588 value &= (RUN | PAUSE | FLUSH | WAKE | DEVSTAT); 589 590 status = ch->regs[DBDMA_STATUS]; 591 592 status = (value & mask) | (status & ~mask); 593 594 if (status & WAKE) 595 status |= ACTIVE; 596 if (status & RUN) { 597 status |= ACTIVE; 598 status &= ~DEAD; 599 } 600 if (status & PAUSE) 601 status &= ~ACTIVE; 602 if ((ch->regs[DBDMA_STATUS] & RUN) && !(status & RUN)) { 603 /* RUN is cleared */ 604 status &= ~(ACTIVE|DEAD); 605 } 606 607 if ((status & FLUSH) && ch->flush) { 608 ch->flush(&ch->io); 609 status &= ~FLUSH; 610 } 611 612 DBDMA_DPRINTFCH(ch, " status 0x%08x\n", status); 613 614 ch->regs[DBDMA_STATUS] = status; 615 616 if (status & ACTIVE) { 617 DBDMA_kick(dbdma_from_ch(ch)); 618 } 619 } 620 621 static void dbdma_write(void *opaque, hwaddr addr, 622 uint64_t value, unsigned size) 623 { 624 int channel = addr >> DBDMA_CHANNEL_SHIFT; 625 DBDMAState *s = opaque; 626 DBDMA_channel *ch = &s->channels[channel]; 627 int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2; 628 629 DBDMA_DPRINTFCH(ch, "writel 0x" TARGET_FMT_plx " <= 0x%08"PRIx64"\n", 630 addr, value); 631 DBDMA_DPRINTFCH(ch, "channel 0x%x reg 0x%x\n", 632 (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg); 633 634 /* cmdptr cannot be modified if channel is ACTIVE */ 635 636 if (reg == DBDMA_CMDPTR_LO && (ch->regs[DBDMA_STATUS] & ACTIVE)) { 637 return; 638 } 639 640 ch->regs[reg] = value; 641 642 switch(reg) { 643 case DBDMA_CONTROL: 644 dbdma_control_write(ch); 645 break; 646 case DBDMA_CMDPTR_LO: 647 /* 16-byte aligned */ 648 ch->regs[DBDMA_CMDPTR_LO] &= ~0xf; 649 dbdma_cmdptr_load(ch); 650 break; 651 case DBDMA_STATUS: 652 case DBDMA_INTR_SEL: 653 case DBDMA_BRANCH_SEL: 654 case DBDMA_WAIT_SEL: 655 /* nothing to do */ 656 break; 657 case DBDMA_XFER_MODE: 658 case DBDMA_CMDPTR_HI: 659 case DBDMA_DATA2PTR_HI: 660 case DBDMA_DATA2PTR_LO: 661 case DBDMA_ADDRESS_HI: 662 case DBDMA_BRANCH_ADDR_HI: 663 case DBDMA_RES1: 664 case DBDMA_RES2: 665 case DBDMA_RES3: 666 case DBDMA_RES4: 667 /* unused */ 668 break; 669 } 670 } 671 672 static uint64_t dbdma_read(void *opaque, hwaddr addr, 673 unsigned size) 674 { 675 uint32_t value; 676 int channel = addr >> DBDMA_CHANNEL_SHIFT; 677 DBDMAState *s = opaque; 678 DBDMA_channel *ch = &s->channels[channel]; 679 int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2; 680 681 value = ch->regs[reg]; 682 683 DBDMA_DPRINTFCH(ch, "readl 0x" TARGET_FMT_plx " => 0x%08x\n", addr, value); 684 DBDMA_DPRINTFCH(ch, "channel 0x%x reg 0x%x\n", 685 (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg); 686 687 switch(reg) { 688 case DBDMA_CONTROL: 689 value = 0; 690 break; 691 case DBDMA_STATUS: 692 case DBDMA_CMDPTR_LO: 693 case DBDMA_INTR_SEL: 694 case DBDMA_BRANCH_SEL: 695 case DBDMA_WAIT_SEL: 696 /* nothing to do */ 697 break; 698 case DBDMA_XFER_MODE: 699 case DBDMA_CMDPTR_HI: 700 case DBDMA_DATA2PTR_HI: 701 case DBDMA_DATA2PTR_LO: 702 case DBDMA_ADDRESS_HI: 703 case DBDMA_BRANCH_ADDR_HI: 704 /* unused */ 705 value = 0; 706 break; 707 case DBDMA_RES1: 708 case DBDMA_RES2: 709 case DBDMA_RES3: 710 case DBDMA_RES4: 711 /* reserved */ 712 break; 713 } 714 715 return value; 716 } 717 718 static const MemoryRegionOps dbdma_ops = { 719 .read = dbdma_read, 720 .write = dbdma_write, 721 .endianness = DEVICE_LITTLE_ENDIAN, 722 .valid = { 723 .min_access_size = 4, 724 .max_access_size = 4, 725 }, 726 }; 727 728 static const VMStateDescription vmstate_dbdma_io = { 729 .name = "dbdma_io", 730 .version_id = 0, 731 .minimum_version_id = 0, 732 .fields = (VMStateField[]) { 733 VMSTATE_UINT64(addr, struct DBDMA_io), 734 VMSTATE_INT32(len, struct DBDMA_io), 735 VMSTATE_INT32(is_last, struct DBDMA_io), 736 VMSTATE_INT32(is_dma_out, struct DBDMA_io), 737 VMSTATE_BOOL(processing, struct DBDMA_io), 738 VMSTATE_END_OF_LIST() 739 } 740 }; 741 742 static const VMStateDescription vmstate_dbdma_cmd = { 743 .name = "dbdma_cmd", 744 .version_id = 0, 745 .minimum_version_id = 0, 746 .fields = (VMStateField[]) { 747 VMSTATE_UINT16(req_count, dbdma_cmd), 748 VMSTATE_UINT16(command, dbdma_cmd), 749 VMSTATE_UINT32(phy_addr, dbdma_cmd), 750 VMSTATE_UINT32(cmd_dep, dbdma_cmd), 751 VMSTATE_UINT16(res_count, dbdma_cmd), 752 VMSTATE_UINT16(xfer_status, dbdma_cmd), 753 VMSTATE_END_OF_LIST() 754 } 755 }; 756 757 static const VMStateDescription vmstate_dbdma_channel = { 758 .name = "dbdma_channel", 759 .version_id = 1, 760 .minimum_version_id = 1, 761 .fields = (VMStateField[]) { 762 VMSTATE_UINT32_ARRAY(regs, struct DBDMA_channel, DBDMA_REGS), 763 VMSTATE_STRUCT(io, struct DBDMA_channel, 0, vmstate_dbdma_io, DBDMA_io), 764 VMSTATE_STRUCT(current, struct DBDMA_channel, 0, vmstate_dbdma_cmd, 765 dbdma_cmd), 766 VMSTATE_END_OF_LIST() 767 } 768 }; 769 770 static const VMStateDescription vmstate_dbdma = { 771 .name = "dbdma", 772 .version_id = 3, 773 .minimum_version_id = 3, 774 .fields = (VMStateField[]) { 775 VMSTATE_STRUCT_ARRAY(channels, DBDMAState, DBDMA_CHANNELS, 1, 776 vmstate_dbdma_channel, DBDMA_channel), 777 VMSTATE_END_OF_LIST() 778 } 779 }; 780 781 static void dbdma_reset(void *opaque) 782 { 783 DBDMAState *s = opaque; 784 int i; 785 786 for (i = 0; i < DBDMA_CHANNELS; i++) 787 memset(s->channels[i].regs, 0, DBDMA_SIZE); 788 } 789 790 static void dbdma_unassigned_rw(DBDMA_io *io) 791 { 792 DBDMA_channel *ch = io->channel; 793 qemu_log_mask(LOG_GUEST_ERROR, "%s: use of unassigned channel %d\n", 794 __func__, ch->channel); 795 } 796 797 static void dbdma_unassigned_flush(DBDMA_io *io) 798 { 799 DBDMA_channel *ch = io->channel; 800 qemu_log_mask(LOG_GUEST_ERROR, "%s: use of unassigned channel %d\n", 801 __func__, ch->channel); 802 } 803 804 void* DBDMA_init (MemoryRegion **dbdma_mem) 805 { 806 DBDMAState *s; 807 int i; 808 809 s = g_malloc0(sizeof(DBDMAState)); 810 811 for (i = 0; i < DBDMA_CHANNELS; i++) { 812 DBDMA_io *io = &s->channels[i].io; 813 DBDMA_channel *ch = &s->channels[i]; 814 qemu_iovec_init(&io->iov, 1); 815 816 ch->rw = dbdma_unassigned_rw; 817 ch->flush = dbdma_unassigned_flush; 818 ch->channel = i; 819 ch->io.channel = ch; 820 } 821 822 memory_region_init_io(&s->mem, NULL, &dbdma_ops, s, "dbdma", 0x1000); 823 *dbdma_mem = &s->mem; 824 vmstate_register(NULL, -1, &vmstate_dbdma, s); 825 qemu_register_reset(dbdma_reset, s); 826 827 s->bh = qemu_bh_new(DBDMA_run_bh, s); 828 829 return s; 830 } 831