1 /* 2 * QEMU PowerMac CUDA device support 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/ppc/mac.h" 28 #include "hw/input/adb.h" 29 #include "hw/misc/mos6522.h" 30 #include "hw/misc/macio/cuda.h" 31 #include "qemu/timer.h" 32 #include "sysemu/sysemu.h" 33 #include "qemu/cutils.h" 34 #include "qemu/log.h" 35 #include "trace.h" 36 37 /* Bits in B data register: all active low */ 38 #define TREQ 0x08 /* Transfer request (input) */ 39 #define TACK 0x10 /* Transfer acknowledge (output) */ 40 #define TIP 0x20 /* Transfer in progress (output) */ 41 42 /* commands (1st byte) */ 43 #define ADB_PACKET 0 44 #define CUDA_PACKET 1 45 #define ERROR_PACKET 2 46 #define TIMER_PACKET 3 47 #define POWER_PACKET 4 48 #define MACIIC_PACKET 5 49 #define PMU_PACKET 6 50 51 #define CUDA_TIMER_FREQ (4700000 / 6) 52 53 /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */ 54 #define RTC_OFFSET 2082844800 55 56 static void cuda_receive_packet_from_host(CUDAState *s, 57 const uint8_t *data, int len); 58 59 /* MacOS uses timer 1 for calibration on startup, so we use 60 * the timebase frequency and cuda_get_counter_value() with 61 * cuda_get_load_time() to steer MacOS to calculate calibrate its timers 62 * correctly for both TCG and KVM (see commit b981289c49 "PPC: Cuda: Use cuda 63 * timer to expose tbfreq to guest" for more information) */ 64 65 static uint64_t cuda_get_counter_value(MOS6522State *s, MOS6522Timer *ti) 66 { 67 MOS6522CUDAState *mcs = container_of(s, MOS6522CUDAState, parent_obj); 68 CUDAState *cs = container_of(mcs, CUDAState, mos6522_cuda); 69 70 /* Reverse of the tb calculation algorithm that Mac OS X uses on bootup */ 71 uint64_t tb_diff = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 72 cs->tb_frequency, NANOSECONDS_PER_SECOND) - 73 ti->load_time; 74 75 return (tb_diff * 0xBF401675E5DULL) / (cs->tb_frequency << 24); 76 } 77 78 static uint64_t cuda_get_load_time(MOS6522State *s, MOS6522Timer *ti) 79 { 80 MOS6522CUDAState *mcs = container_of(s, MOS6522CUDAState, parent_obj); 81 CUDAState *cs = container_of(mcs, CUDAState, mos6522_cuda); 82 83 uint64_t load_time = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 84 cs->tb_frequency, NANOSECONDS_PER_SECOND); 85 return load_time; 86 } 87 88 static void cuda_set_sr_int(void *opaque) 89 { 90 CUDAState *s = opaque; 91 MOS6522CUDAState *mcs = &s->mos6522_cuda; 92 MOS6522State *ms = MOS6522(mcs); 93 MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(ms); 94 95 mdc->set_sr_int(ms); 96 } 97 98 static void cuda_delay_set_sr_int(CUDAState *s) 99 { 100 int64_t expire; 101 102 trace_cuda_delay_set_sr_int(); 103 104 expire = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->sr_delay_ns; 105 timer_mod(s->sr_delay_timer, expire); 106 } 107 108 /* NOTE: TIP and TREQ are negated */ 109 static void cuda_update(CUDAState *s) 110 { 111 MOS6522CUDAState *mcs = &s->mos6522_cuda; 112 MOS6522State *ms = MOS6522(mcs); 113 int packet_received, len; 114 115 packet_received = 0; 116 if (!(ms->b & TIP)) { 117 /* transfer requested from host */ 118 119 if (ms->acr & SR_OUT) { 120 /* data output */ 121 if ((ms->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) { 122 if (s->data_out_index < sizeof(s->data_out)) { 123 trace_cuda_data_send(ms->sr); 124 s->data_out[s->data_out_index++] = ms->sr; 125 cuda_delay_set_sr_int(s); 126 } 127 } 128 } else { 129 if (s->data_in_index < s->data_in_size) { 130 /* data input */ 131 if ((ms->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) { 132 ms->sr = s->data_in[s->data_in_index++]; 133 trace_cuda_data_recv(ms->sr); 134 /* indicate end of transfer */ 135 if (s->data_in_index >= s->data_in_size) { 136 ms->b = (ms->b | TREQ); 137 } 138 cuda_delay_set_sr_int(s); 139 } 140 } 141 } 142 } else { 143 /* no transfer requested: handle sync case */ 144 if ((s->last_b & TIP) && (ms->b & TACK) != (s->last_b & TACK)) { 145 /* update TREQ state each time TACK change state */ 146 if (ms->b & TACK) { 147 ms->b = (ms->b | TREQ); 148 } else { 149 ms->b = (ms->b & ~TREQ); 150 } 151 cuda_delay_set_sr_int(s); 152 } else { 153 if (!(s->last_b & TIP)) { 154 /* handle end of host to cuda transfer */ 155 packet_received = (s->data_out_index > 0); 156 /* always an IRQ at the end of transfer */ 157 cuda_delay_set_sr_int(s); 158 } 159 /* signal if there is data to read */ 160 if (s->data_in_index < s->data_in_size) { 161 ms->b = (ms->b & ~TREQ); 162 } 163 } 164 } 165 166 s->last_acr = ms->acr; 167 s->last_b = ms->b; 168 169 /* NOTE: cuda_receive_packet_from_host() can call cuda_update() 170 recursively */ 171 if (packet_received) { 172 len = s->data_out_index; 173 s->data_out_index = 0; 174 cuda_receive_packet_from_host(s, s->data_out, len); 175 } 176 } 177 178 static void cuda_send_packet_to_host(CUDAState *s, 179 const uint8_t *data, int len) 180 { 181 int i; 182 183 trace_cuda_packet_send(len); 184 for (i = 0; i < len; i++) { 185 trace_cuda_packet_send_data(i, data[i]); 186 } 187 188 memcpy(s->data_in, data, len); 189 s->data_in_size = len; 190 s->data_in_index = 0; 191 cuda_update(s); 192 cuda_delay_set_sr_int(s); 193 } 194 195 static void cuda_adb_poll(void *opaque) 196 { 197 CUDAState *s = opaque; 198 uint8_t obuf[ADB_MAX_OUT_LEN + 2]; 199 int olen; 200 201 olen = adb_poll(&s->adb_bus, obuf + 2, s->adb_poll_mask); 202 if (olen > 0) { 203 obuf[0] = ADB_PACKET; 204 obuf[1] = 0x40; /* polled data */ 205 cuda_send_packet_to_host(s, obuf, olen + 2); 206 } 207 timer_mod(s->adb_poll_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 208 (NANOSECONDS_PER_SECOND / (1000 / s->autopoll_rate_ms))); 209 } 210 211 /* description of commands */ 212 typedef struct CudaCommand { 213 uint8_t command; 214 const char *name; 215 bool (*handler)(CUDAState *s, 216 const uint8_t *in_args, int in_len, 217 uint8_t *out_args, int *out_len); 218 } CudaCommand; 219 220 static bool cuda_cmd_autopoll(CUDAState *s, 221 const uint8_t *in_data, int in_len, 222 uint8_t *out_data, int *out_len) 223 { 224 int autopoll; 225 226 if (in_len != 1) { 227 return false; 228 } 229 230 autopoll = (in_data[0] != 0); 231 if (autopoll != s->autopoll) { 232 s->autopoll = autopoll; 233 if (autopoll) { 234 timer_mod(s->adb_poll_timer, 235 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 236 (NANOSECONDS_PER_SECOND / (1000 / s->autopoll_rate_ms))); 237 } else { 238 timer_del(s->adb_poll_timer); 239 } 240 } 241 return true; 242 } 243 244 static bool cuda_cmd_set_autorate(CUDAState *s, 245 const uint8_t *in_data, int in_len, 246 uint8_t *out_data, int *out_len) 247 { 248 if (in_len != 1) { 249 return false; 250 } 251 252 /* we don't want a period of 0 ms */ 253 /* FIXME: check what real hardware does */ 254 if (in_data[0] == 0) { 255 return false; 256 } 257 258 s->autopoll_rate_ms = in_data[0]; 259 if (s->autopoll) { 260 timer_mod(s->adb_poll_timer, 261 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 262 (NANOSECONDS_PER_SECOND / (1000 / s->autopoll_rate_ms))); 263 } 264 return true; 265 } 266 267 static bool cuda_cmd_set_device_list(CUDAState *s, 268 const uint8_t *in_data, int in_len, 269 uint8_t *out_data, int *out_len) 270 { 271 if (in_len != 2) { 272 return false; 273 } 274 275 s->adb_poll_mask = (((uint16_t)in_data[0]) << 8) | in_data[1]; 276 return true; 277 } 278 279 static bool cuda_cmd_powerdown(CUDAState *s, 280 const uint8_t *in_data, int in_len, 281 uint8_t *out_data, int *out_len) 282 { 283 if (in_len != 0) { 284 return false; 285 } 286 287 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 288 return true; 289 } 290 291 static bool cuda_cmd_reset_system(CUDAState *s, 292 const uint8_t *in_data, int in_len, 293 uint8_t *out_data, int *out_len) 294 { 295 if (in_len != 0) { 296 return false; 297 } 298 299 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 300 return true; 301 } 302 303 static bool cuda_cmd_set_file_server_flag(CUDAState *s, 304 const uint8_t *in_data, int in_len, 305 uint8_t *out_data, int *out_len) 306 { 307 if (in_len != 1) { 308 return false; 309 } 310 311 qemu_log_mask(LOG_UNIMP, 312 "CUDA: unimplemented command FILE_SERVER_FLAG %d\n", 313 in_data[0]); 314 return true; 315 } 316 317 static bool cuda_cmd_set_power_message(CUDAState *s, 318 const uint8_t *in_data, int in_len, 319 uint8_t *out_data, int *out_len) 320 { 321 if (in_len != 1) { 322 return false; 323 } 324 325 qemu_log_mask(LOG_UNIMP, 326 "CUDA: unimplemented command SET_POWER_MESSAGE %d\n", 327 in_data[0]); 328 return true; 329 } 330 331 static bool cuda_cmd_get_time(CUDAState *s, 332 const uint8_t *in_data, int in_len, 333 uint8_t *out_data, int *out_len) 334 { 335 uint32_t ti; 336 337 if (in_len != 0) { 338 return false; 339 } 340 341 ti = s->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) 342 / NANOSECONDS_PER_SECOND); 343 out_data[0] = ti >> 24; 344 out_data[1] = ti >> 16; 345 out_data[2] = ti >> 8; 346 out_data[3] = ti; 347 *out_len = 4; 348 return true; 349 } 350 351 static bool cuda_cmd_set_time(CUDAState *s, 352 const uint8_t *in_data, int in_len, 353 uint8_t *out_data, int *out_len) 354 { 355 uint32_t ti; 356 357 if (in_len != 4) { 358 return false; 359 } 360 361 ti = (((uint32_t)in_data[0]) << 24) + (((uint32_t)in_data[1]) << 16) 362 + (((uint32_t)in_data[2]) << 8) + in_data[3]; 363 s->tick_offset = ti - (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) 364 / NANOSECONDS_PER_SECOND); 365 return true; 366 } 367 368 static const CudaCommand handlers[] = { 369 { CUDA_AUTOPOLL, "AUTOPOLL", cuda_cmd_autopoll }, 370 { CUDA_SET_AUTO_RATE, "SET_AUTO_RATE", cuda_cmd_set_autorate }, 371 { CUDA_SET_DEVICE_LIST, "SET_DEVICE_LIST", cuda_cmd_set_device_list }, 372 { CUDA_POWERDOWN, "POWERDOWN", cuda_cmd_powerdown }, 373 { CUDA_RESET_SYSTEM, "RESET_SYSTEM", cuda_cmd_reset_system }, 374 { CUDA_FILE_SERVER_FLAG, "FILE_SERVER_FLAG", 375 cuda_cmd_set_file_server_flag }, 376 { CUDA_SET_POWER_MESSAGES, "SET_POWER_MESSAGES", 377 cuda_cmd_set_power_message }, 378 { CUDA_GET_TIME, "GET_TIME", cuda_cmd_get_time }, 379 { CUDA_SET_TIME, "SET_TIME", cuda_cmd_set_time }, 380 }; 381 382 static void cuda_receive_packet(CUDAState *s, 383 const uint8_t *data, int len) 384 { 385 uint8_t obuf[16] = { CUDA_PACKET, 0, data[0] }; 386 int i, out_len = 0; 387 388 for (i = 0; i < ARRAY_SIZE(handlers); i++) { 389 const CudaCommand *desc = &handlers[i]; 390 if (desc->command == data[0]) { 391 trace_cuda_receive_packet_cmd(desc->name); 392 out_len = 0; 393 if (desc->handler(s, data + 1, len - 1, obuf + 3, &out_len)) { 394 cuda_send_packet_to_host(s, obuf, 3 + out_len); 395 } else { 396 qemu_log_mask(LOG_GUEST_ERROR, 397 "CUDA: %s: wrong parameters %d\n", 398 desc->name, len); 399 obuf[0] = ERROR_PACKET; 400 obuf[1] = 0x5; /* bad parameters */ 401 obuf[2] = CUDA_PACKET; 402 obuf[3] = data[0]; 403 cuda_send_packet_to_host(s, obuf, 4); 404 } 405 return; 406 } 407 } 408 409 qemu_log_mask(LOG_GUEST_ERROR, "CUDA: unknown command 0x%02x\n", data[0]); 410 obuf[0] = ERROR_PACKET; 411 obuf[1] = 0x2; /* unknown command */ 412 obuf[2] = CUDA_PACKET; 413 obuf[3] = data[0]; 414 cuda_send_packet_to_host(s, obuf, 4); 415 } 416 417 static void cuda_receive_packet_from_host(CUDAState *s, 418 const uint8_t *data, int len) 419 { 420 int i; 421 422 trace_cuda_packet_receive(len); 423 for (i = 0; i < len; i++) { 424 trace_cuda_packet_receive_data(i, data[i]); 425 } 426 427 switch(data[0]) { 428 case ADB_PACKET: 429 { 430 uint8_t obuf[ADB_MAX_OUT_LEN + 3]; 431 int olen; 432 olen = adb_request(&s->adb_bus, obuf + 2, data + 1, len - 1); 433 if (olen > 0) { 434 obuf[0] = ADB_PACKET; 435 obuf[1] = 0x00; 436 cuda_send_packet_to_host(s, obuf, olen + 2); 437 } else { 438 /* error */ 439 obuf[0] = ADB_PACKET; 440 obuf[1] = -olen; 441 obuf[2] = data[1]; 442 olen = 0; 443 cuda_send_packet_to_host(s, obuf, olen + 3); 444 } 445 } 446 break; 447 case CUDA_PACKET: 448 cuda_receive_packet(s, data + 1, len - 1); 449 break; 450 } 451 } 452 453 static uint64_t mos6522_cuda_read(void *opaque, hwaddr addr, unsigned size) 454 { 455 CUDAState *s = opaque; 456 MOS6522CUDAState *mcs = &s->mos6522_cuda; 457 MOS6522State *ms = MOS6522(mcs); 458 459 addr = (addr >> 9) & 0xf; 460 return mos6522_read(ms, addr, size); 461 } 462 463 static void mos6522_cuda_write(void *opaque, hwaddr addr, uint64_t val, 464 unsigned size) 465 { 466 CUDAState *s = opaque; 467 MOS6522CUDAState *mcs = &s->mos6522_cuda; 468 MOS6522State *ms = MOS6522(mcs); 469 470 addr = (addr >> 9) & 0xf; 471 mos6522_write(ms, addr, val, size); 472 } 473 474 static const MemoryRegionOps mos6522_cuda_ops = { 475 .read = mos6522_cuda_read, 476 .write = mos6522_cuda_write, 477 .endianness = DEVICE_BIG_ENDIAN, 478 .valid = { 479 .min_access_size = 1, 480 .max_access_size = 1, 481 }, 482 }; 483 484 static const VMStateDescription vmstate_cuda = { 485 .name = "cuda", 486 .version_id = 5, 487 .minimum_version_id = 5, 488 .fields = (VMStateField[]) { 489 VMSTATE_STRUCT(mos6522_cuda.parent_obj, CUDAState, 0, vmstate_mos6522, 490 MOS6522State), 491 VMSTATE_UINT8(last_b, CUDAState), 492 VMSTATE_UINT8(last_acr, CUDAState), 493 VMSTATE_INT32(data_in_size, CUDAState), 494 VMSTATE_INT32(data_in_index, CUDAState), 495 VMSTATE_INT32(data_out_index, CUDAState), 496 VMSTATE_UINT8(autopoll, CUDAState), 497 VMSTATE_UINT8(autopoll_rate_ms, CUDAState), 498 VMSTATE_UINT16(adb_poll_mask, CUDAState), 499 VMSTATE_BUFFER(data_in, CUDAState), 500 VMSTATE_BUFFER(data_out, CUDAState), 501 VMSTATE_UINT32(tick_offset, CUDAState), 502 VMSTATE_TIMER_PTR(adb_poll_timer, CUDAState), 503 VMSTATE_TIMER_PTR(sr_delay_timer, CUDAState), 504 VMSTATE_END_OF_LIST() 505 } 506 }; 507 508 static void cuda_reset(DeviceState *dev) 509 { 510 CUDAState *s = CUDA(dev); 511 512 s->data_in_size = 0; 513 s->data_in_index = 0; 514 s->data_out_index = 0; 515 s->autopoll = 0; 516 } 517 518 static void cuda_realize(DeviceState *dev, Error **errp) 519 { 520 CUDAState *s = CUDA(dev); 521 SysBusDevice *sbd; 522 MOS6522State *ms; 523 DeviceState *d; 524 struct tm tm; 525 526 /* Pass IRQ from 6522 */ 527 d = DEVICE(&s->mos6522_cuda); 528 ms = MOS6522(d); 529 sbd = SYS_BUS_DEVICE(s); 530 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(ms)); 531 532 qemu_get_timedate(&tm, 0); 533 s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; 534 535 s->sr_delay_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_set_sr_int, s); 536 s->sr_delay_ns = 20 * SCALE_US; 537 538 s->adb_poll_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_adb_poll, s); 539 s->adb_poll_mask = 0xffff; 540 s->autopoll_rate_ms = 20; 541 } 542 543 static void cuda_init(Object *obj) 544 { 545 CUDAState *s = CUDA(obj); 546 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 547 548 sysbus_init_child_obj(obj, "mos6522-cuda", &s->mos6522_cuda, 549 sizeof(s->mos6522_cuda), TYPE_MOS6522_CUDA); 550 551 memory_region_init_io(&s->mem, obj, &mos6522_cuda_ops, s, "cuda", 0x2000); 552 sysbus_init_mmio(sbd, &s->mem); 553 554 qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS, 555 DEVICE(obj), "adb.0"); 556 } 557 558 static Property cuda_properties[] = { 559 DEFINE_PROP_UINT64("timebase-frequency", CUDAState, tb_frequency, 0), 560 DEFINE_PROP_END_OF_LIST() 561 }; 562 563 static void cuda_class_init(ObjectClass *oc, void *data) 564 { 565 DeviceClass *dc = DEVICE_CLASS(oc); 566 567 dc->realize = cuda_realize; 568 dc->reset = cuda_reset; 569 dc->vmsd = &vmstate_cuda; 570 dc->props = cuda_properties; 571 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 572 } 573 574 static const TypeInfo cuda_type_info = { 575 .name = TYPE_CUDA, 576 .parent = TYPE_SYS_BUS_DEVICE, 577 .instance_size = sizeof(CUDAState), 578 .instance_init = cuda_init, 579 .class_init = cuda_class_init, 580 }; 581 582 static void mos6522_cuda_portB_write(MOS6522State *s) 583 { 584 MOS6522CUDAState *mcs = container_of(s, MOS6522CUDAState, parent_obj); 585 CUDAState *cs = container_of(mcs, CUDAState, mos6522_cuda); 586 587 cuda_update(cs); 588 } 589 590 static void mos6522_cuda_reset(DeviceState *dev) 591 { 592 MOS6522State *ms = MOS6522(dev); 593 MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(ms); 594 595 mdc->parent_reset(dev); 596 597 ms->timers[0].frequency = CUDA_TIMER_FREQ; 598 ms->timers[1].frequency = (SCALE_US * 6000) / 4700; 599 } 600 601 static void mos6522_cuda_class_init(ObjectClass *oc, void *data) 602 { 603 DeviceClass *dc = DEVICE_CLASS(oc); 604 MOS6522DeviceClass *mdc = MOS6522_DEVICE_CLASS(oc); 605 606 dc->reset = mos6522_cuda_reset; 607 mdc->portB_write = mos6522_cuda_portB_write; 608 mdc->get_timer1_counter_value = cuda_get_counter_value; 609 mdc->get_timer2_counter_value = cuda_get_counter_value; 610 mdc->get_timer1_load_time = cuda_get_load_time; 611 mdc->get_timer2_load_time = cuda_get_load_time; 612 } 613 614 static const TypeInfo mos6522_cuda_type_info = { 615 .name = TYPE_MOS6522_CUDA, 616 .parent = TYPE_MOS6522, 617 .instance_size = sizeof(MOS6522CUDAState), 618 .class_init = mos6522_cuda_class_init, 619 }; 620 621 static void cuda_register_types(void) 622 { 623 type_register_static(&mos6522_cuda_type_info); 624 type_register_static(&cuda_type_info); 625 } 626 627 type_init(cuda_register_types) 628