1 /* 2 * QEMU PowerMac CUDA device support 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/irq.h" 28 #include "hw/qdev-properties.h" 29 #include "migration/vmstate.h" 30 #include "hw/misc/macio/cuda.h" 31 #include "qapi/error.h" 32 #include "qemu/timer.h" 33 #include "sysemu/runstate.h" 34 #include "sysemu/rtc.h" 35 #include "qapi/error.h" 36 #include "qemu/cutils.h" 37 #include "qemu/log.h" 38 #include "qemu/module.h" 39 #include "trace.h" 40 41 /* Bits in B data register: all active low */ 42 #define TREQ 0x08 /* Transfer request (input) */ 43 #define TACK 0x10 /* Transfer acknowledge (output) */ 44 #define TIP 0x20 /* Transfer in progress (output) */ 45 46 /* commands (1st byte) */ 47 #define ADB_PACKET 0 48 #define CUDA_PACKET 1 49 #define ERROR_PACKET 2 50 #define TIMER_PACKET 3 51 #define POWER_PACKET 4 52 #define MACIIC_PACKET 5 53 #define PMU_PACKET 6 54 55 #define CUDA_TIMER_FREQ (4700000 / 6) 56 57 /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */ 58 #define RTC_OFFSET 2082844800 59 60 static void cuda_receive_packet_from_host(CUDAState *s, 61 const uint8_t *data, int len); 62 63 /* MacOS uses timer 1 for calibration on startup, so we use 64 * the timebase frequency and cuda_get_counter_value() with 65 * cuda_get_load_time() to steer MacOS to calculate calibrate its timers 66 * correctly for both TCG and KVM (see commit b981289c49 "PPC: Cuda: Use cuda 67 * timer to expose tbfreq to guest" for more information) */ 68 69 static uint64_t cuda_get_counter_value(MOS6522State *s, MOS6522Timer *ti) 70 { 71 MOS6522CUDAState *mcs = container_of(s, MOS6522CUDAState, parent_obj); 72 CUDAState *cs = container_of(mcs, CUDAState, mos6522_cuda); 73 74 /* Reverse of the tb calculation algorithm that Mac OS X uses on bootup */ 75 uint64_t tb_diff = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 76 cs->tb_frequency, NANOSECONDS_PER_SECOND) - 77 ti->load_time; 78 79 return (tb_diff * 0xBF401675E5DULL) / (cs->tb_frequency << 24); 80 } 81 82 static uint64_t cuda_get_load_time(MOS6522State *s, MOS6522Timer *ti) 83 { 84 MOS6522CUDAState *mcs = container_of(s, MOS6522CUDAState, parent_obj); 85 CUDAState *cs = container_of(mcs, CUDAState, mos6522_cuda); 86 87 uint64_t load_time = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 88 cs->tb_frequency, NANOSECONDS_PER_SECOND); 89 return load_time; 90 } 91 92 static void cuda_set_sr_int(void *opaque) 93 { 94 CUDAState *s = opaque; 95 MOS6522CUDAState *mcs = &s->mos6522_cuda; 96 MOS6522State *ms = MOS6522(mcs); 97 qemu_irq irq = qdev_get_gpio_in(DEVICE(ms), SR_INT_BIT); 98 99 qemu_set_irq(irq, 1); 100 } 101 102 static void cuda_delay_set_sr_int(CUDAState *s) 103 { 104 int64_t expire; 105 106 trace_cuda_delay_set_sr_int(); 107 108 expire = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->sr_delay_ns; 109 timer_mod(s->sr_delay_timer, expire); 110 } 111 112 /* NOTE: TIP and TREQ are negated */ 113 static void cuda_update(CUDAState *s) 114 { 115 MOS6522CUDAState *mcs = &s->mos6522_cuda; 116 MOS6522State *ms = MOS6522(mcs); 117 ADBBusState *adb_bus = &s->adb_bus; 118 int packet_received, len; 119 120 packet_received = 0; 121 if (!(ms->b & TIP)) { 122 /* transfer requested from host */ 123 124 if (ms->acr & SR_OUT) { 125 /* data output */ 126 if ((ms->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) { 127 if (s->data_out_index < sizeof(s->data_out)) { 128 if (s->data_out_index == 0) { 129 adb_autopoll_block(adb_bus); 130 } 131 trace_cuda_data_send(ms->sr); 132 s->data_out[s->data_out_index++] = ms->sr; 133 cuda_delay_set_sr_int(s); 134 } 135 } 136 } else { 137 if (s->data_in_index < s->data_in_size) { 138 /* data input */ 139 if ((ms->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) { 140 ms->sr = s->data_in[s->data_in_index++]; 141 trace_cuda_data_recv(ms->sr); 142 /* indicate end of transfer */ 143 if (s->data_in_index >= s->data_in_size) { 144 ms->b = (ms->b | TREQ); 145 adb_autopoll_unblock(adb_bus); 146 } 147 cuda_delay_set_sr_int(s); 148 } 149 } 150 } 151 } else { 152 /* no transfer requested: handle sync case */ 153 if ((s->last_b & TIP) && (ms->b & TACK) != (s->last_b & TACK)) { 154 /* update TREQ state each time TACK change state */ 155 if (ms->b & TACK) { 156 ms->b = (ms->b | TREQ); 157 } else { 158 ms->b = (ms->b & ~TREQ); 159 } 160 cuda_delay_set_sr_int(s); 161 } else { 162 if (!(s->last_b & TIP)) { 163 /* handle end of host to cuda transfer */ 164 packet_received = (s->data_out_index > 0); 165 /* always an IRQ at the end of transfer */ 166 cuda_delay_set_sr_int(s); 167 } 168 /* signal if there is data to read */ 169 if (s->data_in_index < s->data_in_size) { 170 ms->b = (ms->b & ~TREQ); 171 } 172 } 173 } 174 175 s->last_acr = ms->acr; 176 s->last_b = ms->b; 177 178 /* NOTE: cuda_receive_packet_from_host() can call cuda_update() 179 recursively */ 180 if (packet_received) { 181 len = s->data_out_index; 182 s->data_out_index = 0; 183 cuda_receive_packet_from_host(s, s->data_out, len); 184 } 185 } 186 187 static void cuda_send_packet_to_host(CUDAState *s, 188 const uint8_t *data, int len) 189 { 190 int i; 191 192 trace_cuda_packet_send(len); 193 for (i = 0; i < len; i++) { 194 trace_cuda_packet_send_data(i, data[i]); 195 } 196 197 memcpy(s->data_in, data, len); 198 s->data_in_size = len; 199 s->data_in_index = 0; 200 cuda_update(s); 201 cuda_delay_set_sr_int(s); 202 } 203 204 static void cuda_adb_poll(void *opaque) 205 { 206 CUDAState *s = opaque; 207 ADBBusState *adb_bus = &s->adb_bus; 208 uint8_t obuf[ADB_MAX_OUT_LEN + 2]; 209 int olen; 210 211 olen = adb_poll(adb_bus, obuf + 2, adb_bus->autopoll_mask); 212 if (olen > 0) { 213 obuf[0] = ADB_PACKET; 214 obuf[1] = 0x40; /* polled data */ 215 cuda_send_packet_to_host(s, obuf, olen + 2); 216 } 217 } 218 219 /* description of commands */ 220 typedef struct CudaCommand { 221 uint8_t command; 222 const char *name; 223 bool (*handler)(CUDAState *s, 224 const uint8_t *in_args, int in_len, 225 uint8_t *out_args, int *out_len); 226 } CudaCommand; 227 228 static bool cuda_cmd_autopoll(CUDAState *s, 229 const uint8_t *in_data, int in_len, 230 uint8_t *out_data, int *out_len) 231 { 232 ADBBusState *adb_bus = &s->adb_bus; 233 bool autopoll; 234 235 if (in_len != 1) { 236 return false; 237 } 238 239 autopoll = (in_data[0] != 0) ? true : false; 240 241 adb_set_autopoll_enabled(adb_bus, autopoll); 242 return true; 243 } 244 245 static bool cuda_cmd_set_autorate(CUDAState *s, 246 const uint8_t *in_data, int in_len, 247 uint8_t *out_data, int *out_len) 248 { 249 ADBBusState *adb_bus = &s->adb_bus; 250 251 if (in_len != 1) { 252 return false; 253 } 254 255 /* we don't want a period of 0 ms */ 256 /* FIXME: check what real hardware does */ 257 if (in_data[0] == 0) { 258 return false; 259 } 260 261 adb_set_autopoll_rate_ms(adb_bus, in_data[0]); 262 return true; 263 } 264 265 static bool cuda_cmd_set_device_list(CUDAState *s, 266 const uint8_t *in_data, int in_len, 267 uint8_t *out_data, int *out_len) 268 { 269 ADBBusState *adb_bus = &s->adb_bus; 270 uint16_t mask; 271 272 if (in_len != 2) { 273 return false; 274 } 275 276 mask = (((uint16_t)in_data[0]) << 8) | in_data[1]; 277 278 adb_set_autopoll_mask(adb_bus, mask); 279 return true; 280 } 281 282 static bool cuda_cmd_powerdown(CUDAState *s, 283 const uint8_t *in_data, int in_len, 284 uint8_t *out_data, int *out_len) 285 { 286 if (in_len != 0) { 287 return false; 288 } 289 290 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 291 return true; 292 } 293 294 static bool cuda_cmd_reset_system(CUDAState *s, 295 const uint8_t *in_data, int in_len, 296 uint8_t *out_data, int *out_len) 297 { 298 if (in_len != 0) { 299 return false; 300 } 301 302 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 303 return true; 304 } 305 306 static bool cuda_cmd_set_file_server_flag(CUDAState *s, 307 const uint8_t *in_data, int in_len, 308 uint8_t *out_data, int *out_len) 309 { 310 if (in_len != 1) { 311 return false; 312 } 313 314 qemu_log_mask(LOG_UNIMP, 315 "CUDA: unimplemented command FILE_SERVER_FLAG %d\n", 316 in_data[0]); 317 return true; 318 } 319 320 static bool cuda_cmd_set_power_message(CUDAState *s, 321 const uint8_t *in_data, int in_len, 322 uint8_t *out_data, int *out_len) 323 { 324 if (in_len != 1) { 325 return false; 326 } 327 328 qemu_log_mask(LOG_UNIMP, 329 "CUDA: unimplemented command SET_POWER_MESSAGE %d\n", 330 in_data[0]); 331 return true; 332 } 333 334 static bool cuda_cmd_get_time(CUDAState *s, 335 const uint8_t *in_data, int in_len, 336 uint8_t *out_data, int *out_len) 337 { 338 uint32_t ti; 339 340 if (in_len != 0) { 341 return false; 342 } 343 344 ti = s->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) 345 / NANOSECONDS_PER_SECOND); 346 out_data[0] = ti >> 24; 347 out_data[1] = ti >> 16; 348 out_data[2] = ti >> 8; 349 out_data[3] = ti; 350 *out_len = 4; 351 return true; 352 } 353 354 static bool cuda_cmd_set_time(CUDAState *s, 355 const uint8_t *in_data, int in_len, 356 uint8_t *out_data, int *out_len) 357 { 358 uint32_t ti; 359 360 if (in_len != 4) { 361 return false; 362 } 363 364 ti = (((uint32_t)in_data[0]) << 24) + (((uint32_t)in_data[1]) << 16) 365 + (((uint32_t)in_data[2]) << 8) + in_data[3]; 366 s->tick_offset = ti - (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) 367 / NANOSECONDS_PER_SECOND); 368 return true; 369 } 370 371 static const CudaCommand handlers[] = { 372 { CUDA_AUTOPOLL, "AUTOPOLL", cuda_cmd_autopoll }, 373 { CUDA_SET_AUTO_RATE, "SET_AUTO_RATE", cuda_cmd_set_autorate }, 374 { CUDA_SET_DEVICE_LIST, "SET_DEVICE_LIST", cuda_cmd_set_device_list }, 375 { CUDA_POWERDOWN, "POWERDOWN", cuda_cmd_powerdown }, 376 { CUDA_RESET_SYSTEM, "RESET_SYSTEM", cuda_cmd_reset_system }, 377 { CUDA_FILE_SERVER_FLAG, "FILE_SERVER_FLAG", 378 cuda_cmd_set_file_server_flag }, 379 { CUDA_SET_POWER_MESSAGES, "SET_POWER_MESSAGES", 380 cuda_cmd_set_power_message }, 381 { CUDA_GET_TIME, "GET_TIME", cuda_cmd_get_time }, 382 { CUDA_SET_TIME, "SET_TIME", cuda_cmd_set_time }, 383 }; 384 385 static void cuda_receive_packet(CUDAState *s, 386 const uint8_t *data, int len) 387 { 388 uint8_t obuf[16] = { CUDA_PACKET, 0, data[0] }; 389 int i, out_len = 0; 390 391 for (i = 0; i < ARRAY_SIZE(handlers); i++) { 392 const CudaCommand *desc = &handlers[i]; 393 if (desc->command == data[0]) { 394 trace_cuda_receive_packet_cmd(desc->name); 395 out_len = 0; 396 if (desc->handler(s, data + 1, len - 1, obuf + 3, &out_len)) { 397 cuda_send_packet_to_host(s, obuf, 3 + out_len); 398 } else { 399 qemu_log_mask(LOG_GUEST_ERROR, 400 "CUDA: %s: wrong parameters %d\n", 401 desc->name, len); 402 obuf[0] = ERROR_PACKET; 403 obuf[1] = 0x5; /* bad parameters */ 404 obuf[2] = CUDA_PACKET; 405 obuf[3] = data[0]; 406 cuda_send_packet_to_host(s, obuf, 4); 407 } 408 return; 409 } 410 } 411 412 qemu_log_mask(LOG_GUEST_ERROR, "CUDA: unknown command 0x%02x\n", data[0]); 413 obuf[0] = ERROR_PACKET; 414 obuf[1] = 0x2; /* unknown command */ 415 obuf[2] = CUDA_PACKET; 416 obuf[3] = data[0]; 417 cuda_send_packet_to_host(s, obuf, 4); 418 } 419 420 static void cuda_receive_packet_from_host(CUDAState *s, 421 const uint8_t *data, int len) 422 { 423 int i; 424 425 trace_cuda_packet_receive(len); 426 for (i = 0; i < len; i++) { 427 trace_cuda_packet_receive_data(i, data[i]); 428 } 429 430 switch(data[0]) { 431 case ADB_PACKET: 432 { 433 uint8_t obuf[ADB_MAX_OUT_LEN + 3]; 434 int olen; 435 olen = adb_request(&s->adb_bus, obuf + 2, data + 1, len - 1); 436 if (olen > 0) { 437 obuf[0] = ADB_PACKET; 438 obuf[1] = 0x00; 439 cuda_send_packet_to_host(s, obuf, olen + 2); 440 } else { 441 /* error */ 442 obuf[0] = ADB_PACKET; 443 obuf[1] = -olen; 444 obuf[2] = data[1]; 445 olen = 0; 446 cuda_send_packet_to_host(s, obuf, olen + 3); 447 } 448 } 449 break; 450 case CUDA_PACKET: 451 cuda_receive_packet(s, data + 1, len - 1); 452 break; 453 } 454 } 455 456 static uint64_t mos6522_cuda_read(void *opaque, hwaddr addr, unsigned size) 457 { 458 CUDAState *s = opaque; 459 MOS6522CUDAState *mcs = &s->mos6522_cuda; 460 MOS6522State *ms = MOS6522(mcs); 461 462 addr = (addr >> 9) & 0xf; 463 return mos6522_read(ms, addr, size); 464 } 465 466 static void mos6522_cuda_write(void *opaque, hwaddr addr, uint64_t val, 467 unsigned size) 468 { 469 CUDAState *s = opaque; 470 MOS6522CUDAState *mcs = &s->mos6522_cuda; 471 MOS6522State *ms = MOS6522(mcs); 472 473 addr = (addr >> 9) & 0xf; 474 mos6522_write(ms, addr, val, size); 475 } 476 477 static const MemoryRegionOps mos6522_cuda_ops = { 478 .read = mos6522_cuda_read, 479 .write = mos6522_cuda_write, 480 .endianness = DEVICE_BIG_ENDIAN, 481 .valid = { 482 .min_access_size = 1, 483 .max_access_size = 1, 484 }, 485 }; 486 487 static const VMStateDescription vmstate_cuda = { 488 .name = "cuda", 489 .version_id = 6, 490 .minimum_version_id = 6, 491 .fields = (VMStateField[]) { 492 VMSTATE_STRUCT(mos6522_cuda.parent_obj, CUDAState, 0, vmstate_mos6522, 493 MOS6522State), 494 VMSTATE_UINT8(last_b, CUDAState), 495 VMSTATE_UINT8(last_acr, CUDAState), 496 VMSTATE_INT32(data_in_size, CUDAState), 497 VMSTATE_INT32(data_in_index, CUDAState), 498 VMSTATE_INT32(data_out_index, CUDAState), 499 VMSTATE_BUFFER(data_in, CUDAState), 500 VMSTATE_BUFFER(data_out, CUDAState), 501 VMSTATE_UINT32(tick_offset, CUDAState), 502 VMSTATE_TIMER_PTR(sr_delay_timer, CUDAState), 503 VMSTATE_END_OF_LIST() 504 } 505 }; 506 507 static void cuda_reset(DeviceState *dev) 508 { 509 CUDAState *s = CUDA(dev); 510 ADBBusState *adb_bus = &s->adb_bus; 511 512 s->data_in_size = 0; 513 s->data_in_index = 0; 514 s->data_out_index = 0; 515 516 adb_set_autopoll_enabled(adb_bus, false); 517 } 518 519 static void cuda_realize(DeviceState *dev, Error **errp) 520 { 521 CUDAState *s = CUDA(dev); 522 SysBusDevice *sbd; 523 ADBBusState *adb_bus = &s->adb_bus; 524 struct tm tm; 525 526 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mos6522_cuda), errp)) { 527 return; 528 } 529 530 /* Pass IRQ from 6522 */ 531 sbd = SYS_BUS_DEVICE(s); 532 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->mos6522_cuda)); 533 534 qemu_get_timedate(&tm, 0); 535 s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; 536 537 s->sr_delay_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_set_sr_int, s); 538 s->sr_delay_ns = 20 * SCALE_US; 539 540 adb_register_autopoll_callback(adb_bus, cuda_adb_poll, s); 541 } 542 543 static void cuda_init(Object *obj) 544 { 545 CUDAState *s = CUDA(obj); 546 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 547 548 object_initialize_child(obj, "mos6522-cuda", &s->mos6522_cuda, 549 TYPE_MOS6522_CUDA); 550 551 memory_region_init_io(&s->mem, obj, &mos6522_cuda_ops, s, "cuda", 0x2000); 552 sysbus_init_mmio(sbd, &s->mem); 553 554 qbus_init(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS, 555 DEVICE(obj), "adb.0"); 556 } 557 558 static Property cuda_properties[] = { 559 DEFINE_PROP_UINT64("timebase-frequency", CUDAState, tb_frequency, 0), 560 DEFINE_PROP_END_OF_LIST() 561 }; 562 563 static void cuda_class_init(ObjectClass *oc, void *data) 564 { 565 DeviceClass *dc = DEVICE_CLASS(oc); 566 567 dc->realize = cuda_realize; 568 dc->reset = cuda_reset; 569 dc->vmsd = &vmstate_cuda; 570 device_class_set_props(dc, cuda_properties); 571 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 572 } 573 574 static const TypeInfo cuda_type_info = { 575 .name = TYPE_CUDA, 576 .parent = TYPE_SYS_BUS_DEVICE, 577 .instance_size = sizeof(CUDAState), 578 .instance_init = cuda_init, 579 .class_init = cuda_class_init, 580 }; 581 582 static void mos6522_cuda_portB_write(MOS6522State *s) 583 { 584 MOS6522CUDAState *mcs = container_of(s, MOS6522CUDAState, parent_obj); 585 CUDAState *cs = container_of(mcs, CUDAState, mos6522_cuda); 586 587 cuda_update(cs); 588 } 589 590 static void mos6522_cuda_reset_hold(Object *obj) 591 { 592 MOS6522State *ms = MOS6522(obj); 593 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); 594 595 if (mdc->parent_phases.hold) { 596 mdc->parent_phases.hold(obj); 597 } 598 599 ms->timers[0].frequency = CUDA_TIMER_FREQ; 600 ms->timers[1].frequency = (SCALE_US * 6000) / 4700; 601 } 602 603 static void mos6522_cuda_class_init(ObjectClass *oc, void *data) 604 { 605 ResettableClass *rc = RESETTABLE_CLASS(oc); 606 MOS6522DeviceClass *mdc = MOS6522_CLASS(oc); 607 608 resettable_class_set_parent_phases(rc, NULL, mos6522_cuda_reset_hold, 609 NULL, &mdc->parent_phases); 610 mdc->portB_write = mos6522_cuda_portB_write; 611 mdc->get_timer1_counter_value = cuda_get_counter_value; 612 mdc->get_timer2_counter_value = cuda_get_counter_value; 613 mdc->get_timer1_load_time = cuda_get_load_time; 614 mdc->get_timer2_load_time = cuda_get_load_time; 615 } 616 617 static const TypeInfo mos6522_cuda_type_info = { 618 .name = TYPE_MOS6522_CUDA, 619 .parent = TYPE_MOS6522, 620 .instance_size = sizeof(MOS6522CUDAState), 621 .class_init = mos6522_cuda_class_init, 622 }; 623 624 static void cuda_register_types(void) 625 { 626 type_register_static(&mos6522_cuda_type_info); 627 type_register_static(&cuda_type_info); 628 } 629 630 type_init(cuda_register_types) 631