1 /* 2 * QEMU m68k Macintosh VIA device support 3 * 4 * Copyright (c) 2011-2018 Laurent Vivier 5 * Copyright (c) 2018 Mark Cave-Ayland 6 * 7 * Some parts from hw/misc/macio/cuda.c 8 * 9 * Copyright (c) 2004-2007 Fabrice Bellard 10 * Copyright (c) 2007 Jocelyn Mayer 11 * 12 * some parts from linux-2.6.29, arch/m68k/include/asm/mac_via.h 13 * 14 * This work is licensed under the terms of the GNU GPL, version 2 or later. 15 * See the COPYING file in the top-level directory. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "migration/vmstate.h" 20 #include "hw/sysbus.h" 21 #include "hw/irq.h" 22 #include "qemu/timer.h" 23 #include "hw/misc/mac_via.h" 24 #include "hw/misc/mos6522.h" 25 #include "hw/input/adb.h" 26 #include "sysemu/runstate.h" 27 #include "qapi/error.h" 28 #include "qemu/cutils.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/qdev-properties-system.h" 31 #include "sysemu/block-backend.h" 32 #include "sysemu/rtc.h" 33 #include "trace.h" 34 #include "qemu/log.h" 35 36 /* 37 * VIAs: There are two in every machine 38 */ 39 40 /* 41 * Not all of these are true post MacII I think. 42 * CSA: probably the ones CHRP marks as 'unused' change purposes 43 * when the IWM becomes the SWIM. 44 * http://www.rs6000.ibm.com/resource/technology/chrpio/via5.mak.html 45 * ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf 46 * 47 * also, http://developer.apple.com/technotes/hw/hw_09.html claims the 48 * following changes for IIfx: 49 * VIA1A_vSccWrReq not available and that VIA1A_vSync has moved to an IOP. 50 * Also, "All of the functionality of VIA2 has been moved to other chips". 51 */ 52 53 #define VIA1A_vSccWrReq 0x80 /* 54 * SCC write. (input) 55 * [CHRP] SCC WREQ: Reflects the state of the 56 * Wait/Request pins from the SCC. 57 * [Macintosh Family Hardware] 58 * as CHRP on SE/30,II,IIx,IIcx,IIci. 59 * on IIfx, "0 means an active request" 60 */ 61 #define VIA1A_vRev8 0x40 /* 62 * Revision 8 board ??? 63 * [CHRP] En WaitReqB: Lets the WaitReq_L 64 * signal from port B of the SCC appear on 65 * the PA7 input pin. Output. 66 * [Macintosh Family] On the SE/30, this 67 * is the bit to flip screen buffers. 68 * 0=alternate, 1=main. 69 * on II,IIx,IIcx,IIci,IIfx this is a bit 70 * for Rev ID. 0=II,IIx, 1=IIcx,IIci,IIfx 71 */ 72 #define VIA1A_vHeadSel 0x20 /* 73 * Head select for IWM. 74 * [CHRP] unused. 75 * [Macintosh Family] "Floppy disk 76 * state-control line SEL" on all but IIfx 77 */ 78 #define VIA1A_vOverlay 0x10 /* 79 * [Macintosh Family] On SE/30,II,IIx,IIcx 80 * this bit enables the "Overlay" address 81 * map in the address decoders as it is on 82 * reset for mapping the ROM over the reset 83 * vector. 1=use overlay map. 84 * On the IIci,IIfx it is another bit of the 85 * CPU ID: 0=normal IIci, 1=IIci with parity 86 * feature or IIfx. 87 * [CHRP] En WaitReqA: Lets the WaitReq_L 88 * signal from port A of the SCC appear 89 * on the PA7 input pin (CHRP). Output. 90 * [MkLinux] "Drive Select" 91 * (with 0x20 being 'disk head select') 92 */ 93 #define VIA1A_vSync 0x08 /* 94 * [CHRP] Sync Modem: modem clock select: 95 * 1: select the external serial clock to 96 * drive the SCC's /RTxCA pin. 97 * 0: Select the 3.6864MHz clock to drive 98 * the SCC cell. 99 * [Macintosh Family] Correct on all but IIfx 100 */ 101 102 /* 103 * Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control 104 * on Macs which had the PWM sound hardware. Reserved on newer models. 105 * On IIci,IIfx, bits 1-2 are the rest of the CPU ID: 106 * bit 2: 1=IIci, 0=IIfx 107 * bit 1: 1 on both IIci and IIfx. 108 * MkLinux sez bit 0 is 'burnin flag' in this case. 109 * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as 110 * inputs, these bits will read 0. 111 */ 112 #define VIA1A_vVolume 0x07 /* Audio volume mask for PWM */ 113 #define VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */ 114 #define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */ 115 #define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */ 116 #define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */ 117 118 /* 119 * Info on VIA1B is from Macintosh Family Hardware & MkLinux. 120 * CHRP offers no info. 121 */ 122 #define VIA1B_vSound 0x80 /* 123 * Sound enable (for compatibility with 124 * PWM hardware) 0=enabled. 125 * Also, on IIci w/parity, shows parity error 126 * 0=error, 1=OK. 127 */ 128 #define VIA1B_vMystery 0x40 /* 129 * On IIci, parity enable. 0=enabled,1=disabled 130 * On SE/30, vertical sync interrupt enable. 131 * 0=enabled. This vSync interrupt shows up 132 * as a slot $E interrupt. 133 * On Quadra 800 this bit toggles A/UX mode which 134 * configures the glue logic to deliver some IRQs 135 * at different levels compared to a classic 136 * Mac. 137 */ 138 #define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */ 139 #define VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */ 140 #define VIA1B_vADBInt 0x08 /* ADB interrupt 0=interrupt (unused on IIfx)*/ 141 #define VIA1B_vRTCEnb 0x04 /* Enable Real time clock. 0=enabled. */ 142 #define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */ 143 #define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */ 144 145 /* 146 * VIA2 A register is the interrupt lines raised off the nubus 147 * slots. 148 * The below info is from 'Macintosh Family Hardware.' 149 * MkLinux calls the 'IIci internal video IRQ' below the 'RBV slot 0 irq.' 150 * It also notes that the slot $9 IRQ is the 'Ethernet IRQ' and 151 * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike. 152 * Perhaps OSS uses vRAM1 and vRAM2 for ADB. 153 */ 154 155 #define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */ 156 #define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ) */ 157 #define VIA2A_vIRQE 0x20 /* IRQ from slot $E */ 158 #define VIA2A_vIRQD 0x10 /* IRQ from slot $D */ 159 #define VIA2A_vIRQC 0x08 /* IRQ from slot $C */ 160 #define VIA2A_vIRQB 0x04 /* IRQ from slot $B */ 161 #define VIA2A_vIRQA 0x02 /* IRQ from slot $A */ 162 #define VIA2A_vIRQ9 0x01 /* IRQ from slot $9 */ 163 164 /* 165 * RAM size bits decoded as follows: 166 * bit1 bit0 size of ICs in bank A 167 * 0 0 256 kbit 168 * 0 1 1 Mbit 169 * 1 0 4 Mbit 170 * 1 1 16 Mbit 171 */ 172 173 /* 174 * Register B has the fun stuff in it 175 */ 176 177 #define VIA2B_vVBL 0x80 /* 178 * VBL output to VIA1 (60.15Hz) driven by 179 * timer T1. 180 * on IIci, parity test: 0=test mode. 181 * [MkLinux] RBV_PARODD: 1=odd,0=even. 182 */ 183 #define VIA2B_vSndJck 0x40 /* 184 * External sound jack status. 185 * 0=plug is inserted. On SE/30, always 0 186 */ 187 #define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */ 188 #define VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */ 189 #define VIA2B_vMode32 0x08 /* 190 * 24/32bit switch - doubles as cache flush 191 * on II, AMU/PMMU control. 192 * if AMU, 0=24bit to 32bit translation 193 * if PMMU, 1=PMMU is accessing page table. 194 * on SE/30 tied low. 195 * on IIx,IIcx,IIfx, unused. 196 * on IIci/RBV, cache control. 0=flush cache. 197 */ 198 #define VIA2B_vPower 0x04 /* 199 * Power off, 0=shut off power. 200 * on SE/30 this signal sent to PDS card. 201 */ 202 #define VIA2B_vBusLk 0x02 /* 203 * Lock NuBus transactions, 0=locked. 204 * on SE/30 sent to PDS card. 205 */ 206 #define VIA2B_vCDis 0x01 /* 207 * Cache control. On IIci, 1=disable cache card 208 * on others, 0=disable processor's instruction 209 * and data caches. 210 */ 211 212 /* interrupt flags */ 213 214 #define IRQ_SET 0x80 215 216 /* common */ 217 218 #define VIA_IRQ_TIMER1 0x40 219 #define VIA_IRQ_TIMER2 0x20 220 221 /* 222 * Apple sez: http://developer.apple.com/technotes/ov/ov_04.html 223 * Another example of a valid function that has no ROM support is the use 224 * of the alternate video page for page-flipping animation. Since there 225 * is no ROM call to flip pages, it is necessary to go play with the 226 * right bit in the VIA chip (6522 Versatile Interface Adapter). 227 * [CSA: don't know which one this is, but it's one of 'em!] 228 */ 229 230 /* 231 * 6522 registers - see databook. 232 * CSA: Assignments for VIA1 confirmed from CHRP spec. 233 */ 234 235 /* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */ 236 /* Note: 15 VIA regs, 8 RBV regs */ 237 238 #define vBufB 0x0000 /* [VIA/RBV] Register B */ 239 #define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */ 240 #define vDirB 0x0400 /* [VIA only] Data Direction Register B. */ 241 #define vDirA 0x0600 /* [VIA only] Data Direction Register A. */ 242 #define vT1CL 0x0800 /* [VIA only] Timer one counter low. */ 243 #define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */ 244 #define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */ 245 #define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */ 246 #define vT2CL 0x1000 /* [VIA only] Timer two counter low. */ 247 #define vT2CH 0x1200 /* [VIA only] Timer two counter high. */ 248 #define vSR 0x1400 /* [VIA only] Shift register. */ 249 #define vACR 0x1600 /* [VIA only] Auxilary control register. */ 250 #define vPCR 0x1800 /* [VIA only] Peripheral control register. */ 251 /* 252 * CHRP sez never ever to *write* this. 253 * Mac family says never to *change* this. 254 * In fact we need to initialize it once at start. 255 */ 256 #define vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */ 257 #define vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */ 258 #define vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */ 259 260 /* from linux 2.6 drivers/macintosh/via-macii.c */ 261 262 /* Bits in ACR */ 263 264 #define VIA1ACR_vShiftCtrl 0x1c /* Shift register control bits */ 265 #define VIA1ACR_vShiftExtClk 0x0c /* Shift on external clock */ 266 #define VIA1ACR_vShiftOut 0x10 /* Shift out if 1 */ 267 268 /* 269 * Apple Macintosh Family Hardware Refenece 270 * Table 19-10 ADB transaction states 271 */ 272 273 #define ADB_STATE_NEW 0 274 #define ADB_STATE_EVEN 1 275 #define ADB_STATE_ODD 2 276 #define ADB_STATE_IDLE 3 277 278 #define VIA1B_vADB_StateMask (VIA1B_vADBS1 | VIA1B_vADBS2) 279 #define VIA1B_vADB_StateShift 4 280 281 #define VIA_TIMER_FREQ (783360) 282 #define VIA_ADB_POLL_FREQ 50 /* XXX: not real */ 283 284 /* 285 * Guide to the Macintosh Family Hardware ch. 12 "Displays" p. 401 gives the 286 * precise 60Hz interrupt frequency as ~60.15Hz with a period of 16625.8 us 287 */ 288 #define VIA_60HZ_TIMER_PERIOD_NS 16625800 289 290 /* VIA returns time offset from Jan 1, 1904, not 1970 */ 291 #define RTC_OFFSET 2082844800 292 293 enum { 294 REG_0, 295 REG_1, 296 REG_2, 297 REG_3, 298 REG_TEST, 299 REG_WPROTECT, 300 REG_PRAM_ADDR, 301 REG_PRAM_ADDR_LAST = REG_PRAM_ADDR + 19, 302 REG_PRAM_SECT, 303 REG_PRAM_SECT_LAST = REG_PRAM_SECT + 7, 304 REG_INVALID, 305 REG_EMPTY = 0xff, 306 }; 307 308 static void via1_sixty_hz_update(MOS6522Q800VIA1State *v1s) 309 { 310 /* 60 Hz irq */ 311 v1s->next_sixty_hz = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 312 VIA_60HZ_TIMER_PERIOD_NS) / 313 VIA_60HZ_TIMER_PERIOD_NS * VIA_60HZ_TIMER_PERIOD_NS; 314 timer_mod(v1s->sixty_hz_timer, v1s->next_sixty_hz); 315 } 316 317 static void via1_one_second_update(MOS6522Q800VIA1State *v1s) 318 { 319 v1s->next_second = (qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000) / 320 1000 * 1000; 321 timer_mod(v1s->one_second_timer, v1s->next_second); 322 } 323 324 static void via1_sixty_hz(void *opaque) 325 { 326 MOS6522Q800VIA1State *v1s = opaque; 327 MOS6522State *s = MOS6522(v1s); 328 qemu_irq irq = qdev_get_gpio_in(DEVICE(s), VIA1_IRQ_60HZ_BIT); 329 330 /* Negative edge trigger */ 331 qemu_irq_lower(irq); 332 qemu_irq_raise(irq); 333 334 via1_sixty_hz_update(v1s); 335 } 336 337 static void via1_one_second(void *opaque) 338 { 339 MOS6522Q800VIA1State *v1s = opaque; 340 MOS6522State *s = MOS6522(v1s); 341 qemu_irq irq = qdev_get_gpio_in(DEVICE(s), VIA1_IRQ_ONE_SECOND_BIT); 342 343 /* Negative edge trigger */ 344 qemu_irq_lower(irq); 345 qemu_irq_raise(irq); 346 347 via1_one_second_update(v1s); 348 } 349 350 351 static void pram_update(MOS6522Q800VIA1State *v1s) 352 { 353 if (v1s->blk) { 354 if (blk_pwrite(v1s->blk, 0, v1s->PRAM, sizeof(v1s->PRAM), 0) < 0) { 355 qemu_log("pram_update: cannot write to file\n"); 356 } 357 } 358 } 359 360 /* 361 * RTC Commands 362 * 363 * Command byte Register addressed by the command 364 * 365 * z0000001 Seconds register 0 (lowest-order byte) 366 * z0000101 Seconds register 1 367 * z0001001 Seconds register 2 368 * z0001101 Seconds register 3 (highest-order byte) 369 * 00110001 Test register (write-only) 370 * 00110101 Write-Protect Register (write-only) 371 * z010aa01 RAM address 100aa ($10-$13) (first 20 bytes only) 372 * z1aaaa01 RAM address 0aaaa ($00-$0F) (first 20 bytes only) 373 * z0111aaa Extended memory designator and sector number 374 * 375 * For a read request, z=1, for a write z=0 376 * The letter a indicates bits whose value depend on what parameter 377 * RAM byte you want to address 378 */ 379 static int via1_rtc_compact_cmd(uint8_t value) 380 { 381 uint8_t read = value & 0x80; 382 383 value &= 0x7f; 384 385 /* the last 2 bits of a command byte must always be 0b01 ... */ 386 if ((value & 0x78) == 0x38) { 387 /* except for the extended memory designator */ 388 return read | (REG_PRAM_SECT + (value & 0x07)); 389 } 390 if ((value & 0x03) == 0x01) { 391 value >>= 2; 392 if ((value & 0x1c) == 0) { 393 /* seconds registers */ 394 return read | (REG_0 + (value & 0x03)); 395 } else if ((value == 0x0c) && !read) { 396 return REG_TEST; 397 } else if ((value == 0x0d) && !read) { 398 return REG_WPROTECT; 399 } else if ((value & 0x1c) == 0x08) { 400 /* RAM address 0x10 to 0x13 */ 401 return read | (REG_PRAM_ADDR + 0x10 + (value & 0x03)); 402 } else if ((value & 0x43) == 0x41) { 403 /* RAM address 0x00 to 0x0f */ 404 return read | (REG_PRAM_ADDR + (value & 0x0f)); 405 } 406 } 407 return REG_INVALID; 408 } 409 410 static void via1_rtc_update(MOS6522Q800VIA1State *v1s) 411 { 412 MOS6522State *s = MOS6522(v1s); 413 int cmd, sector, addr; 414 uint32_t time; 415 416 if (s->b & VIA1B_vRTCEnb) { 417 return; 418 } 419 420 if (s->dirb & VIA1B_vRTCData) { 421 /* send bits to the RTC */ 422 if (!(v1s->last_b & VIA1B_vRTCClk) && (s->b & VIA1B_vRTCClk)) { 423 v1s->data_out <<= 1; 424 v1s->data_out |= s->b & VIA1B_vRTCData; 425 v1s->data_out_cnt++; 426 } 427 trace_via1_rtc_update_data_out(v1s->data_out_cnt, v1s->data_out); 428 } else { 429 trace_via1_rtc_update_data_in(v1s->data_in_cnt, v1s->data_in); 430 /* receive bits from the RTC */ 431 if ((v1s->last_b & VIA1B_vRTCClk) && 432 !(s->b & VIA1B_vRTCClk) && 433 v1s->data_in_cnt) { 434 s->b = (s->b & ~VIA1B_vRTCData) | 435 ((v1s->data_in >> 7) & VIA1B_vRTCData); 436 v1s->data_in <<= 1; 437 v1s->data_in_cnt--; 438 } 439 return; 440 } 441 442 if (v1s->data_out_cnt != 8) { 443 return; 444 } 445 446 v1s->data_out_cnt = 0; 447 448 trace_via1_rtc_internal_status(v1s->cmd, v1s->alt, v1s->data_out); 449 /* first byte: it's a command */ 450 if (v1s->cmd == REG_EMPTY) { 451 452 cmd = via1_rtc_compact_cmd(v1s->data_out); 453 trace_via1_rtc_internal_cmd(cmd); 454 455 if (cmd == REG_INVALID) { 456 trace_via1_rtc_cmd_invalid(v1s->data_out); 457 return; 458 } 459 460 if (cmd & 0x80) { /* this is a read command */ 461 switch (cmd & 0x7f) { 462 case REG_0...REG_3: /* seconds registers */ 463 /* 464 * register 0 is lowest-order byte 465 * register 3 is highest-order byte 466 */ 467 468 time = v1s->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) 469 / NANOSECONDS_PER_SECOND); 470 trace_via1_rtc_internal_time(time); 471 v1s->data_in = (time >> ((cmd & 0x03) << 3)) & 0xff; 472 v1s->data_in_cnt = 8; 473 trace_via1_rtc_cmd_seconds_read((cmd & 0x7f) - REG_0, 474 v1s->data_in); 475 break; 476 case REG_PRAM_ADDR...REG_PRAM_ADDR_LAST: 477 /* PRAM address 0x00 -> 0x13 */ 478 v1s->data_in = v1s->PRAM[(cmd & 0x7f) - REG_PRAM_ADDR]; 479 v1s->data_in_cnt = 8; 480 trace_via1_rtc_cmd_pram_read((cmd & 0x7f) - REG_PRAM_ADDR, 481 v1s->data_in); 482 break; 483 case REG_PRAM_SECT...REG_PRAM_SECT_LAST: 484 /* 485 * extended memory designator and sector number 486 * the only two-byte read command 487 */ 488 trace_via1_rtc_internal_set_cmd(cmd); 489 v1s->cmd = cmd; 490 break; 491 default: 492 g_assert_not_reached(); 493 break; 494 } 495 return; 496 } 497 498 /* this is a write command, needs a parameter */ 499 if (cmd == REG_WPROTECT || !v1s->wprotect) { 500 trace_via1_rtc_internal_set_cmd(cmd); 501 v1s->cmd = cmd; 502 } else { 503 trace_via1_rtc_internal_ignore_cmd(cmd); 504 } 505 return; 506 } 507 508 /* second byte: it's a parameter */ 509 if (v1s->alt == REG_EMPTY) { 510 switch (v1s->cmd & 0x7f) { 511 case REG_0...REG_3: /* seconds register */ 512 /* FIXME */ 513 trace_via1_rtc_cmd_seconds_write(v1s->cmd - REG_0, v1s->data_out); 514 v1s->cmd = REG_EMPTY; 515 break; 516 case REG_TEST: 517 /* device control: nothing to do */ 518 trace_via1_rtc_cmd_test_write(v1s->data_out); 519 v1s->cmd = REG_EMPTY; 520 break; 521 case REG_WPROTECT: 522 /* Write Protect register */ 523 trace_via1_rtc_cmd_wprotect_write(v1s->data_out); 524 v1s->wprotect = !!(v1s->data_out & 0x80); 525 v1s->cmd = REG_EMPTY; 526 break; 527 case REG_PRAM_ADDR...REG_PRAM_ADDR_LAST: 528 /* PRAM address 0x00 -> 0x13 */ 529 trace_via1_rtc_cmd_pram_write(v1s->cmd - REG_PRAM_ADDR, 530 v1s->data_out); 531 v1s->PRAM[v1s->cmd - REG_PRAM_ADDR] = v1s->data_out; 532 pram_update(v1s); 533 v1s->cmd = REG_EMPTY; 534 break; 535 case REG_PRAM_SECT...REG_PRAM_SECT_LAST: 536 addr = (v1s->data_out >> 2) & 0x1f; 537 sector = (v1s->cmd & 0x7f) - REG_PRAM_SECT; 538 if (v1s->cmd & 0x80) { 539 /* it's a read */ 540 v1s->data_in = v1s->PRAM[sector * 32 + addr]; 541 v1s->data_in_cnt = 8; 542 trace_via1_rtc_cmd_pram_sect_read(sector, addr, 543 sector * 32 + addr, 544 v1s->data_in); 545 v1s->cmd = REG_EMPTY; 546 } else { 547 /* it's a write, we need one more parameter */ 548 trace_via1_rtc_internal_set_alt(addr, sector, addr); 549 v1s->alt = addr; 550 } 551 break; 552 default: 553 g_assert_not_reached(); 554 break; 555 } 556 return; 557 } 558 559 /* third byte: it's the data of a REG_PRAM_SECT write */ 560 g_assert(REG_PRAM_SECT <= v1s->cmd && v1s->cmd <= REG_PRAM_SECT_LAST); 561 sector = v1s->cmd - REG_PRAM_SECT; 562 v1s->PRAM[sector * 32 + v1s->alt] = v1s->data_out; 563 pram_update(v1s); 564 trace_via1_rtc_cmd_pram_sect_write(sector, v1s->alt, sector * 32 + v1s->alt, 565 v1s->data_out); 566 v1s->alt = REG_EMPTY; 567 v1s->cmd = REG_EMPTY; 568 } 569 570 static void adb_via_poll(void *opaque) 571 { 572 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque); 573 MOS6522State *s = MOS6522(v1s); 574 ADBBusState *adb_bus = &v1s->adb_bus; 575 uint8_t obuf[9]; 576 uint8_t *data = &s->sr; 577 int olen; 578 579 /* 580 * Setting vADBInt below indicates that an autopoll reply has been 581 * received, however we must block autopoll until the point where 582 * the entire reply has been read back to the host 583 */ 584 adb_autopoll_block(adb_bus); 585 586 if (v1s->adb_data_in_size > 0 && v1s->adb_data_in_index == 0) { 587 /* 588 * For older Linux kernels that switch to IDLE mode after sending the 589 * ADB command, detect if there is an existing response and return that 590 * as a a "fake" autopoll reply or bus timeout accordingly 591 */ 592 *data = v1s->adb_data_out[0]; 593 olen = v1s->adb_data_in_size; 594 595 s->b &= ~VIA1B_vADBInt; 596 qemu_irq_raise(v1s->adb_data_ready); 597 } else { 598 /* 599 * Otherwise poll as normal 600 */ 601 v1s->adb_data_in_index = 0; 602 v1s->adb_data_out_index = 0; 603 olen = adb_poll(adb_bus, obuf, adb_bus->autopoll_mask); 604 605 if (olen > 0) { 606 /* Autopoll response */ 607 *data = obuf[0]; 608 olen--; 609 memcpy(v1s->adb_data_in, &obuf[1], olen); 610 v1s->adb_data_in_size = olen; 611 612 s->b &= ~VIA1B_vADBInt; 613 qemu_irq_raise(v1s->adb_data_ready); 614 } else { 615 *data = v1s->adb_autopoll_cmd; 616 obuf[0] = 0xff; 617 obuf[1] = 0xff; 618 olen = 2; 619 620 memcpy(v1s->adb_data_in, obuf, olen); 621 v1s->adb_data_in_size = olen; 622 623 s->b &= ~VIA1B_vADBInt; 624 qemu_irq_raise(v1s->adb_data_ready); 625 } 626 } 627 628 trace_via1_adb_poll(*data, (s->b & VIA1B_vADBInt) ? "+" : "-", 629 adb_bus->status, v1s->adb_data_in_index, olen); 630 } 631 632 static int adb_via_send_len(uint8_t data) 633 { 634 /* Determine the send length from the given ADB command */ 635 uint8_t cmd = data & 0xc; 636 uint8_t reg = data & 0x3; 637 638 switch (cmd) { 639 case 0x8: 640 /* Listen command */ 641 switch (reg) { 642 case 2: 643 /* Register 2 is only used for the keyboard */ 644 return 3; 645 case 3: 646 /* 647 * Fortunately our devices only implement writes 648 * to register 3 which is fixed at 2 bytes 649 */ 650 return 3; 651 default: 652 qemu_log_mask(LOG_UNIMP, "ADB unknown length for register %d\n", 653 reg); 654 return 1; 655 } 656 default: 657 /* Talk, BusReset */ 658 return 1; 659 } 660 } 661 662 static void adb_via_send(MOS6522Q800VIA1State *v1s, int state, uint8_t data) 663 { 664 MOS6522State *ms = MOS6522(v1s); 665 ADBBusState *adb_bus = &v1s->adb_bus; 666 uint16_t autopoll_mask; 667 668 switch (state) { 669 case ADB_STATE_NEW: 670 /* 671 * Command byte: vADBInt tells host autopoll data already present 672 * in VIA shift register and ADB transceiver 673 */ 674 adb_autopoll_block(adb_bus); 675 676 if (adb_bus->status & ADB_STATUS_POLLREPLY) { 677 /* Tell the host the existing data is from autopoll */ 678 ms->b &= ~VIA1B_vADBInt; 679 } else { 680 ms->b |= VIA1B_vADBInt; 681 v1s->adb_data_out_index = 0; 682 v1s->adb_data_out[v1s->adb_data_out_index++] = data; 683 } 684 685 trace_via1_adb_send(" NEW", data, (ms->b & VIA1B_vADBInt) ? "+" : "-"); 686 qemu_irq_raise(v1s->adb_data_ready); 687 break; 688 689 case ADB_STATE_EVEN: 690 case ADB_STATE_ODD: 691 ms->b |= VIA1B_vADBInt; 692 v1s->adb_data_out[v1s->adb_data_out_index++] = data; 693 694 trace_via1_adb_send(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 695 data, (ms->b & VIA1B_vADBInt) ? "+" : "-"); 696 qemu_irq_raise(v1s->adb_data_ready); 697 break; 698 699 case ADB_STATE_IDLE: 700 return; 701 } 702 703 /* If the command is complete, execute it */ 704 if (v1s->adb_data_out_index == adb_via_send_len(v1s->adb_data_out[0])) { 705 v1s->adb_data_in_size = adb_request(adb_bus, v1s->adb_data_in, 706 v1s->adb_data_out, 707 v1s->adb_data_out_index); 708 v1s->adb_data_in_index = 0; 709 710 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 711 /* 712 * Bus timeout (but allow first EVEN and ODD byte to indicate 713 * timeout via vADBInt and SRQ status) 714 */ 715 v1s->adb_data_in[0] = 0xff; 716 v1s->adb_data_in[1] = 0xff; 717 v1s->adb_data_in_size = 2; 718 } 719 720 /* 721 * If last command is TALK, store it for use by autopoll and adjust 722 * the autopoll mask accordingly 723 */ 724 if ((v1s->adb_data_out[0] & 0xc) == 0xc) { 725 v1s->adb_autopoll_cmd = v1s->adb_data_out[0]; 726 727 autopoll_mask = 1 << (v1s->adb_autopoll_cmd >> 4); 728 adb_set_autopoll_mask(adb_bus, autopoll_mask); 729 } 730 } 731 } 732 733 static void adb_via_receive(MOS6522Q800VIA1State *v1s, int state, uint8_t *data) 734 { 735 MOS6522State *ms = MOS6522(v1s); 736 ADBBusState *adb_bus = &v1s->adb_bus; 737 uint16_t pending; 738 739 switch (state) { 740 case ADB_STATE_NEW: 741 ms->b |= VIA1B_vADBInt; 742 return; 743 744 case ADB_STATE_IDLE: 745 ms->b |= VIA1B_vADBInt; 746 adb_autopoll_unblock(adb_bus); 747 748 trace_via1_adb_receive("IDLE", *data, 749 (ms->b & VIA1B_vADBInt) ? "+" : "-", adb_bus->status, 750 v1s->adb_data_in_index, v1s->adb_data_in_size); 751 752 break; 753 754 case ADB_STATE_EVEN: 755 case ADB_STATE_ODD: 756 switch (v1s->adb_data_in_index) { 757 case 0: 758 /* First EVEN byte: vADBInt indicates bus timeout */ 759 *data = v1s->adb_data_in[v1s->adb_data_in_index]; 760 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 761 ms->b &= ~VIA1B_vADBInt; 762 } else { 763 ms->b |= VIA1B_vADBInt; 764 } 765 766 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 767 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 768 adb_bus->status, v1s->adb_data_in_index, 769 v1s->adb_data_in_size); 770 771 v1s->adb_data_in_index++; 772 break; 773 774 case 1: 775 /* First ODD byte: vADBInt indicates SRQ */ 776 *data = v1s->adb_data_in[v1s->adb_data_in_index]; 777 pending = adb_bus->pending & ~(1 << (v1s->adb_autopoll_cmd >> 4)); 778 if (pending) { 779 ms->b &= ~VIA1B_vADBInt; 780 } else { 781 ms->b |= VIA1B_vADBInt; 782 } 783 784 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 785 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 786 adb_bus->status, v1s->adb_data_in_index, 787 v1s->adb_data_in_size); 788 789 v1s->adb_data_in_index++; 790 break; 791 792 default: 793 /* 794 * Otherwise vADBInt indicates end of data. Note that Linux 795 * specifically checks for the sequence 0x0 0xff to confirm the 796 * end of the poll reply, so provide these extra bytes below to 797 * keep it happy 798 */ 799 if (v1s->adb_data_in_index < v1s->adb_data_in_size) { 800 /* Next data byte */ 801 *data = v1s->adb_data_in[v1s->adb_data_in_index]; 802 ms->b |= VIA1B_vADBInt; 803 } else if (v1s->adb_data_in_index == v1s->adb_data_in_size) { 804 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 805 /* Bus timeout (no more data) */ 806 *data = 0xff; 807 } else { 808 /* Return 0x0 after reply */ 809 *data = 0; 810 } 811 ms->b &= ~VIA1B_vADBInt; 812 } else { 813 /* Bus timeout (no more data) */ 814 *data = 0xff; 815 ms->b &= ~VIA1B_vADBInt; 816 adb_bus->status = 0; 817 adb_autopoll_unblock(adb_bus); 818 } 819 820 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 821 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 822 adb_bus->status, v1s->adb_data_in_index, 823 v1s->adb_data_in_size); 824 825 if (v1s->adb_data_in_index <= v1s->adb_data_in_size) { 826 v1s->adb_data_in_index++; 827 } 828 break; 829 } 830 831 qemu_irq_raise(v1s->adb_data_ready); 832 break; 833 } 834 } 835 836 static void via1_adb_update(MOS6522Q800VIA1State *v1s) 837 { 838 MOS6522State *s = MOS6522(v1s); 839 int oldstate, state; 840 841 oldstate = (v1s->last_b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; 842 state = (s->b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; 843 844 if (state != oldstate) { 845 if (s->acr & VIA1ACR_vShiftOut) { 846 /* output mode */ 847 adb_via_send(v1s, state, s->sr); 848 } else { 849 /* input mode */ 850 adb_via_receive(v1s, state, &s->sr); 851 } 852 } 853 } 854 855 static void via1_auxmode_update(MOS6522Q800VIA1State *v1s) 856 { 857 MOS6522State *s = MOS6522(v1s); 858 int oldirq, irq; 859 860 oldirq = (v1s->last_b & VIA1B_vMystery) ? 1 : 0; 861 irq = (s->b & VIA1B_vMystery) ? 1 : 0; 862 863 /* Check to see if the A/UX mode bit has changed */ 864 if (irq != oldirq) { 865 trace_via1_auxmode(irq); 866 qemu_set_irq(v1s->auxmode_irq, irq); 867 } 868 } 869 870 static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned size) 871 { 872 MOS6522Q800VIA1State *s = MOS6522_Q800_VIA1(opaque); 873 MOS6522State *ms = MOS6522(s); 874 875 addr = (addr >> 9) & 0xf; 876 return mos6522_read(ms, addr, size); 877 } 878 879 static void mos6522_q800_via1_write(void *opaque, hwaddr addr, uint64_t val, 880 unsigned size) 881 { 882 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque); 883 MOS6522State *ms = MOS6522(v1s); 884 885 addr = (addr >> 9) & 0xf; 886 mos6522_write(ms, addr, val, size); 887 888 switch (addr) { 889 case VIA_REG_B: 890 via1_rtc_update(v1s); 891 via1_adb_update(v1s); 892 via1_auxmode_update(v1s); 893 894 v1s->last_b = ms->b; 895 break; 896 } 897 } 898 899 static const MemoryRegionOps mos6522_q800_via1_ops = { 900 .read = mos6522_q800_via1_read, 901 .write = mos6522_q800_via1_write, 902 .endianness = DEVICE_BIG_ENDIAN, 903 .valid = { 904 .min_access_size = 1, 905 .max_access_size = 4, 906 }, 907 }; 908 909 static uint64_t mos6522_q800_via2_read(void *opaque, hwaddr addr, unsigned size) 910 { 911 MOS6522Q800VIA2State *s = MOS6522_Q800_VIA2(opaque); 912 MOS6522State *ms = MOS6522(s); 913 uint64_t val; 914 915 addr = (addr >> 9) & 0xf; 916 val = mos6522_read(ms, addr, size); 917 918 switch (addr) { 919 case VIA_REG_IFR: 920 /* 921 * On a Q800 an emulated VIA2 is integrated into the onboard logic. The 922 * expectation of most OSs is that the DRQ bit is live, rather than 923 * latched as it would be on a real VIA so do the same here. 924 * 925 * Note: DRQ is negative edge triggered 926 */ 927 val &= ~VIA2_IRQ_SCSI_DATA; 928 val |= (~ms->last_irq_levels & VIA2_IRQ_SCSI_DATA); 929 break; 930 } 931 932 return val; 933 } 934 935 static void mos6522_q800_via2_write(void *opaque, hwaddr addr, uint64_t val, 936 unsigned size) 937 { 938 MOS6522Q800VIA2State *s = MOS6522_Q800_VIA2(opaque); 939 MOS6522State *ms = MOS6522(s); 940 941 addr = (addr >> 9) & 0xf; 942 mos6522_write(ms, addr, val, size); 943 } 944 945 static const MemoryRegionOps mos6522_q800_via2_ops = { 946 .read = mos6522_q800_via2_read, 947 .write = mos6522_q800_via2_write, 948 .endianness = DEVICE_BIG_ENDIAN, 949 .valid = { 950 .min_access_size = 1, 951 .max_access_size = 4, 952 }, 953 }; 954 955 static void via1_postload_update_cb(void *opaque, bool running, RunState state) 956 { 957 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque); 958 959 qemu_del_vm_change_state_handler(v1s->vmstate); 960 v1s->vmstate = NULL; 961 962 pram_update(v1s); 963 } 964 965 static int via1_post_load(void *opaque, int version_id) 966 { 967 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque); 968 969 if (v1s->blk) { 970 v1s->vmstate = qemu_add_vm_change_state_handler( 971 via1_postload_update_cb, v1s); 972 } 973 974 return 0; 975 } 976 977 /* VIA 1 */ 978 static void mos6522_q800_via1_reset(DeviceState *dev) 979 { 980 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(dev); 981 MOS6522State *ms = MOS6522(v1s); 982 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); 983 ADBBusState *adb_bus = &v1s->adb_bus; 984 985 mdc->parent_reset(dev); 986 987 ms->timers[0].frequency = VIA_TIMER_FREQ; 988 ms->timers[1].frequency = VIA_TIMER_FREQ; 989 990 ms->b = VIA1B_vADB_StateMask | VIA1B_vADBInt | VIA1B_vRTCEnb; 991 992 /* ADB/RTC */ 993 adb_set_autopoll_enabled(adb_bus, true); 994 v1s->cmd = REG_EMPTY; 995 v1s->alt = REG_EMPTY; 996 } 997 998 static void mos6522_q800_via1_realize(DeviceState *dev, Error **errp) 999 { 1000 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(dev); 1001 ADBBusState *adb_bus = &v1s->adb_bus; 1002 struct tm tm; 1003 int ret; 1004 1005 v1s->one_second_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, via1_one_second, 1006 v1s); 1007 via1_one_second_update(v1s); 1008 v1s->sixty_hz_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, via1_sixty_hz, 1009 v1s); 1010 via1_sixty_hz_update(v1s); 1011 1012 qemu_get_timedate(&tm, 0); 1013 v1s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; 1014 1015 adb_register_autopoll_callback(adb_bus, adb_via_poll, v1s); 1016 v1s->adb_data_ready = qdev_get_gpio_in(dev, VIA1_IRQ_ADB_READY_BIT); 1017 1018 if (v1s->blk) { 1019 int64_t len = blk_getlength(v1s->blk); 1020 if (len < 0) { 1021 error_setg_errno(errp, -len, 1022 "could not get length of backing image"); 1023 return; 1024 } 1025 ret = blk_set_perm(v1s->blk, 1026 BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE, 1027 BLK_PERM_ALL, errp); 1028 if (ret < 0) { 1029 return; 1030 } 1031 1032 len = blk_pread(v1s->blk, 0, v1s->PRAM, sizeof(v1s->PRAM)); 1033 if (len != sizeof(v1s->PRAM)) { 1034 error_setg(errp, "can't read PRAM contents"); 1035 return; 1036 } 1037 } 1038 } 1039 1040 static void mos6522_q800_via1_init(Object *obj) 1041 { 1042 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(obj); 1043 SysBusDevice *sbd = SYS_BUS_DEVICE(v1s); 1044 1045 memory_region_init_io(&v1s->via_mem, obj, &mos6522_q800_via1_ops, v1s, 1046 "via1", VIA_SIZE); 1047 sysbus_init_mmio(sbd, &v1s->via_mem); 1048 1049 /* ADB */ 1050 qbus_init((BusState *)&v1s->adb_bus, sizeof(v1s->adb_bus), 1051 TYPE_ADB_BUS, DEVICE(v1s), "adb.0"); 1052 1053 /* A/UX mode */ 1054 qdev_init_gpio_out(DEVICE(obj), &v1s->auxmode_irq, 1); 1055 } 1056 1057 static const VMStateDescription vmstate_q800_via1 = { 1058 .name = "q800-via1", 1059 .version_id = 0, 1060 .minimum_version_id = 0, 1061 .post_load = via1_post_load, 1062 .fields = (VMStateField[]) { 1063 VMSTATE_STRUCT(parent_obj, MOS6522Q800VIA1State, 0, vmstate_mos6522, 1064 MOS6522State), 1065 VMSTATE_UINT8(last_b, MOS6522Q800VIA1State), 1066 /* RTC */ 1067 VMSTATE_BUFFER(PRAM, MOS6522Q800VIA1State), 1068 VMSTATE_UINT32(tick_offset, MOS6522Q800VIA1State), 1069 VMSTATE_UINT8(data_out, MOS6522Q800VIA1State), 1070 VMSTATE_INT32(data_out_cnt, MOS6522Q800VIA1State), 1071 VMSTATE_UINT8(data_in, MOS6522Q800VIA1State), 1072 VMSTATE_UINT8(data_in_cnt, MOS6522Q800VIA1State), 1073 VMSTATE_UINT8(cmd, MOS6522Q800VIA1State), 1074 VMSTATE_INT32(wprotect, MOS6522Q800VIA1State), 1075 VMSTATE_INT32(alt, MOS6522Q800VIA1State), 1076 /* ADB */ 1077 VMSTATE_INT32(adb_data_in_size, MOS6522Q800VIA1State), 1078 VMSTATE_INT32(adb_data_in_index, MOS6522Q800VIA1State), 1079 VMSTATE_INT32(adb_data_out_index, MOS6522Q800VIA1State), 1080 VMSTATE_BUFFER(adb_data_in, MOS6522Q800VIA1State), 1081 VMSTATE_BUFFER(adb_data_out, MOS6522Q800VIA1State), 1082 VMSTATE_UINT8(adb_autopoll_cmd, MOS6522Q800VIA1State), 1083 /* Timers */ 1084 VMSTATE_TIMER_PTR(one_second_timer, MOS6522Q800VIA1State), 1085 VMSTATE_INT64(next_second, MOS6522Q800VIA1State), 1086 VMSTATE_TIMER_PTR(sixty_hz_timer, MOS6522Q800VIA1State), 1087 VMSTATE_INT64(next_sixty_hz, MOS6522Q800VIA1State), 1088 VMSTATE_END_OF_LIST() 1089 } 1090 }; 1091 1092 static Property mos6522_q800_via1_properties[] = { 1093 DEFINE_PROP_DRIVE("drive", MOS6522Q800VIA1State, blk), 1094 DEFINE_PROP_END_OF_LIST(), 1095 }; 1096 1097 static void mos6522_q800_via1_class_init(ObjectClass *oc, void *data) 1098 { 1099 DeviceClass *dc = DEVICE_CLASS(oc); 1100 MOS6522DeviceClass *mdc = MOS6522_CLASS(oc); 1101 1102 dc->realize = mos6522_q800_via1_realize; 1103 device_class_set_parent_reset(dc, mos6522_q800_via1_reset, 1104 &mdc->parent_reset); 1105 dc->vmsd = &vmstate_q800_via1; 1106 device_class_set_props(dc, mos6522_q800_via1_properties); 1107 } 1108 1109 static const TypeInfo mos6522_q800_via1_type_info = { 1110 .name = TYPE_MOS6522_Q800_VIA1, 1111 .parent = TYPE_MOS6522, 1112 .instance_size = sizeof(MOS6522Q800VIA1State), 1113 .instance_init = mos6522_q800_via1_init, 1114 .class_init = mos6522_q800_via1_class_init, 1115 }; 1116 1117 /* VIA 2 */ 1118 static void mos6522_q800_via2_portB_write(MOS6522State *s) 1119 { 1120 if (s->dirb & VIA2B_vPower && (s->b & VIA2B_vPower) == 0) { 1121 /* shutdown */ 1122 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 1123 } 1124 } 1125 1126 static void mos6522_q800_via2_reset(DeviceState *dev) 1127 { 1128 MOS6522State *ms = MOS6522(dev); 1129 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); 1130 1131 mdc->parent_reset(dev); 1132 1133 ms->timers[0].frequency = VIA_TIMER_FREQ; 1134 ms->timers[1].frequency = VIA_TIMER_FREQ; 1135 1136 ms->dirb = 0; 1137 ms->b = 0; 1138 ms->dira = 0; 1139 ms->a = 0x7f; 1140 } 1141 1142 static void via2_nubus_irq_request(void *opaque, int n, int level) 1143 { 1144 MOS6522Q800VIA2State *v2s = opaque; 1145 MOS6522State *s = MOS6522(v2s); 1146 qemu_irq irq = qdev_get_gpio_in(DEVICE(s), VIA2_IRQ_NUBUS_BIT); 1147 1148 if (level) { 1149 /* Port A nubus IRQ inputs are active LOW */ 1150 s->a &= ~(1 << n); 1151 } else { 1152 s->a |= (1 << n); 1153 } 1154 1155 /* Negative edge trigger */ 1156 qemu_set_irq(irq, !level); 1157 } 1158 1159 static void mos6522_q800_via2_init(Object *obj) 1160 { 1161 MOS6522Q800VIA2State *v2s = MOS6522_Q800_VIA2(obj); 1162 SysBusDevice *sbd = SYS_BUS_DEVICE(v2s); 1163 1164 memory_region_init_io(&v2s->via_mem, obj, &mos6522_q800_via2_ops, v2s, 1165 "via2", VIA_SIZE); 1166 sysbus_init_mmio(sbd, &v2s->via_mem); 1167 1168 qdev_init_gpio_in_named(DEVICE(obj), via2_nubus_irq_request, "nubus-irq", 1169 VIA2_NUBUS_IRQ_NB); 1170 } 1171 1172 static const VMStateDescription vmstate_q800_via2 = { 1173 .name = "q800-via2", 1174 .version_id = 0, 1175 .minimum_version_id = 0, 1176 .fields = (VMStateField[]) { 1177 VMSTATE_STRUCT(parent_obj, MOS6522Q800VIA2State, 0, vmstate_mos6522, 1178 MOS6522State), 1179 VMSTATE_END_OF_LIST() 1180 } 1181 }; 1182 1183 static void mos6522_q800_via2_class_init(ObjectClass *oc, void *data) 1184 { 1185 DeviceClass *dc = DEVICE_CLASS(oc); 1186 MOS6522DeviceClass *mdc = MOS6522_CLASS(oc); 1187 1188 device_class_set_parent_reset(dc, mos6522_q800_via2_reset, 1189 &mdc->parent_reset); 1190 dc->vmsd = &vmstate_q800_via2; 1191 mdc->portB_write = mos6522_q800_via2_portB_write; 1192 } 1193 1194 static const TypeInfo mos6522_q800_via2_type_info = { 1195 .name = TYPE_MOS6522_Q800_VIA2, 1196 .parent = TYPE_MOS6522, 1197 .instance_size = sizeof(MOS6522Q800VIA2State), 1198 .instance_init = mos6522_q800_via2_init, 1199 .class_init = mos6522_q800_via2_class_init, 1200 }; 1201 1202 static void mac_via_register_types(void) 1203 { 1204 type_register_static(&mos6522_q800_via1_type_info); 1205 type_register_static(&mos6522_q800_via2_type_info); 1206 } 1207 1208 type_init(mac_via_register_types); 1209