1 /* 2 * QEMU m68k Macintosh VIA device support 3 * 4 * Copyright (c) 2011-2018 Laurent Vivier 5 * Copyright (c) 2018 Mark Cave-Ayland 6 * 7 * Some parts from hw/misc/macio/cuda.c 8 * 9 * Copyright (c) 2004-2007 Fabrice Bellard 10 * Copyright (c) 2007 Jocelyn Mayer 11 * 12 * some parts from linux-2.6.29, arch/m68k/include/asm/mac_via.h 13 * 14 * This work is licensed under the terms of the GNU GPL, version 2 or later. 15 * See the COPYING file in the top-level directory. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu-common.h" 20 #include "migration/vmstate.h" 21 #include "hw/sysbus.h" 22 #include "hw/irq.h" 23 #include "qemu/timer.h" 24 #include "hw/misc/mac_via.h" 25 #include "hw/misc/mos6522.h" 26 #include "hw/input/adb.h" 27 #include "sysemu/runstate.h" 28 #include "qapi/error.h" 29 #include "qemu/cutils.h" 30 #include "hw/qdev-properties.h" 31 #include "hw/qdev-properties-system.h" 32 #include "sysemu/block-backend.h" 33 #include "trace.h" 34 #include "qemu/log.h" 35 36 /* 37 * VIAs: There are two in every machine, 38 */ 39 40 #define VIA_SIZE (0x2000) 41 42 /* 43 * Not all of these are true post MacII I think. 44 * CSA: probably the ones CHRP marks as 'unused' change purposes 45 * when the IWM becomes the SWIM. 46 * http://www.rs6000.ibm.com/resource/technology/chrpio/via5.mak.html 47 * ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf 48 * 49 * also, http://developer.apple.com/technotes/hw/hw_09.html claims the 50 * following changes for IIfx: 51 * VIA1A_vSccWrReq not available and that VIA1A_vSync has moved to an IOP. 52 * Also, "All of the functionality of VIA2 has been moved to other chips". 53 */ 54 55 #define VIA1A_vSccWrReq 0x80 /* 56 * SCC write. (input) 57 * [CHRP] SCC WREQ: Reflects the state of the 58 * Wait/Request pins from the SCC. 59 * [Macintosh Family Hardware] 60 * as CHRP on SE/30,II,IIx,IIcx,IIci. 61 * on IIfx, "0 means an active request" 62 */ 63 #define VIA1A_vRev8 0x40 /* 64 * Revision 8 board ??? 65 * [CHRP] En WaitReqB: Lets the WaitReq_L 66 * signal from port B of the SCC appear on 67 * the PA7 input pin. Output. 68 * [Macintosh Family] On the SE/30, this 69 * is the bit to flip screen buffers. 70 * 0=alternate, 1=main. 71 * on II,IIx,IIcx,IIci,IIfx this is a bit 72 * for Rev ID. 0=II,IIx, 1=IIcx,IIci,IIfx 73 */ 74 #define VIA1A_vHeadSel 0x20 /* 75 * Head select for IWM. 76 * [CHRP] unused. 77 * [Macintosh Family] "Floppy disk 78 * state-control line SEL" on all but IIfx 79 */ 80 #define VIA1A_vOverlay 0x10 /* 81 * [Macintosh Family] On SE/30,II,IIx,IIcx 82 * this bit enables the "Overlay" address 83 * map in the address decoders as it is on 84 * reset for mapping the ROM over the reset 85 * vector. 1=use overlay map. 86 * On the IIci,IIfx it is another bit of the 87 * CPU ID: 0=normal IIci, 1=IIci with parity 88 * feature or IIfx. 89 * [CHRP] En WaitReqA: Lets the WaitReq_L 90 * signal from port A of the SCC appear 91 * on the PA7 input pin (CHRP). Output. 92 * [MkLinux] "Drive Select" 93 * (with 0x20 being 'disk head select') 94 */ 95 #define VIA1A_vSync 0x08 /* 96 * [CHRP] Sync Modem: modem clock select: 97 * 1: select the external serial clock to 98 * drive the SCC's /RTxCA pin. 99 * 0: Select the 3.6864MHz clock to drive 100 * the SCC cell. 101 * [Macintosh Family] Correct on all but IIfx 102 */ 103 104 /* 105 * Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control 106 * on Macs which had the PWM sound hardware. Reserved on newer models. 107 * On IIci,IIfx, bits 1-2 are the rest of the CPU ID: 108 * bit 2: 1=IIci, 0=IIfx 109 * bit 1: 1 on both IIci and IIfx. 110 * MkLinux sez bit 0 is 'burnin flag' in this case. 111 * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as 112 * inputs, these bits will read 0. 113 */ 114 #define VIA1A_vVolume 0x07 /* Audio volume mask for PWM */ 115 #define VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */ 116 #define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */ 117 #define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */ 118 #define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */ 119 120 /* 121 * Info on VIA1B is from Macintosh Family Hardware & MkLinux. 122 * CHRP offers no info. 123 */ 124 #define VIA1B_vSound 0x80 /* 125 * Sound enable (for compatibility with 126 * PWM hardware) 0=enabled. 127 * Also, on IIci w/parity, shows parity error 128 * 0=error, 1=OK. 129 */ 130 #define VIA1B_vMystery 0x40 /* 131 * On IIci, parity enable. 0=enabled,1=disabled 132 * On SE/30, vertical sync interrupt enable. 133 * 0=enabled. This vSync interrupt shows up 134 * as a slot $E interrupt. 135 */ 136 #define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */ 137 #define VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */ 138 #define VIA1B_vADBInt 0x08 /* ADB interrupt 0=interrupt (unused on IIfx)*/ 139 #define VIA1B_vRTCEnb 0x04 /* Enable Real time clock. 0=enabled. */ 140 #define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */ 141 #define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */ 142 143 /* 144 * VIA2 A register is the interrupt lines raised off the nubus 145 * slots. 146 * The below info is from 'Macintosh Family Hardware.' 147 * MkLinux calls the 'IIci internal video IRQ' below the 'RBV slot 0 irq.' 148 * It also notes that the slot $9 IRQ is the 'Ethernet IRQ' and 149 * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike. 150 * Perhaps OSS uses vRAM1 and vRAM2 for ADB. 151 */ 152 153 #define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */ 154 #define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ) */ 155 #define VIA2A_vIRQE 0x20 /* IRQ from slot $E */ 156 #define VIA2A_vIRQD 0x10 /* IRQ from slot $D */ 157 #define VIA2A_vIRQC 0x08 /* IRQ from slot $C */ 158 #define VIA2A_vIRQB 0x04 /* IRQ from slot $B */ 159 #define VIA2A_vIRQA 0x02 /* IRQ from slot $A */ 160 #define VIA2A_vIRQ9 0x01 /* IRQ from slot $9 */ 161 162 /* 163 * RAM size bits decoded as follows: 164 * bit1 bit0 size of ICs in bank A 165 * 0 0 256 kbit 166 * 0 1 1 Mbit 167 * 1 0 4 Mbit 168 * 1 1 16 Mbit 169 */ 170 171 /* 172 * Register B has the fun stuff in it 173 */ 174 175 #define VIA2B_vVBL 0x80 /* 176 * VBL output to VIA1 (60.15Hz) driven by 177 * timer T1. 178 * on IIci, parity test: 0=test mode. 179 * [MkLinux] RBV_PARODD: 1=odd,0=even. 180 */ 181 #define VIA2B_vSndJck 0x40 /* 182 * External sound jack status. 183 * 0=plug is inserted. On SE/30, always 0 184 */ 185 #define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */ 186 #define VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */ 187 #define VIA2B_vMode32 0x08 /* 188 * 24/32bit switch - doubles as cache flush 189 * on II, AMU/PMMU control. 190 * if AMU, 0=24bit to 32bit translation 191 * if PMMU, 1=PMMU is accessing page table. 192 * on SE/30 tied low. 193 * on IIx,IIcx,IIfx, unused. 194 * on IIci/RBV, cache control. 0=flush cache. 195 */ 196 #define VIA2B_vPower 0x04 /* 197 * Power off, 0=shut off power. 198 * on SE/30 this signal sent to PDS card. 199 */ 200 #define VIA2B_vBusLk 0x02 /* 201 * Lock NuBus transactions, 0=locked. 202 * on SE/30 sent to PDS card. 203 */ 204 #define VIA2B_vCDis 0x01 /* 205 * Cache control. On IIci, 1=disable cache card 206 * on others, 0=disable processor's instruction 207 * and data caches. 208 */ 209 210 /* interrupt flags */ 211 212 #define IRQ_SET 0x80 213 214 /* common */ 215 216 #define VIA_IRQ_TIMER1 0x40 217 #define VIA_IRQ_TIMER2 0x20 218 219 /* 220 * Apple sez: http://developer.apple.com/technotes/ov/ov_04.html 221 * Another example of a valid function that has no ROM support is the use 222 * of the alternate video page for page-flipping animation. Since there 223 * is no ROM call to flip pages, it is necessary to go play with the 224 * right bit in the VIA chip (6522 Versatile Interface Adapter). 225 * [CSA: don't know which one this is, but it's one of 'em!] 226 */ 227 228 /* 229 * 6522 registers - see databook. 230 * CSA: Assignments for VIA1 confirmed from CHRP spec. 231 */ 232 233 /* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */ 234 /* Note: 15 VIA regs, 8 RBV regs */ 235 236 #define vBufB 0x0000 /* [VIA/RBV] Register B */ 237 #define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */ 238 #define vDirB 0x0400 /* [VIA only] Data Direction Register B. */ 239 #define vDirA 0x0600 /* [VIA only] Data Direction Register A. */ 240 #define vT1CL 0x0800 /* [VIA only] Timer one counter low. */ 241 #define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */ 242 #define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */ 243 #define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */ 244 #define vT2CL 0x1000 /* [VIA only] Timer two counter low. */ 245 #define vT2CH 0x1200 /* [VIA only] Timer two counter high. */ 246 #define vSR 0x1400 /* [VIA only] Shift register. */ 247 #define vACR 0x1600 /* [VIA only] Auxilary control register. */ 248 #define vPCR 0x1800 /* [VIA only] Peripheral control register. */ 249 /* 250 * CHRP sez never ever to *write* this. 251 * Mac family says never to *change* this. 252 * In fact we need to initialize it once at start. 253 */ 254 #define vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */ 255 #define vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */ 256 #define vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */ 257 258 /* from linux 2.6 drivers/macintosh/via-macii.c */ 259 260 /* Bits in ACR */ 261 262 #define VIA1ACR_vShiftCtrl 0x1c /* Shift register control bits */ 263 #define VIA1ACR_vShiftExtClk 0x0c /* Shift on external clock */ 264 #define VIA1ACR_vShiftOut 0x10 /* Shift out if 1 */ 265 266 /* 267 * Apple Macintosh Family Hardware Refenece 268 * Table 19-10 ADB transaction states 269 */ 270 271 #define ADB_STATE_NEW 0 272 #define ADB_STATE_EVEN 1 273 #define ADB_STATE_ODD 2 274 #define ADB_STATE_IDLE 3 275 276 #define VIA1B_vADB_StateMask (VIA1B_vADBS1 | VIA1B_vADBS2) 277 #define VIA1B_vADB_StateShift 4 278 279 #define VIA_TIMER_FREQ (783360) 280 #define VIA_ADB_POLL_FREQ 50 /* XXX: not real */ 281 282 /* 283 * Guide to the Macintosh Family Hardware ch. 12 "Displays" p. 401 gives the 284 * precise 60Hz interrupt frequency as ~60.15Hz with a period of 16625.8 us 285 */ 286 #define VIA_60HZ_TIMER_PERIOD_NS 16625800 287 288 /* VIA returns time offset from Jan 1, 1904, not 1970 */ 289 #define RTC_OFFSET 2082844800 290 291 enum { 292 REG_0, 293 REG_1, 294 REG_2, 295 REG_3, 296 REG_TEST, 297 REG_WPROTECT, 298 REG_PRAM_ADDR, 299 REG_PRAM_ADDR_LAST = REG_PRAM_ADDR + 19, 300 REG_PRAM_SECT, 301 REG_PRAM_SECT_LAST = REG_PRAM_SECT + 7, 302 REG_INVALID, 303 REG_EMPTY = 0xff, 304 }; 305 306 static void via1_sixty_hz_update(MOS6522Q800VIA1State *v1s) 307 { 308 /* 60 Hz irq */ 309 v1s->next_sixty_hz = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 310 VIA_60HZ_TIMER_PERIOD_NS) / 311 VIA_60HZ_TIMER_PERIOD_NS * VIA_60HZ_TIMER_PERIOD_NS; 312 timer_mod(v1s->sixty_hz_timer, v1s->next_sixty_hz); 313 } 314 315 static void via1_one_second_update(MOS6522Q800VIA1State *v1s) 316 { 317 v1s->next_second = (qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000) / 318 1000 * 1000; 319 timer_mod(v1s->one_second_timer, v1s->next_second); 320 } 321 322 static void via1_sixty_hz(void *opaque) 323 { 324 MOS6522Q800VIA1State *v1s = opaque; 325 MOS6522State *s = MOS6522(v1s); 326 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 327 328 s->ifr |= VIA1_IRQ_60HZ; 329 mdc->update_irq(s); 330 331 via1_sixty_hz_update(v1s); 332 } 333 334 static void via1_one_second(void *opaque) 335 { 336 MOS6522Q800VIA1State *v1s = opaque; 337 MOS6522State *s = MOS6522(v1s); 338 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 339 340 s->ifr |= VIA1_IRQ_ONE_SECOND; 341 mdc->update_irq(s); 342 343 via1_one_second_update(v1s); 344 } 345 346 static void via1_irq_request(void *opaque, int irq, int level) 347 { 348 MOS6522Q800VIA1State *v1s = opaque; 349 MOS6522State *s = MOS6522(v1s); 350 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 351 352 if (level) { 353 s->ifr |= 1 << irq; 354 } else { 355 s->ifr &= ~(1 << irq); 356 } 357 358 mdc->update_irq(s); 359 } 360 361 static void via2_irq_request(void *opaque, int irq, int level) 362 { 363 MOS6522Q800VIA2State *v2s = opaque; 364 MOS6522State *s = MOS6522(v2s); 365 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 366 367 if (level) { 368 s->ifr |= 1 << irq; 369 } else { 370 s->ifr &= ~(1 << irq); 371 } 372 373 mdc->update_irq(s); 374 } 375 376 377 static void pram_update(MacVIAState *m) 378 { 379 if (m->blk) { 380 if (blk_pwrite(m->blk, 0, m->mos6522_via1.PRAM, 381 sizeof(m->mos6522_via1.PRAM), 0) < 0) { 382 qemu_log("pram_update: cannot write to file\n"); 383 } 384 } 385 } 386 387 /* 388 * RTC Commands 389 * 390 * Command byte Register addressed by the command 391 * 392 * z0000001 Seconds register 0 (lowest-order byte) 393 * z0000101 Seconds register 1 394 * z0001001 Seconds register 2 395 * z0001101 Seconds register 3 (highest-order byte) 396 * 00110001 Test register (write-only) 397 * 00110101 Write-Protect Register (write-only) 398 * z010aa01 RAM address 100aa ($10-$13) (first 20 bytes only) 399 * z1aaaa01 RAM address 0aaaa ($00-$0F) (first 20 bytes only) 400 * z0111aaa Extended memory designator and sector number 401 * 402 * For a read request, z=1, for a write z=0 403 * The letter a indicates bits whose value depend on what parameter 404 * RAM byte you want to address 405 */ 406 static int via1_rtc_compact_cmd(uint8_t value) 407 { 408 uint8_t read = value & 0x80; 409 410 value &= 0x7f; 411 412 /* the last 2 bits of a command byte must always be 0b01 ... */ 413 if ((value & 0x78) == 0x38) { 414 /* except for the extended memory designator */ 415 return read | (REG_PRAM_SECT + (value & 0x07)); 416 } 417 if ((value & 0x03) == 0x01) { 418 value >>= 2; 419 if ((value & 0x1c) == 0) { 420 /* seconds registers */ 421 return read | (REG_0 + (value & 0x03)); 422 } else if ((value == 0x0c) && !read) { 423 return REG_TEST; 424 } else if ((value == 0x0d) && !read) { 425 return REG_WPROTECT; 426 } else if ((value & 0x1c) == 0x08) { 427 /* RAM address 0x10 to 0x13 */ 428 return read | (REG_PRAM_ADDR + 0x10 + (value & 0x03)); 429 } else if ((value & 0x43) == 0x41) { 430 /* RAM address 0x00 to 0x0f */ 431 return read | (REG_PRAM_ADDR + (value & 0x0f)); 432 } 433 } 434 return REG_INVALID; 435 } 436 437 static void via1_rtc_update(MacVIAState *m) 438 { 439 MOS6522Q800VIA1State *v1s = &m->mos6522_via1; 440 MOS6522State *s = MOS6522(v1s); 441 int cmd, sector, addr; 442 uint32_t time; 443 444 if (s->b & VIA1B_vRTCEnb) { 445 return; 446 } 447 448 if (s->dirb & VIA1B_vRTCData) { 449 /* send bits to the RTC */ 450 if (!(v1s->last_b & VIA1B_vRTCClk) && (s->b & VIA1B_vRTCClk)) { 451 m->data_out <<= 1; 452 m->data_out |= s->b & VIA1B_vRTCData; 453 m->data_out_cnt++; 454 } 455 trace_via1_rtc_update_data_out(m->data_out_cnt, m->data_out); 456 } else { 457 trace_via1_rtc_update_data_in(m->data_in_cnt, m->data_in); 458 /* receive bits from the RTC */ 459 if ((v1s->last_b & VIA1B_vRTCClk) && 460 !(s->b & VIA1B_vRTCClk) && 461 m->data_in_cnt) { 462 s->b = (s->b & ~VIA1B_vRTCData) | 463 ((m->data_in >> 7) & VIA1B_vRTCData); 464 m->data_in <<= 1; 465 m->data_in_cnt--; 466 } 467 return; 468 } 469 470 if (m->data_out_cnt != 8) { 471 return; 472 } 473 474 m->data_out_cnt = 0; 475 476 trace_via1_rtc_internal_status(m->cmd, m->alt, m->data_out); 477 /* first byte: it's a command */ 478 if (m->cmd == REG_EMPTY) { 479 480 cmd = via1_rtc_compact_cmd(m->data_out); 481 trace_via1_rtc_internal_cmd(cmd); 482 483 if (cmd == REG_INVALID) { 484 trace_via1_rtc_cmd_invalid(m->data_out); 485 return; 486 } 487 488 if (cmd & 0x80) { /* this is a read command */ 489 switch (cmd & 0x7f) { 490 case REG_0...REG_3: /* seconds registers */ 491 /* 492 * register 0 is lowest-order byte 493 * register 3 is highest-order byte 494 */ 495 496 time = m->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) 497 / NANOSECONDS_PER_SECOND); 498 trace_via1_rtc_internal_time(time); 499 m->data_in = (time >> ((cmd & 0x03) << 3)) & 0xff; 500 m->data_in_cnt = 8; 501 trace_via1_rtc_cmd_seconds_read((cmd & 0x7f) - REG_0, 502 m->data_in); 503 break; 504 case REG_PRAM_ADDR...REG_PRAM_ADDR_LAST: 505 /* PRAM address 0x00 -> 0x13 */ 506 m->data_in = v1s->PRAM[(cmd & 0x7f) - REG_PRAM_ADDR]; 507 m->data_in_cnt = 8; 508 trace_via1_rtc_cmd_pram_read((cmd & 0x7f) - REG_PRAM_ADDR, 509 m->data_in); 510 break; 511 case REG_PRAM_SECT...REG_PRAM_SECT_LAST: 512 /* 513 * extended memory designator and sector number 514 * the only two-byte read command 515 */ 516 trace_via1_rtc_internal_set_cmd(cmd); 517 m->cmd = cmd; 518 break; 519 default: 520 g_assert_not_reached(); 521 break; 522 } 523 return; 524 } 525 526 /* this is a write command, needs a parameter */ 527 if (cmd == REG_WPROTECT || !m->wprotect) { 528 trace_via1_rtc_internal_set_cmd(cmd); 529 m->cmd = cmd; 530 } else { 531 trace_via1_rtc_internal_ignore_cmd(cmd); 532 } 533 return; 534 } 535 536 /* second byte: it's a parameter */ 537 if (m->alt == REG_EMPTY) { 538 switch (m->cmd & 0x7f) { 539 case REG_0...REG_3: /* seconds register */ 540 /* FIXME */ 541 trace_via1_rtc_cmd_seconds_write(m->cmd - REG_0, m->data_out); 542 m->cmd = REG_EMPTY; 543 break; 544 case REG_TEST: 545 /* device control: nothing to do */ 546 trace_via1_rtc_cmd_test_write(m->data_out); 547 m->cmd = REG_EMPTY; 548 break; 549 case REG_WPROTECT: 550 /* Write Protect register */ 551 trace_via1_rtc_cmd_wprotect_write(m->data_out); 552 m->wprotect = !!(m->data_out & 0x80); 553 m->cmd = REG_EMPTY; 554 break; 555 case REG_PRAM_ADDR...REG_PRAM_ADDR_LAST: 556 /* PRAM address 0x00 -> 0x13 */ 557 trace_via1_rtc_cmd_pram_write(m->cmd - REG_PRAM_ADDR, m->data_out); 558 v1s->PRAM[m->cmd - REG_PRAM_ADDR] = m->data_out; 559 pram_update(m); 560 m->cmd = REG_EMPTY; 561 break; 562 case REG_PRAM_SECT...REG_PRAM_SECT_LAST: 563 addr = (m->data_out >> 2) & 0x1f; 564 sector = (m->cmd & 0x7f) - REG_PRAM_SECT; 565 if (m->cmd & 0x80) { 566 /* it's a read */ 567 m->data_in = v1s->PRAM[sector * 32 + addr]; 568 m->data_in_cnt = 8; 569 trace_via1_rtc_cmd_pram_sect_read(sector, addr, 570 sector * 32 + addr, 571 m->data_in); 572 m->cmd = REG_EMPTY; 573 } else { 574 /* it's a write, we need one more parameter */ 575 trace_via1_rtc_internal_set_alt(addr, sector, addr); 576 m->alt = addr; 577 } 578 break; 579 default: 580 g_assert_not_reached(); 581 break; 582 } 583 return; 584 } 585 586 /* third byte: it's the data of a REG_PRAM_SECT write */ 587 g_assert(REG_PRAM_SECT <= m->cmd && m->cmd <= REG_PRAM_SECT_LAST); 588 sector = m->cmd - REG_PRAM_SECT; 589 v1s->PRAM[sector * 32 + m->alt] = m->data_out; 590 pram_update(m); 591 trace_via1_rtc_cmd_pram_sect_write(sector, m->alt, sector * 32 + m->alt, 592 m->data_out); 593 m->alt = REG_EMPTY; 594 m->cmd = REG_EMPTY; 595 } 596 597 static void adb_via_poll(void *opaque) 598 { 599 MacVIAState *m = opaque; 600 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&m->mos6522_via1); 601 MOS6522State *s = MOS6522(v1s); 602 ADBBusState *adb_bus = &m->adb_bus; 603 uint8_t obuf[9]; 604 uint8_t *data = &s->sr; 605 int olen; 606 607 /* 608 * Setting vADBInt below indicates that an autopoll reply has been 609 * received, however we must block autopoll until the point where 610 * the entire reply has been read back to the host 611 */ 612 adb_autopoll_block(adb_bus); 613 614 if (m->adb_data_in_size > 0 && m->adb_data_in_index == 0) { 615 /* 616 * For older Linux kernels that switch to IDLE mode after sending the 617 * ADB command, detect if there is an existing response and return that 618 * as a a "fake" autopoll reply or bus timeout accordingly 619 */ 620 *data = m->adb_data_out[0]; 621 olen = m->adb_data_in_size; 622 623 s->b &= ~VIA1B_vADBInt; 624 qemu_irq_raise(m->adb_data_ready); 625 } else { 626 /* 627 * Otherwise poll as normal 628 */ 629 m->adb_data_in_index = 0; 630 m->adb_data_out_index = 0; 631 olen = adb_poll(adb_bus, obuf, adb_bus->autopoll_mask); 632 633 if (olen > 0) { 634 /* Autopoll response */ 635 *data = obuf[0]; 636 olen--; 637 memcpy(m->adb_data_in, &obuf[1], olen); 638 m->adb_data_in_size = olen; 639 640 s->b &= ~VIA1B_vADBInt; 641 qemu_irq_raise(m->adb_data_ready); 642 } else { 643 *data = m->adb_autopoll_cmd; 644 obuf[0] = 0xff; 645 obuf[1] = 0xff; 646 olen = 2; 647 648 memcpy(m->adb_data_in, obuf, olen); 649 m->adb_data_in_size = olen; 650 651 s->b &= ~VIA1B_vADBInt; 652 qemu_irq_raise(m->adb_data_ready); 653 } 654 } 655 656 trace_via1_adb_poll(*data, (s->b & VIA1B_vADBInt) ? "+" : "-", 657 adb_bus->status, m->adb_data_in_index, olen); 658 } 659 660 static int adb_via_send_len(uint8_t data) 661 { 662 /* Determine the send length from the given ADB command */ 663 uint8_t cmd = data & 0xc; 664 uint8_t reg = data & 0x3; 665 666 switch (cmd) { 667 case 0x8: 668 /* Listen command */ 669 switch (reg) { 670 case 2: 671 /* Register 2 is only used for the keyboard */ 672 return 3; 673 case 3: 674 /* 675 * Fortunately our devices only implement writes 676 * to register 3 which is fixed at 2 bytes 677 */ 678 return 3; 679 default: 680 qemu_log_mask(LOG_UNIMP, "ADB unknown length for register %d\n", 681 reg); 682 return 1; 683 } 684 default: 685 /* Talk, BusReset */ 686 return 1; 687 } 688 } 689 690 static void adb_via_send(MacVIAState *s, int state, uint8_t data) 691 { 692 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&s->mos6522_via1); 693 MOS6522State *ms = MOS6522(v1s); 694 ADBBusState *adb_bus = &s->adb_bus; 695 uint16_t autopoll_mask; 696 697 switch (state) { 698 case ADB_STATE_NEW: 699 /* 700 * Command byte: vADBInt tells host autopoll data already present 701 * in VIA shift register and ADB transceiver 702 */ 703 adb_autopoll_block(adb_bus); 704 705 if (adb_bus->status & ADB_STATUS_POLLREPLY) { 706 /* Tell the host the existing data is from autopoll */ 707 ms->b &= ~VIA1B_vADBInt; 708 } else { 709 ms->b |= VIA1B_vADBInt; 710 s->adb_data_out_index = 0; 711 s->adb_data_out[s->adb_data_out_index++] = data; 712 } 713 714 trace_via1_adb_send(" NEW", data, (ms->b & VIA1B_vADBInt) ? "+" : "-"); 715 qemu_irq_raise(s->adb_data_ready); 716 break; 717 718 case ADB_STATE_EVEN: 719 case ADB_STATE_ODD: 720 ms->b |= VIA1B_vADBInt; 721 s->adb_data_out[s->adb_data_out_index++] = data; 722 723 trace_via1_adb_send(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 724 data, (ms->b & VIA1B_vADBInt) ? "+" : "-"); 725 qemu_irq_raise(s->adb_data_ready); 726 break; 727 728 case ADB_STATE_IDLE: 729 return; 730 } 731 732 /* If the command is complete, execute it */ 733 if (s->adb_data_out_index == adb_via_send_len(s->adb_data_out[0])) { 734 s->adb_data_in_size = adb_request(adb_bus, s->adb_data_in, 735 s->adb_data_out, 736 s->adb_data_out_index); 737 s->adb_data_in_index = 0; 738 739 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 740 /* 741 * Bus timeout (but allow first EVEN and ODD byte to indicate 742 * timeout via vADBInt and SRQ status) 743 */ 744 s->adb_data_in[0] = 0xff; 745 s->adb_data_in[1] = 0xff; 746 s->adb_data_in_size = 2; 747 } 748 749 /* 750 * If last command is TALK, store it for use by autopoll and adjust 751 * the autopoll mask accordingly 752 */ 753 if ((s->adb_data_out[0] & 0xc) == 0xc) { 754 s->adb_autopoll_cmd = s->adb_data_out[0]; 755 756 autopoll_mask = 1 << (s->adb_autopoll_cmd >> 4); 757 adb_set_autopoll_mask(adb_bus, autopoll_mask); 758 } 759 } 760 } 761 762 static void adb_via_receive(MacVIAState *s, int state, uint8_t *data) 763 { 764 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&s->mos6522_via1); 765 MOS6522State *ms = MOS6522(v1s); 766 ADBBusState *adb_bus = &s->adb_bus; 767 uint16_t pending; 768 769 switch (state) { 770 case ADB_STATE_NEW: 771 ms->b |= VIA1B_vADBInt; 772 return; 773 774 case ADB_STATE_IDLE: 775 ms->b |= VIA1B_vADBInt; 776 adb_autopoll_unblock(adb_bus); 777 778 trace_via1_adb_receive("IDLE", *data, 779 (ms->b & VIA1B_vADBInt) ? "+" : "-", adb_bus->status, 780 s->adb_data_in_index, s->adb_data_in_size); 781 782 break; 783 784 case ADB_STATE_EVEN: 785 case ADB_STATE_ODD: 786 switch (s->adb_data_in_index) { 787 case 0: 788 /* First EVEN byte: vADBInt indicates bus timeout */ 789 *data = s->adb_data_in[s->adb_data_in_index]; 790 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 791 ms->b &= ~VIA1B_vADBInt; 792 } else { 793 ms->b |= VIA1B_vADBInt; 794 } 795 796 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 797 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 798 adb_bus->status, s->adb_data_in_index, 799 s->adb_data_in_size); 800 801 s->adb_data_in_index++; 802 break; 803 804 case 1: 805 /* First ODD byte: vADBInt indicates SRQ */ 806 *data = s->adb_data_in[s->adb_data_in_index]; 807 pending = adb_bus->pending & ~(1 << (s->adb_autopoll_cmd >> 4)); 808 if (pending) { 809 ms->b &= ~VIA1B_vADBInt; 810 } else { 811 ms->b |= VIA1B_vADBInt; 812 } 813 814 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 815 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 816 adb_bus->status, s->adb_data_in_index, 817 s->adb_data_in_size); 818 819 s->adb_data_in_index++; 820 break; 821 822 default: 823 /* 824 * Otherwise vADBInt indicates end of data. Note that Linux 825 * specifically checks for the sequence 0x0 0xff to confirm the 826 * end of the poll reply, so provide these extra bytes below to 827 * keep it happy 828 */ 829 if (s->adb_data_in_index < s->adb_data_in_size) { 830 /* Next data byte */ 831 *data = s->adb_data_in[s->adb_data_in_index]; 832 ms->b |= VIA1B_vADBInt; 833 } else if (s->adb_data_in_index == s->adb_data_in_size) { 834 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 835 /* Bus timeout (no more data) */ 836 *data = 0xff; 837 } else { 838 /* Return 0x0 after reply */ 839 *data = 0; 840 } 841 ms->b &= ~VIA1B_vADBInt; 842 } else { 843 /* Bus timeout (no more data) */ 844 *data = 0xff; 845 ms->b &= ~VIA1B_vADBInt; 846 adb_bus->status = 0; 847 adb_autopoll_unblock(adb_bus); 848 } 849 850 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 851 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 852 adb_bus->status, s->adb_data_in_index, 853 s->adb_data_in_size); 854 855 if (s->adb_data_in_index <= s->adb_data_in_size) { 856 s->adb_data_in_index++; 857 } 858 break; 859 } 860 861 qemu_irq_raise(s->adb_data_ready); 862 break; 863 } 864 } 865 866 static void via1_adb_update(MacVIAState *m) 867 { 868 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&m->mos6522_via1); 869 MOS6522State *s = MOS6522(v1s); 870 int oldstate, state; 871 872 oldstate = (v1s->last_b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; 873 state = (s->b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; 874 875 if (state != oldstate) { 876 if (s->acr & VIA1ACR_vShiftOut) { 877 /* output mode */ 878 adb_via_send(m, state, s->sr); 879 } else { 880 /* input mode */ 881 adb_via_receive(m, state, &s->sr); 882 } 883 } 884 } 885 886 static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned size) 887 { 888 MOS6522Q800VIA1State *s = MOS6522_Q800_VIA1(opaque); 889 MOS6522State *ms = MOS6522(s); 890 891 addr = (addr >> 9) & 0xf; 892 return mos6522_read(ms, addr, size); 893 } 894 895 static void mos6522_q800_via1_write(void *opaque, hwaddr addr, uint64_t val, 896 unsigned size) 897 { 898 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque); 899 MacVIAState *m = container_of(v1s, MacVIAState, mos6522_via1); 900 MOS6522State *ms = MOS6522(v1s); 901 902 addr = (addr >> 9) & 0xf; 903 mos6522_write(ms, addr, val, size); 904 905 switch (addr) { 906 case VIA_REG_B: 907 via1_rtc_update(m); 908 via1_adb_update(m); 909 910 v1s->last_b = ms->b; 911 break; 912 } 913 } 914 915 static const MemoryRegionOps mos6522_q800_via1_ops = { 916 .read = mos6522_q800_via1_read, 917 .write = mos6522_q800_via1_write, 918 .endianness = DEVICE_BIG_ENDIAN, 919 .valid = { 920 .min_access_size = 1, 921 .max_access_size = 4, 922 }, 923 }; 924 925 static uint64_t mos6522_q800_via2_read(void *opaque, hwaddr addr, unsigned size) 926 { 927 MOS6522Q800VIA2State *s = MOS6522_Q800_VIA2(opaque); 928 MOS6522State *ms = MOS6522(s); 929 930 addr = (addr >> 9) & 0xf; 931 return mos6522_read(ms, addr, size); 932 } 933 934 static void mos6522_q800_via2_write(void *opaque, hwaddr addr, uint64_t val, 935 unsigned size) 936 { 937 MOS6522Q800VIA2State *s = MOS6522_Q800_VIA2(opaque); 938 MOS6522State *ms = MOS6522(s); 939 940 addr = (addr >> 9) & 0xf; 941 mos6522_write(ms, addr, val, size); 942 } 943 944 static const MemoryRegionOps mos6522_q800_via2_ops = { 945 .read = mos6522_q800_via2_read, 946 .write = mos6522_q800_via2_write, 947 .endianness = DEVICE_BIG_ENDIAN, 948 .valid = { 949 .min_access_size = 1, 950 .max_access_size = 4, 951 }, 952 }; 953 954 static void mac_via_reset(DeviceState *dev) 955 { 956 MacVIAState *m = MAC_VIA(dev); 957 ADBBusState *adb_bus = &m->adb_bus; 958 959 adb_set_autopoll_enabled(adb_bus, true); 960 961 m->cmd = REG_EMPTY; 962 m->alt = REG_EMPTY; 963 } 964 965 static void mac_via_realize(DeviceState *dev, Error **errp) 966 { 967 MacVIAState *m = MAC_VIA(dev); 968 MOS6522State *ms; 969 ADBBusState *adb_bus = &m->adb_bus; 970 struct tm tm; 971 int ret; 972 973 /* Init VIAs 1 and 2 */ 974 object_initialize_child(OBJECT(dev), "via1", &m->mos6522_via1, 975 TYPE_MOS6522_Q800_VIA1); 976 977 object_initialize_child(OBJECT(dev), "via2", &m->mos6522_via2, 978 TYPE_MOS6522_Q800_VIA2); 979 980 /* Pass through mos6522 output IRQs */ 981 ms = MOS6522(&m->mos6522_via1); 982 object_property_add_alias(OBJECT(dev), "irq[0]", OBJECT(ms), 983 SYSBUS_DEVICE_GPIO_IRQ "[0]"); 984 ms = MOS6522(&m->mos6522_via2); 985 object_property_add_alias(OBJECT(dev), "irq[1]", OBJECT(ms), 986 SYSBUS_DEVICE_GPIO_IRQ "[0]"); 987 988 sysbus_realize(SYS_BUS_DEVICE(&m->mos6522_via1), &error_abort); 989 sysbus_realize(SYS_BUS_DEVICE(&m->mos6522_via2), &error_abort); 990 991 /* Pass through mos6522 input IRQs */ 992 qdev_pass_gpios(DEVICE(&m->mos6522_via1), dev, "via1-irq"); 993 qdev_pass_gpios(DEVICE(&m->mos6522_via2), dev, "via2-irq"); 994 995 /* VIA 1 */ 996 m->mos6522_via1.one_second_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 997 via1_one_second, 998 &m->mos6522_via1); 999 via1_one_second_update(&m->mos6522_via1); 1000 m->mos6522_via1.sixty_hz_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1001 via1_sixty_hz, 1002 &m->mos6522_via1); 1003 via1_sixty_hz_update(&m->mos6522_via1); 1004 1005 qemu_get_timedate(&tm, 0); 1006 m->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; 1007 1008 adb_register_autopoll_callback(adb_bus, adb_via_poll, m); 1009 m->adb_data_ready = qdev_get_gpio_in_named(dev, "via1-irq", 1010 VIA1_IRQ_ADB_READY_BIT); 1011 1012 if (m->blk) { 1013 int64_t len = blk_getlength(m->blk); 1014 if (len < 0) { 1015 error_setg_errno(errp, -len, 1016 "could not get length of backing image"); 1017 return; 1018 } 1019 ret = blk_set_perm(m->blk, 1020 BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE, 1021 BLK_PERM_ALL, errp); 1022 if (ret < 0) { 1023 return; 1024 } 1025 1026 len = blk_pread(m->blk, 0, m->mos6522_via1.PRAM, 1027 sizeof(m->mos6522_via1.PRAM)); 1028 if (len != sizeof(m->mos6522_via1.PRAM)) { 1029 error_setg(errp, "can't read PRAM contents"); 1030 return; 1031 } 1032 } 1033 } 1034 1035 static void mac_via_init(Object *obj) 1036 { 1037 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1038 MacVIAState *m = MAC_VIA(obj); 1039 1040 /* MMIO */ 1041 memory_region_init(&m->mmio, obj, "mac-via", 2 * VIA_SIZE); 1042 sysbus_init_mmio(sbd, &m->mmio); 1043 1044 memory_region_init_io(&m->via1mem, obj, &mos6522_q800_via1_ops, 1045 &m->mos6522_via1, "via1", VIA_SIZE); 1046 memory_region_add_subregion(&m->mmio, 0x0, &m->via1mem); 1047 1048 memory_region_init_io(&m->via2mem, obj, &mos6522_q800_via2_ops, 1049 &m->mos6522_via2, "via2", VIA_SIZE); 1050 memory_region_add_subregion(&m->mmio, VIA_SIZE, &m->via2mem); 1051 1052 /* ADB */ 1053 qbus_create_inplace((BusState *)&m->adb_bus, sizeof(m->adb_bus), 1054 TYPE_ADB_BUS, DEVICE(obj), "adb.0"); 1055 } 1056 1057 static void postload_update_cb(void *opaque, bool running, RunState state) 1058 { 1059 MacVIAState *m = MAC_VIA(opaque); 1060 1061 qemu_del_vm_change_state_handler(m->vmstate); 1062 m->vmstate = NULL; 1063 1064 pram_update(m); 1065 } 1066 1067 static int mac_via_post_load(void *opaque, int version_id) 1068 { 1069 MacVIAState *m = MAC_VIA(opaque); 1070 1071 if (m->blk) { 1072 m->vmstate = qemu_add_vm_change_state_handler(postload_update_cb, 1073 m); 1074 } 1075 1076 return 0; 1077 } 1078 1079 static const VMStateDescription vmstate_mac_via = { 1080 .name = "mac-via", 1081 .version_id = 2, 1082 .minimum_version_id = 2, 1083 .post_load = mac_via_post_load, 1084 .fields = (VMStateField[]) { 1085 /* VIAs */ 1086 VMSTATE_STRUCT(mos6522_via1.parent_obj, MacVIAState, 0, vmstate_mos6522, 1087 MOS6522State), 1088 VMSTATE_UINT8(mos6522_via1.last_b, MacVIAState), 1089 VMSTATE_BUFFER(mos6522_via1.PRAM, MacVIAState), 1090 VMSTATE_TIMER_PTR(mos6522_via1.one_second_timer, MacVIAState), 1091 VMSTATE_INT64(mos6522_via1.next_second, MacVIAState), 1092 VMSTATE_TIMER_PTR(mos6522_via1.sixty_hz_timer, MacVIAState), 1093 VMSTATE_INT64(mos6522_via1.next_sixty_hz, MacVIAState), 1094 VMSTATE_STRUCT(mos6522_via2.parent_obj, MacVIAState, 0, vmstate_mos6522, 1095 MOS6522State), 1096 /* RTC */ 1097 VMSTATE_UINT32(tick_offset, MacVIAState), 1098 VMSTATE_UINT8(data_out, MacVIAState), 1099 VMSTATE_INT32(data_out_cnt, MacVIAState), 1100 VMSTATE_UINT8(data_in, MacVIAState), 1101 VMSTATE_UINT8(data_in_cnt, MacVIAState), 1102 VMSTATE_UINT8(cmd, MacVIAState), 1103 VMSTATE_INT32(wprotect, MacVIAState), 1104 VMSTATE_INT32(alt, MacVIAState), 1105 /* ADB */ 1106 VMSTATE_INT32(adb_data_in_size, MacVIAState), 1107 VMSTATE_INT32(adb_data_in_index, MacVIAState), 1108 VMSTATE_INT32(adb_data_out_index, MacVIAState), 1109 VMSTATE_BUFFER(adb_data_in, MacVIAState), 1110 VMSTATE_BUFFER(adb_data_out, MacVIAState), 1111 VMSTATE_UINT8(adb_autopoll_cmd, MacVIAState), 1112 VMSTATE_END_OF_LIST() 1113 } 1114 }; 1115 1116 static Property mac_via_properties[] = { 1117 DEFINE_PROP_DRIVE("drive", MacVIAState, blk), 1118 DEFINE_PROP_END_OF_LIST(), 1119 }; 1120 1121 static void mac_via_class_init(ObjectClass *oc, void *data) 1122 { 1123 DeviceClass *dc = DEVICE_CLASS(oc); 1124 1125 dc->realize = mac_via_realize; 1126 dc->reset = mac_via_reset; 1127 dc->vmsd = &vmstate_mac_via; 1128 device_class_set_props(dc, mac_via_properties); 1129 } 1130 1131 static TypeInfo mac_via_info = { 1132 .name = TYPE_MAC_VIA, 1133 .parent = TYPE_SYS_BUS_DEVICE, 1134 .instance_size = sizeof(MacVIAState), 1135 .instance_init = mac_via_init, 1136 .class_init = mac_via_class_init, 1137 }; 1138 1139 /* VIA 1 */ 1140 static void mos6522_q800_via1_reset(DeviceState *dev) 1141 { 1142 MOS6522State *ms = MOS6522(dev); 1143 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); 1144 1145 mdc->parent_reset(dev); 1146 1147 ms->timers[0].frequency = VIA_TIMER_FREQ; 1148 ms->timers[1].frequency = VIA_TIMER_FREQ; 1149 1150 ms->b = VIA1B_vADB_StateMask | VIA1B_vADBInt | VIA1B_vRTCEnb; 1151 } 1152 1153 static void mos6522_q800_via1_init(Object *obj) 1154 { 1155 qdev_init_gpio_in_named(DEVICE(obj), via1_irq_request, "via1-irq", 1156 VIA1_IRQ_NB); 1157 } 1158 1159 static void mos6522_q800_via1_class_init(ObjectClass *oc, void *data) 1160 { 1161 DeviceClass *dc = DEVICE_CLASS(oc); 1162 1163 dc->reset = mos6522_q800_via1_reset; 1164 } 1165 1166 static const TypeInfo mos6522_q800_via1_type_info = { 1167 .name = TYPE_MOS6522_Q800_VIA1, 1168 .parent = TYPE_MOS6522, 1169 .instance_size = sizeof(MOS6522Q800VIA1State), 1170 .instance_init = mos6522_q800_via1_init, 1171 .class_init = mos6522_q800_via1_class_init, 1172 }; 1173 1174 /* VIA 2 */ 1175 static void mos6522_q800_via2_portB_write(MOS6522State *s) 1176 { 1177 if (s->dirb & VIA2B_vPower && (s->b & VIA2B_vPower) == 0) { 1178 /* shutdown */ 1179 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 1180 } 1181 } 1182 1183 static void mos6522_q800_via2_reset(DeviceState *dev) 1184 { 1185 MOS6522State *ms = MOS6522(dev); 1186 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); 1187 1188 mdc->parent_reset(dev); 1189 1190 ms->timers[0].frequency = VIA_TIMER_FREQ; 1191 ms->timers[1].frequency = VIA_TIMER_FREQ; 1192 1193 ms->dirb = 0; 1194 ms->b = 0; 1195 } 1196 1197 static void mos6522_q800_via2_init(Object *obj) 1198 { 1199 qdev_init_gpio_in_named(DEVICE(obj), via2_irq_request, "via2-irq", 1200 VIA2_IRQ_NB); 1201 } 1202 1203 static void mos6522_q800_via2_class_init(ObjectClass *oc, void *data) 1204 { 1205 DeviceClass *dc = DEVICE_CLASS(oc); 1206 MOS6522DeviceClass *mdc = MOS6522_CLASS(oc); 1207 1208 dc->reset = mos6522_q800_via2_reset; 1209 mdc->portB_write = mos6522_q800_via2_portB_write; 1210 } 1211 1212 static const TypeInfo mos6522_q800_via2_type_info = { 1213 .name = TYPE_MOS6522_Q800_VIA2, 1214 .parent = TYPE_MOS6522, 1215 .instance_size = sizeof(MOS6522Q800VIA2State), 1216 .instance_init = mos6522_q800_via2_init, 1217 .class_init = mos6522_q800_via2_class_init, 1218 }; 1219 1220 static void mac_via_register_types(void) 1221 { 1222 type_register_static(&mos6522_q800_via1_type_info); 1223 type_register_static(&mos6522_q800_via2_type_info); 1224 type_register_static(&mac_via_info); 1225 } 1226 1227 type_init(mac_via_register_types); 1228