1 /* 2 * ARM IoTKit system control element 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* 13 * This is a model of the "system control element" which is part of the 14 * Arm IoTKit and documented in 15 * https://developer.arm.com/documentation/ecm0601256/latest 16 * Specifically, it implements the "system control register" blocks. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/bitops.h" 21 #include "qemu/log.h" 22 #include "qemu/module.h" 23 #include "sysemu/runstate.h" 24 #include "trace.h" 25 #include "qapi/error.h" 26 #include "hw/sysbus.h" 27 #include "migration/vmstate.h" 28 #include "hw/registerfields.h" 29 #include "hw/misc/iotkit-sysctl.h" 30 #include "hw/qdev-properties.h" 31 #include "hw/arm/armsse-version.h" 32 #include "target/arm/arm-powerctl.h" 33 #include "target/arm/cpu.h" 34 35 REG32(SECDBGSTAT, 0x0) 36 REG32(SECDBGSET, 0x4) 37 REG32(SECDBGCLR, 0x8) 38 REG32(SCSECCTRL, 0xc) 39 REG32(FCLK_DIV, 0x10) 40 REG32(SYSCLK_DIV, 0x14) 41 REG32(CLOCK_FORCE, 0x18) 42 REG32(RESET_SYNDROME, 0x100) 43 REG32(RESET_MASK, 0x104) 44 REG32(SWRESET, 0x108) 45 FIELD(SWRESET, SWRESETREQ, 9, 1) 46 REG32(GRETREG, 0x10c) 47 REG32(INITSVTOR0, 0x110) 48 REG32(INITSVTOR1, 0x114) 49 REG32(CPUWAIT, 0x118) 50 REG32(NMI_ENABLE, 0x11c) /* BUSWAIT in IoTKit */ 51 REG32(WICCTRL, 0x120) 52 REG32(EWCTRL, 0x124) 53 REG32(PDCM_PD_SYS_SENSE, 0x200) 54 REG32(PDCM_PD_SRAM0_SENSE, 0x20c) 55 REG32(PDCM_PD_SRAM1_SENSE, 0x210) 56 REG32(PDCM_PD_SRAM2_SENSE, 0x214) 57 REG32(PDCM_PD_SRAM3_SENSE, 0x218) 58 REG32(PID4, 0xfd0) 59 REG32(PID5, 0xfd4) 60 REG32(PID6, 0xfd8) 61 REG32(PID7, 0xfdc) 62 REG32(PID0, 0xfe0) 63 REG32(PID1, 0xfe4) 64 REG32(PID2, 0xfe8) 65 REG32(PID3, 0xfec) 66 REG32(CID0, 0xff0) 67 REG32(CID1, 0xff4) 68 REG32(CID2, 0xff8) 69 REG32(CID3, 0xffc) 70 71 /* PID/CID values */ 72 static const int sysctl_id[] = { 73 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ 74 0x54, 0xb8, 0x0b, 0x00, /* PID0..PID3 */ 75 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ 76 }; 77 78 /* 79 * Set the initial secure vector table offset address for the core. 80 * This will take effect when the CPU next resets. 81 */ 82 static void set_init_vtor(uint64_t cpuid, uint32_t vtor) 83 { 84 Object *cpuobj = OBJECT(arm_get_cpu_by_id(cpuid)); 85 86 if (cpuobj) { 87 if (object_property_find(cpuobj, "init-svtor")) { 88 object_property_set_uint(cpuobj, "init-svtor", vtor, &error_abort); 89 } 90 } 91 } 92 93 static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset, 94 unsigned size) 95 { 96 IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque); 97 uint64_t r; 98 99 switch (offset) { 100 case A_SECDBGSTAT: 101 r = s->secure_debug; 102 break; 103 case A_SCSECCTRL: 104 switch (s->sse_version) { 105 case ARMSSE_IOTKIT: 106 goto bad_offset; 107 case ARMSSE_SSE200: 108 r = s->scsecctrl; 109 break; 110 default: 111 g_assert_not_reached(); 112 } 113 break; 114 case A_FCLK_DIV: 115 switch (s->sse_version) { 116 case ARMSSE_IOTKIT: 117 goto bad_offset; 118 case ARMSSE_SSE200: 119 r = s->fclk_div; 120 break; 121 default: 122 g_assert_not_reached(); 123 } 124 break; 125 case A_SYSCLK_DIV: 126 switch (s->sse_version) { 127 case ARMSSE_IOTKIT: 128 goto bad_offset; 129 case ARMSSE_SSE200: 130 r = s->sysclk_div; 131 break; 132 default: 133 g_assert_not_reached(); 134 } 135 break; 136 case A_CLOCK_FORCE: 137 switch (s->sse_version) { 138 case ARMSSE_IOTKIT: 139 goto bad_offset; 140 case ARMSSE_SSE200: 141 r = s->clock_force; 142 break; 143 default: 144 g_assert_not_reached(); 145 } 146 break; 147 case A_RESET_SYNDROME: 148 r = s->reset_syndrome; 149 break; 150 case A_RESET_MASK: 151 r = s->reset_mask; 152 break; 153 case A_GRETREG: 154 r = s->gretreg; 155 break; 156 case A_INITSVTOR0: 157 r = s->initsvtor0; 158 break; 159 case A_INITSVTOR1: 160 switch (s->sse_version) { 161 case ARMSSE_IOTKIT: 162 goto bad_offset; 163 case ARMSSE_SSE200: 164 r = s->initsvtor1; 165 break; 166 default: 167 g_assert_not_reached(); 168 } 169 break; 170 case A_CPUWAIT: 171 r = s->cpuwait; 172 break; 173 case A_NMI_ENABLE: 174 switch (s->sse_version) { 175 case ARMSSE_IOTKIT: 176 /* In IoTKit this is named BUSWAIT but marked reserved, R/O, zero */ 177 r = 0; 178 break; 179 case ARMSSE_SSE200: 180 r = s->nmi_enable; 181 break; 182 default: 183 g_assert_not_reached(); 184 } 185 break; 186 case A_WICCTRL: 187 r = s->wicctrl; 188 break; 189 case A_EWCTRL: 190 switch (s->sse_version) { 191 case ARMSSE_IOTKIT: 192 goto bad_offset; 193 case ARMSSE_SSE200: 194 r = s->ewctrl; 195 break; 196 default: 197 g_assert_not_reached(); 198 } 199 break; 200 case A_PDCM_PD_SYS_SENSE: 201 switch (s->sse_version) { 202 case ARMSSE_IOTKIT: 203 goto bad_offset; 204 case ARMSSE_SSE200: 205 r = s->pdcm_pd_sys_sense; 206 break; 207 default: 208 g_assert_not_reached(); 209 } 210 break; 211 case A_PDCM_PD_SRAM0_SENSE: 212 switch (s->sse_version) { 213 case ARMSSE_IOTKIT: 214 goto bad_offset; 215 case ARMSSE_SSE200: 216 r = s->pdcm_pd_sram0_sense; 217 break; 218 default: 219 g_assert_not_reached(); 220 } 221 break; 222 case A_PDCM_PD_SRAM1_SENSE: 223 switch (s->sse_version) { 224 case ARMSSE_IOTKIT: 225 goto bad_offset; 226 case ARMSSE_SSE200: 227 r = s->pdcm_pd_sram1_sense; 228 break; 229 default: 230 g_assert_not_reached(); 231 } 232 break; 233 case A_PDCM_PD_SRAM2_SENSE: 234 switch (s->sse_version) { 235 case ARMSSE_IOTKIT: 236 goto bad_offset; 237 case ARMSSE_SSE200: 238 r = s->pdcm_pd_sram2_sense; 239 break; 240 default: 241 g_assert_not_reached(); 242 } 243 break; 244 case A_PDCM_PD_SRAM3_SENSE: 245 switch (s->sse_version) { 246 case ARMSSE_IOTKIT: 247 goto bad_offset; 248 case ARMSSE_SSE200: 249 r = s->pdcm_pd_sram3_sense; 250 break; 251 default: 252 g_assert_not_reached(); 253 } 254 break; 255 case A_PID4 ... A_CID3: 256 r = sysctl_id[(offset - A_PID4) / 4]; 257 break; 258 case A_SECDBGSET: 259 case A_SECDBGCLR: 260 case A_SWRESET: 261 qemu_log_mask(LOG_GUEST_ERROR, 262 "IoTKit SysCtl read: read of WO offset %x\n", 263 (int)offset); 264 r = 0; 265 break; 266 default: 267 bad_offset: 268 qemu_log_mask(LOG_GUEST_ERROR, 269 "IoTKit SysCtl read: bad offset %x\n", (int)offset); 270 r = 0; 271 break; 272 } 273 trace_iotkit_sysctl_read(offset, r, size); 274 return r; 275 } 276 277 static void iotkit_sysctl_write(void *opaque, hwaddr offset, 278 uint64_t value, unsigned size) 279 { 280 IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque); 281 282 trace_iotkit_sysctl_write(offset, value, size); 283 284 /* 285 * Most of the state here has to do with control of reset and 286 * similar kinds of power up -- for instance the guest can ask 287 * what the reason for the last reset was, or forbid reset for 288 * some causes (like the non-secure watchdog). Most of this is 289 * not relevant to QEMU, which doesn't really model anything other 290 * than a full power-on reset. 291 * We just model the registers as reads-as-written. 292 */ 293 294 switch (offset) { 295 case A_RESET_SYNDROME: 296 qemu_log_mask(LOG_UNIMP, 297 "IoTKit SysCtl RESET_SYNDROME unimplemented\n"); 298 s->reset_syndrome = value; 299 break; 300 case A_RESET_MASK: 301 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl RESET_MASK unimplemented\n"); 302 s->reset_mask = value; 303 break; 304 case A_GRETREG: 305 /* 306 * General retention register, which is only reset by a power-on 307 * reset. Technically this implementation is complete, since 308 * QEMU only supports power-on resets... 309 */ 310 s->gretreg = value; 311 break; 312 case A_INITSVTOR0: 313 s->initsvtor0 = value; 314 set_init_vtor(0, s->initsvtor0); 315 break; 316 case A_CPUWAIT: 317 if ((s->cpuwait & 1) && !(value & 1)) { 318 /* Powering up CPU 0 */ 319 arm_set_cpu_on_and_reset(0); 320 } 321 if ((s->cpuwait & 2) && !(value & 2)) { 322 /* Powering up CPU 1 */ 323 arm_set_cpu_on_and_reset(1); 324 } 325 s->cpuwait = value; 326 break; 327 case A_WICCTRL: 328 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl WICCTRL unimplemented\n"); 329 s->wicctrl = value; 330 break; 331 case A_SECDBGSET: 332 /* write-1-to-set */ 333 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SECDBGSET unimplemented\n"); 334 s->secure_debug |= value; 335 break; 336 case A_SECDBGCLR: 337 /* write-1-to-clear */ 338 s->secure_debug &= ~value; 339 break; 340 case A_SWRESET: 341 /* One w/o bit to request a reset; all other bits reserved */ 342 if (value & R_SWRESET_SWRESETREQ_MASK) { 343 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 344 } 345 break; 346 case A_SCSECCTRL: 347 switch (s->sse_version) { 348 case ARMSSE_IOTKIT: 349 goto bad_offset; 350 case ARMSSE_SSE200: 351 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemented\n"); 352 s->scsecctrl = value; 353 break; 354 default: 355 g_assert_not_reached(); 356 } 357 break; 358 case A_FCLK_DIV: 359 switch (s->sse_version) { 360 case ARMSSE_IOTKIT: 361 goto bad_offset; 362 case ARMSSE_SSE200: 363 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented\n"); 364 s->fclk_div = value; 365 break; 366 default: 367 g_assert_not_reached(); 368 } 369 break; 370 case A_SYSCLK_DIV: 371 switch (s->sse_version) { 372 case ARMSSE_IOTKIT: 373 goto bad_offset; 374 case ARMSSE_SSE200: 375 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplemented\n"); 376 s->sysclk_div = value; 377 break; 378 default: 379 g_assert_not_reached(); 380 } 381 break; 382 case A_CLOCK_FORCE: 383 switch (s->sse_version) { 384 case ARMSSE_IOTKIT: 385 goto bad_offset; 386 case ARMSSE_SSE200: 387 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemented\n"); 388 s->clock_force = value; 389 break; 390 default: 391 g_assert_not_reached(); 392 } 393 break; 394 case A_INITSVTOR1: 395 switch (s->sse_version) { 396 case ARMSSE_IOTKIT: 397 goto bad_offset; 398 case ARMSSE_SSE200: 399 s->initsvtor1 = value; 400 set_init_vtor(1, s->initsvtor1); 401 break; 402 default: 403 g_assert_not_reached(); 404 } 405 break; 406 case A_EWCTRL: 407 switch (s->sse_version) { 408 case ARMSSE_IOTKIT: 409 goto bad_offset; 410 case ARMSSE_SSE200: 411 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl EWCTRL unimplemented\n"); 412 s->ewctrl = value; 413 break; 414 default: 415 g_assert_not_reached(); 416 } 417 break; 418 case A_PDCM_PD_SYS_SENSE: 419 switch (s->sse_version) { 420 case ARMSSE_IOTKIT: 421 goto bad_offset; 422 case ARMSSE_SSE200: 423 qemu_log_mask(LOG_UNIMP, 424 "IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n"); 425 s->pdcm_pd_sys_sense = value; 426 break; 427 default: 428 g_assert_not_reached(); 429 } 430 break; 431 case A_PDCM_PD_SRAM0_SENSE: 432 switch (s->sse_version) { 433 case ARMSSE_IOTKIT: 434 goto bad_offset; 435 case ARMSSE_SSE200: 436 qemu_log_mask(LOG_UNIMP, 437 "IoTKit SysCtl PDCM_PD_SRAM0_SENSE unimplemented\n"); 438 s->pdcm_pd_sram0_sense = value; 439 break; 440 default: 441 g_assert_not_reached(); 442 } 443 break; 444 case A_PDCM_PD_SRAM1_SENSE: 445 switch (s->sse_version) { 446 case ARMSSE_IOTKIT: 447 goto bad_offset; 448 case ARMSSE_SSE200: 449 qemu_log_mask(LOG_UNIMP, 450 "IoTKit SysCtl PDCM_PD_SRAM1_SENSE unimplemented\n"); 451 s->pdcm_pd_sram1_sense = value; 452 break; 453 default: 454 g_assert_not_reached(); 455 } 456 break; 457 case A_PDCM_PD_SRAM2_SENSE: 458 switch (s->sse_version) { 459 case ARMSSE_IOTKIT: 460 goto bad_offset; 461 case ARMSSE_SSE200: 462 qemu_log_mask(LOG_UNIMP, 463 "IoTKit SysCtl PDCM_PD_SRAM2_SENSE unimplemented\n"); 464 s->pdcm_pd_sram2_sense = value; 465 break; 466 default: 467 g_assert_not_reached(); 468 } 469 break; 470 case A_PDCM_PD_SRAM3_SENSE: 471 switch (s->sse_version) { 472 case ARMSSE_IOTKIT: 473 goto bad_offset; 474 case ARMSSE_SSE200: 475 qemu_log_mask(LOG_UNIMP, 476 "IoTKit SysCtl PDCM_PD_SRAM3_SENSE unimplemented\n"); 477 s->pdcm_pd_sram3_sense = value; 478 break; 479 default: 480 g_assert_not_reached(); 481 } 482 break; 483 case A_NMI_ENABLE: 484 /* In IoTKit this is BUSWAIT: reserved, R/O, zero */ 485 switch (s->sse_version) { 486 case ARMSSE_IOTKIT: 487 goto ro_offset; 488 case ARMSSE_SSE200: 489 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n"); 490 s->nmi_enable = value; 491 break; 492 default: 493 g_assert_not_reached(); 494 } 495 break; 496 case A_SECDBGSTAT: 497 case A_PID4 ... A_CID3: 498 ro_offset: 499 qemu_log_mask(LOG_GUEST_ERROR, 500 "IoTKit SysCtl write: write of RO offset %x\n", 501 (int)offset); 502 break; 503 default: 504 bad_offset: 505 qemu_log_mask(LOG_GUEST_ERROR, 506 "IoTKit SysCtl write: bad offset %x\n", (int)offset); 507 break; 508 } 509 } 510 511 static const MemoryRegionOps iotkit_sysctl_ops = { 512 .read = iotkit_sysctl_read, 513 .write = iotkit_sysctl_write, 514 .endianness = DEVICE_LITTLE_ENDIAN, 515 /* byte/halfword accesses are just zero-padded on reads and writes */ 516 .impl.min_access_size = 4, 517 .impl.max_access_size = 4, 518 .valid.min_access_size = 1, 519 .valid.max_access_size = 4, 520 }; 521 522 static void iotkit_sysctl_reset(DeviceState *dev) 523 { 524 IoTKitSysCtl *s = IOTKIT_SYSCTL(dev); 525 526 trace_iotkit_sysctl_reset(); 527 s->secure_debug = 0; 528 s->reset_syndrome = 1; 529 s->reset_mask = 0; 530 s->gretreg = 0; 531 s->initsvtor0 = s->initsvtor0_rst; 532 s->initsvtor1 = s->initsvtor1_rst; 533 s->cpuwait = s->cpuwait_rst; 534 s->wicctrl = 0; 535 s->scsecctrl = 0; 536 s->fclk_div = 0; 537 s->sysclk_div = 0; 538 s->clock_force = 0; 539 s->nmi_enable = 0; 540 s->ewctrl = 0; 541 s->pdcm_pd_sys_sense = 0x7f; 542 s->pdcm_pd_sram0_sense = 0; 543 s->pdcm_pd_sram1_sense = 0; 544 s->pdcm_pd_sram2_sense = 0; 545 s->pdcm_pd_sram3_sense = 0; 546 } 547 548 static void iotkit_sysctl_init(Object *obj) 549 { 550 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 551 IoTKitSysCtl *s = IOTKIT_SYSCTL(obj); 552 553 memory_region_init_io(&s->iomem, obj, &iotkit_sysctl_ops, 554 s, "iotkit-sysctl", 0x1000); 555 sysbus_init_mmio(sbd, &s->iomem); 556 } 557 558 static void iotkit_sysctl_realize(DeviceState *dev, Error **errp) 559 { 560 IoTKitSysCtl *s = IOTKIT_SYSCTL(dev); 561 562 if (!armsse_version_valid(s->sse_version)) { 563 error_setg(errp, "invalid sse-version value %d", s->sse_version); 564 return; 565 } 566 } 567 568 static bool sse200_needed(void *opaque) 569 { 570 IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque); 571 572 return s->sse_version == ARMSSE_SSE200; 573 } 574 575 static const VMStateDescription iotkit_sysctl_sse200_vmstate = { 576 .name = "iotkit-sysctl/sse-200", 577 .version_id = 1, 578 .minimum_version_id = 1, 579 .needed = sse200_needed, 580 .fields = (VMStateField[]) { 581 VMSTATE_UINT32(scsecctrl, IoTKitSysCtl), 582 VMSTATE_UINT32(fclk_div, IoTKitSysCtl), 583 VMSTATE_UINT32(sysclk_div, IoTKitSysCtl), 584 VMSTATE_UINT32(clock_force, IoTKitSysCtl), 585 VMSTATE_UINT32(initsvtor1, IoTKitSysCtl), 586 VMSTATE_UINT32(nmi_enable, IoTKitSysCtl), 587 VMSTATE_UINT32(pdcm_pd_sys_sense, IoTKitSysCtl), 588 VMSTATE_UINT32(pdcm_pd_sram0_sense, IoTKitSysCtl), 589 VMSTATE_UINT32(pdcm_pd_sram1_sense, IoTKitSysCtl), 590 VMSTATE_UINT32(pdcm_pd_sram2_sense, IoTKitSysCtl), 591 VMSTATE_UINT32(pdcm_pd_sram3_sense, IoTKitSysCtl), 592 VMSTATE_END_OF_LIST() 593 } 594 }; 595 596 static const VMStateDescription iotkit_sysctl_vmstate = { 597 .name = "iotkit-sysctl", 598 .version_id = 1, 599 .minimum_version_id = 1, 600 .fields = (VMStateField[]) { 601 VMSTATE_UINT32(secure_debug, IoTKitSysCtl), 602 VMSTATE_UINT32(reset_syndrome, IoTKitSysCtl), 603 VMSTATE_UINT32(reset_mask, IoTKitSysCtl), 604 VMSTATE_UINT32(gretreg, IoTKitSysCtl), 605 VMSTATE_UINT32(initsvtor0, IoTKitSysCtl), 606 VMSTATE_UINT32(cpuwait, IoTKitSysCtl), 607 VMSTATE_UINT32(wicctrl, IoTKitSysCtl), 608 VMSTATE_END_OF_LIST() 609 }, 610 .subsections = (const VMStateDescription*[]) { 611 &iotkit_sysctl_sse200_vmstate, 612 NULL 613 } 614 }; 615 616 static Property iotkit_sysctl_props[] = { 617 DEFINE_PROP_UINT32("sse-version", IoTKitSysCtl, sse_version, 0), 618 DEFINE_PROP_UINT32("CPUWAIT_RST", IoTKitSysCtl, cpuwait_rst, 0), 619 DEFINE_PROP_UINT32("INITSVTOR0_RST", IoTKitSysCtl, initsvtor0_rst, 620 0x10000000), 621 DEFINE_PROP_UINT32("INITSVTOR1_RST", IoTKitSysCtl, initsvtor1_rst, 622 0x10000000), 623 DEFINE_PROP_END_OF_LIST() 624 }; 625 626 static void iotkit_sysctl_class_init(ObjectClass *klass, void *data) 627 { 628 DeviceClass *dc = DEVICE_CLASS(klass); 629 630 dc->vmsd = &iotkit_sysctl_vmstate; 631 dc->reset = iotkit_sysctl_reset; 632 device_class_set_props(dc, iotkit_sysctl_props); 633 dc->realize = iotkit_sysctl_realize; 634 } 635 636 static const TypeInfo iotkit_sysctl_info = { 637 .name = TYPE_IOTKIT_SYSCTL, 638 .parent = TYPE_SYS_BUS_DEVICE, 639 .instance_size = sizeof(IoTKitSysCtl), 640 .instance_init = iotkit_sysctl_init, 641 .class_init = iotkit_sysctl_class_init, 642 }; 643 644 static void iotkit_sysctl_register_types(void) 645 { 646 type_register_static(&iotkit_sysctl_info); 647 } 648 649 type_init(iotkit_sysctl_register_types); 650