1 /* 2 * Exynos4210 Pseudo Random Nubmer Generator Emulation 3 * 4 * Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/sysbus.h" 22 #include "qapi/error.h" 23 #include "qemu/log.h" 24 #include "qemu/guest-random.h" 25 26 #define DEBUG_EXYNOS_RNG 0 27 28 #define DPRINTF(fmt, ...) \ 29 do { \ 30 if (DEBUG_EXYNOS_RNG) { \ 31 printf("exynos4210_rng: " fmt, ## __VA_ARGS__); \ 32 } \ 33 } while (0) 34 35 #define TYPE_EXYNOS4210_RNG "exynos4210.rng" 36 #define EXYNOS4210_RNG(obj) \ 37 OBJECT_CHECK(Exynos4210RngState, (obj), TYPE_EXYNOS4210_RNG) 38 39 /* 40 * Exynos4220, PRNG, only polling mode is supported. 41 */ 42 43 /* RNG_CONTROL_1 register bitfields, reset value: 0x0 */ 44 #define EXYNOS4210_RNG_CONTROL_1_PRNG 0x8 45 #define EXYNOS4210_RNG_CONTROL_1_START_INIT BIT(4) 46 /* RNG_STATUS register bitfields, reset value: 0x1 */ 47 #define EXYNOS4210_RNG_STATUS_PRNG_ERROR BIT(7) 48 #define EXYNOS4210_RNG_STATUS_PRNG_DONE BIT(5) 49 #define EXYNOS4210_RNG_STATUS_MSG_DONE BIT(4) 50 #define EXYNOS4210_RNG_STATUS_PARTIAL_DONE BIT(3) 51 #define EXYNOS4210_RNG_STATUS_PRNG_BUSY BIT(2) 52 #define EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE BIT(1) 53 #define EXYNOS4210_RNG_STATUS_BUFFER_READY BIT(0) 54 #define EXYNOS4210_RNG_STATUS_WRITE_MASK (EXYNOS4210_RNG_STATUS_PRNG_DONE \ 55 | EXYNOS4210_RNG_STATUS_MSG_DONE \ 56 | EXYNOS4210_RNG_STATUS_PARTIAL_DONE) 57 58 #define EXYNOS4210_RNG_CONTROL_1 0x0 59 #define EXYNOS4210_RNG_STATUS 0x10 60 #define EXYNOS4210_RNG_SEED_IN 0x140 61 #define EXYNOS4210_RNG_SEED_IN_OFFSET(n) (EXYNOS4210_RNG_SEED_IN + (n * 0x4)) 62 #define EXYNOS4210_RNG_PRNG 0x160 63 #define EXYNOS4210_RNG_PRNG_OFFSET(n) (EXYNOS4210_RNG_PRNG + (n * 0x4)) 64 65 #define EXYNOS4210_RNG_PRNG_NUM 5 66 67 #define EXYNOS4210_RNG_REGS_MEM_SIZE 0x200 68 69 typedef struct Exynos4210RngState { 70 SysBusDevice parent_obj; 71 MemoryRegion iomem; 72 73 int32_t randr_value[EXYNOS4210_RNG_PRNG_NUM]; 74 /* bits from 0 to EXYNOS4210_RNG_PRNG_NUM if given seed register was set */ 75 uint32_t seed_set; 76 77 /* Register values */ 78 uint32_t reg_control; 79 uint32_t reg_status; 80 } Exynos4210RngState; 81 82 static bool exynos4210_rng_seed_ready(const Exynos4210RngState *s) 83 { 84 uint32_t mask = MAKE_64BIT_MASK(0, EXYNOS4210_RNG_PRNG_NUM); 85 86 /* Return true if all the seed-set bits are set. */ 87 return (s->seed_set & mask) == mask; 88 } 89 90 static void exynos4210_rng_set_seed(Exynos4210RngState *s, unsigned int i, 91 uint64_t val) 92 { 93 /* 94 * We actually ignore the seed and always generate true random numbers. 95 * Theoretically this should not match the device as Exynos has 96 * a Pseudo Random Number Generator but testing shown that it always 97 * generates random numbers regardless of the seed value. 98 */ 99 s->seed_set |= BIT(i); 100 101 /* If all seeds were written, update the status to reflect it */ 102 if (exynos4210_rng_seed_ready(s)) { 103 s->reg_status |= EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE; 104 } else { 105 s->reg_status &= ~EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE; 106 } 107 } 108 109 static void exynos4210_rng_run_engine(Exynos4210RngState *s) 110 { 111 Error *err = NULL; 112 113 /* Seed set? */ 114 if ((s->reg_status & EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE) == 0) { 115 goto out; 116 } 117 118 /* PRNG engine chosen? */ 119 if ((s->reg_control & EXYNOS4210_RNG_CONTROL_1_PRNG) == 0) { 120 goto out; 121 } 122 123 /* PRNG engine started? */ 124 if ((s->reg_control & EXYNOS4210_RNG_CONTROL_1_START_INIT) == 0) { 125 goto out; 126 } 127 128 /* Get randoms */ 129 if (qemu_guest_getrandom(s->randr_value, sizeof(s->randr_value), &err)) { 130 error_report_err(err); 131 } else { 132 /* Notify that PRNG is ready */ 133 s->reg_status |= EXYNOS4210_RNG_STATUS_PRNG_DONE; 134 } 135 136 out: 137 /* Always clear start engine bit */ 138 s->reg_control &= ~EXYNOS4210_RNG_CONTROL_1_START_INIT; 139 } 140 141 static uint64_t exynos4210_rng_read(void *opaque, hwaddr offset, 142 unsigned size) 143 { 144 Exynos4210RngState *s = (Exynos4210RngState *)opaque; 145 uint32_t val = 0; 146 147 assert(size == 4); 148 149 switch (offset) { 150 case EXYNOS4210_RNG_CONTROL_1: 151 val = s->reg_control; 152 break; 153 154 case EXYNOS4210_RNG_STATUS: 155 val = s->reg_status; 156 break; 157 158 case EXYNOS4210_RNG_PRNG_OFFSET(0): 159 case EXYNOS4210_RNG_PRNG_OFFSET(1): 160 case EXYNOS4210_RNG_PRNG_OFFSET(2): 161 case EXYNOS4210_RNG_PRNG_OFFSET(3): 162 case EXYNOS4210_RNG_PRNG_OFFSET(4): 163 val = s->randr_value[(offset - EXYNOS4210_RNG_PRNG_OFFSET(0)) / 4]; 164 DPRINTF("returning random @0x%" HWADDR_PRIx ": 0x%" PRIx32 "\n", 165 offset, val); 166 break; 167 168 default: 169 qemu_log_mask(LOG_GUEST_ERROR, 170 "%s: bad read offset 0x%" HWADDR_PRIx "\n", 171 __func__, offset); 172 } 173 174 return val; 175 } 176 177 static void exynos4210_rng_write(void *opaque, hwaddr offset, 178 uint64_t val, unsigned size) 179 { 180 Exynos4210RngState *s = (Exynos4210RngState *)opaque; 181 182 assert(size == 4); 183 184 switch (offset) { 185 case EXYNOS4210_RNG_CONTROL_1: 186 DPRINTF("RNG_CONTROL_1 = 0x%" PRIx64 "\n", val); 187 s->reg_control = val; 188 exynos4210_rng_run_engine(s); 189 break; 190 191 case EXYNOS4210_RNG_STATUS: 192 /* For clearing status fields */ 193 s->reg_status &= ~EXYNOS4210_RNG_STATUS_WRITE_MASK; 194 s->reg_status |= val & EXYNOS4210_RNG_STATUS_WRITE_MASK; 195 break; 196 197 case EXYNOS4210_RNG_SEED_IN_OFFSET(0): 198 case EXYNOS4210_RNG_SEED_IN_OFFSET(1): 199 case EXYNOS4210_RNG_SEED_IN_OFFSET(2): 200 case EXYNOS4210_RNG_SEED_IN_OFFSET(3): 201 case EXYNOS4210_RNG_SEED_IN_OFFSET(4): 202 exynos4210_rng_set_seed(s, 203 (offset - EXYNOS4210_RNG_SEED_IN_OFFSET(0)) / 4, 204 val); 205 break; 206 207 default: 208 qemu_log_mask(LOG_GUEST_ERROR, 209 "%s: bad write offset 0x%" HWADDR_PRIx "\n", 210 __func__, offset); 211 } 212 } 213 214 static const MemoryRegionOps exynos4210_rng_ops = { 215 .read = exynos4210_rng_read, 216 .write = exynos4210_rng_write, 217 .endianness = DEVICE_NATIVE_ENDIAN, 218 }; 219 220 static void exynos4210_rng_reset(DeviceState *dev) 221 { 222 Exynos4210RngState *s = EXYNOS4210_RNG(dev); 223 224 s->reg_control = 0; 225 s->reg_status = EXYNOS4210_RNG_STATUS_BUFFER_READY; 226 memset(s->randr_value, 0, sizeof(s->randr_value)); 227 s->seed_set = 0; 228 } 229 230 static void exynos4210_rng_init(Object *obj) 231 { 232 Exynos4210RngState *s = EXYNOS4210_RNG(obj); 233 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 234 235 memory_region_init_io(&s->iomem, obj, &exynos4210_rng_ops, s, 236 TYPE_EXYNOS4210_RNG, EXYNOS4210_RNG_REGS_MEM_SIZE); 237 sysbus_init_mmio(dev, &s->iomem); 238 } 239 240 static const VMStateDescription exynos4210_rng_vmstate = { 241 .name = TYPE_EXYNOS4210_RNG, 242 .version_id = 1, 243 .minimum_version_id = 1, 244 .fields = (VMStateField[]) { 245 VMSTATE_INT32_ARRAY(randr_value, Exynos4210RngState, 246 EXYNOS4210_RNG_PRNG_NUM), 247 VMSTATE_UINT32(seed_set, Exynos4210RngState), 248 VMSTATE_UINT32(reg_status, Exynos4210RngState), 249 VMSTATE_UINT32(reg_control, Exynos4210RngState), 250 VMSTATE_END_OF_LIST() 251 } 252 }; 253 254 static void exynos4210_rng_class_init(ObjectClass *klass, void *data) 255 { 256 DeviceClass *dc = DEVICE_CLASS(klass); 257 258 dc->reset = exynos4210_rng_reset; 259 dc->vmsd = &exynos4210_rng_vmstate; 260 } 261 262 static const TypeInfo exynos4210_rng_info = { 263 .name = TYPE_EXYNOS4210_RNG, 264 .parent = TYPE_SYS_BUS_DEVICE, 265 .instance_size = sizeof(Exynos4210RngState), 266 .instance_init = exynos4210_rng_init, 267 .class_init = exynos4210_rng_class_init, 268 }; 269 270 static void exynos4210_rng_register(void) 271 { 272 type_register_static(&exynos4210_rng_info); 273 } 274 275 type_init(exynos4210_rng_register) 276