1 /* 2 * Exynos4210 Pseudo Random Nubmer Generator Emulation 3 * 4 * Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/sysbus.h" 22 #include "migration/vmstate.h" 23 #include "qapi/error.h" 24 #include "qemu/log.h" 25 #include "qemu/guest-random.h" 26 #include "qemu/module.h" 27 #include "qom/object.h" 28 29 #define DEBUG_EXYNOS_RNG 0 30 31 #define DPRINTF(fmt, ...) \ 32 do { \ 33 if (DEBUG_EXYNOS_RNG) { \ 34 printf("exynos4210_rng: " fmt, ## __VA_ARGS__); \ 35 } \ 36 } while (0) 37 38 #define TYPE_EXYNOS4210_RNG "exynos4210.rng" 39 typedef struct Exynos4210RngState Exynos4210RngState; 40 DECLARE_INSTANCE_CHECKER(Exynos4210RngState, EXYNOS4210_RNG, 41 TYPE_EXYNOS4210_RNG) 42 43 /* 44 * Exynos4220, PRNG, only polling mode is supported. 45 */ 46 47 /* RNG_CONTROL_1 register bitfields, reset value: 0x0 */ 48 #define EXYNOS4210_RNG_CONTROL_1_PRNG 0x8 49 #define EXYNOS4210_RNG_CONTROL_1_START_INIT BIT(4) 50 /* RNG_STATUS register bitfields, reset value: 0x1 */ 51 #define EXYNOS4210_RNG_STATUS_PRNG_ERROR BIT(7) 52 #define EXYNOS4210_RNG_STATUS_PRNG_DONE BIT(5) 53 #define EXYNOS4210_RNG_STATUS_MSG_DONE BIT(4) 54 #define EXYNOS4210_RNG_STATUS_PARTIAL_DONE BIT(3) 55 #define EXYNOS4210_RNG_STATUS_PRNG_BUSY BIT(2) 56 #define EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE BIT(1) 57 #define EXYNOS4210_RNG_STATUS_BUFFER_READY BIT(0) 58 #define EXYNOS4210_RNG_STATUS_WRITE_MASK (EXYNOS4210_RNG_STATUS_PRNG_DONE \ 59 | EXYNOS4210_RNG_STATUS_MSG_DONE \ 60 | EXYNOS4210_RNG_STATUS_PARTIAL_DONE) 61 62 #define EXYNOS4210_RNG_CONTROL_1 0x0 63 #define EXYNOS4210_RNG_STATUS 0x10 64 #define EXYNOS4210_RNG_SEED_IN 0x140 65 #define EXYNOS4210_RNG_SEED_IN_OFFSET(n) (EXYNOS4210_RNG_SEED_IN + (n * 0x4)) 66 #define EXYNOS4210_RNG_PRNG 0x160 67 #define EXYNOS4210_RNG_PRNG_OFFSET(n) (EXYNOS4210_RNG_PRNG + (n * 0x4)) 68 69 #define EXYNOS4210_RNG_PRNG_NUM 5 70 71 #define EXYNOS4210_RNG_REGS_MEM_SIZE 0x200 72 73 struct Exynos4210RngState { 74 SysBusDevice parent_obj; 75 MemoryRegion iomem; 76 77 int32_t randr_value[EXYNOS4210_RNG_PRNG_NUM]; 78 /* bits from 0 to EXYNOS4210_RNG_PRNG_NUM if given seed register was set */ 79 uint32_t seed_set; 80 81 /* Register values */ 82 uint32_t reg_control; 83 uint32_t reg_status; 84 }; 85 86 static bool exynos4210_rng_seed_ready(const Exynos4210RngState *s) 87 { 88 uint32_t mask = MAKE_64BIT_MASK(0, EXYNOS4210_RNG_PRNG_NUM); 89 90 /* Return true if all the seed-set bits are set. */ 91 return (s->seed_set & mask) == mask; 92 } 93 94 static void exynos4210_rng_set_seed(Exynos4210RngState *s, unsigned int i, 95 uint64_t val) 96 { 97 /* 98 * We actually ignore the seed and always generate true random numbers. 99 * Theoretically this should not match the device as Exynos has 100 * a Pseudo Random Number Generator but testing shown that it always 101 * generates random numbers regardless of the seed value. 102 */ 103 s->seed_set |= BIT(i); 104 105 /* If all seeds were written, update the status to reflect it */ 106 if (exynos4210_rng_seed_ready(s)) { 107 s->reg_status |= EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE; 108 } else { 109 s->reg_status &= ~EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE; 110 } 111 } 112 113 static void exynos4210_rng_run_engine(Exynos4210RngState *s) 114 { 115 Error *err = NULL; 116 117 /* Seed set? */ 118 if ((s->reg_status & EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE) == 0) { 119 goto out; 120 } 121 122 /* PRNG engine chosen? */ 123 if ((s->reg_control & EXYNOS4210_RNG_CONTROL_1_PRNG) == 0) { 124 goto out; 125 } 126 127 /* PRNG engine started? */ 128 if ((s->reg_control & EXYNOS4210_RNG_CONTROL_1_START_INIT) == 0) { 129 goto out; 130 } 131 132 /* Get randoms */ 133 if (qemu_guest_getrandom(s->randr_value, sizeof(s->randr_value), &err)) { 134 error_report_err(err); 135 } else { 136 /* Notify that PRNG is ready */ 137 s->reg_status |= EXYNOS4210_RNG_STATUS_PRNG_DONE; 138 } 139 140 out: 141 /* Always clear start engine bit */ 142 s->reg_control &= ~EXYNOS4210_RNG_CONTROL_1_START_INIT; 143 } 144 145 static uint64_t exynos4210_rng_read(void *opaque, hwaddr offset, 146 unsigned size) 147 { 148 Exynos4210RngState *s = (Exynos4210RngState *)opaque; 149 uint32_t val = 0; 150 151 assert(size == 4); 152 153 switch (offset) { 154 case EXYNOS4210_RNG_CONTROL_1: 155 val = s->reg_control; 156 break; 157 158 case EXYNOS4210_RNG_STATUS: 159 val = s->reg_status; 160 break; 161 162 case EXYNOS4210_RNG_PRNG_OFFSET(0): 163 case EXYNOS4210_RNG_PRNG_OFFSET(1): 164 case EXYNOS4210_RNG_PRNG_OFFSET(2): 165 case EXYNOS4210_RNG_PRNG_OFFSET(3): 166 case EXYNOS4210_RNG_PRNG_OFFSET(4): 167 val = s->randr_value[(offset - EXYNOS4210_RNG_PRNG_OFFSET(0)) / 4]; 168 DPRINTF("returning random @0x%" HWADDR_PRIx ": 0x%" PRIx32 "\n", 169 offset, val); 170 break; 171 172 default: 173 qemu_log_mask(LOG_GUEST_ERROR, 174 "%s: bad read offset 0x%" HWADDR_PRIx "\n", 175 __func__, offset); 176 } 177 178 return val; 179 } 180 181 static void exynos4210_rng_write(void *opaque, hwaddr offset, 182 uint64_t val, unsigned size) 183 { 184 Exynos4210RngState *s = (Exynos4210RngState *)opaque; 185 186 assert(size == 4); 187 188 switch (offset) { 189 case EXYNOS4210_RNG_CONTROL_1: 190 DPRINTF("RNG_CONTROL_1 = 0x%" PRIx64 "\n", val); 191 s->reg_control = val; 192 exynos4210_rng_run_engine(s); 193 break; 194 195 case EXYNOS4210_RNG_STATUS: 196 /* For clearing status fields */ 197 s->reg_status &= ~EXYNOS4210_RNG_STATUS_WRITE_MASK; 198 s->reg_status |= val & EXYNOS4210_RNG_STATUS_WRITE_MASK; 199 break; 200 201 case EXYNOS4210_RNG_SEED_IN_OFFSET(0): 202 case EXYNOS4210_RNG_SEED_IN_OFFSET(1): 203 case EXYNOS4210_RNG_SEED_IN_OFFSET(2): 204 case EXYNOS4210_RNG_SEED_IN_OFFSET(3): 205 case EXYNOS4210_RNG_SEED_IN_OFFSET(4): 206 exynos4210_rng_set_seed(s, 207 (offset - EXYNOS4210_RNG_SEED_IN_OFFSET(0)) / 4, 208 val); 209 break; 210 211 default: 212 qemu_log_mask(LOG_GUEST_ERROR, 213 "%s: bad write offset 0x%" HWADDR_PRIx "\n", 214 __func__, offset); 215 } 216 } 217 218 static const MemoryRegionOps exynos4210_rng_ops = { 219 .read = exynos4210_rng_read, 220 .write = exynos4210_rng_write, 221 .endianness = DEVICE_NATIVE_ENDIAN, 222 }; 223 224 static void exynos4210_rng_reset(DeviceState *dev) 225 { 226 Exynos4210RngState *s = EXYNOS4210_RNG(dev); 227 228 s->reg_control = 0; 229 s->reg_status = EXYNOS4210_RNG_STATUS_BUFFER_READY; 230 memset(s->randr_value, 0, sizeof(s->randr_value)); 231 s->seed_set = 0; 232 } 233 234 static void exynos4210_rng_init(Object *obj) 235 { 236 Exynos4210RngState *s = EXYNOS4210_RNG(obj); 237 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 238 239 memory_region_init_io(&s->iomem, obj, &exynos4210_rng_ops, s, 240 TYPE_EXYNOS4210_RNG, EXYNOS4210_RNG_REGS_MEM_SIZE); 241 sysbus_init_mmio(dev, &s->iomem); 242 } 243 244 static const VMStateDescription exynos4210_rng_vmstate = { 245 .name = TYPE_EXYNOS4210_RNG, 246 .version_id = 1, 247 .minimum_version_id = 1, 248 .fields = (VMStateField[]) { 249 VMSTATE_INT32_ARRAY(randr_value, Exynos4210RngState, 250 EXYNOS4210_RNG_PRNG_NUM), 251 VMSTATE_UINT32(seed_set, Exynos4210RngState), 252 VMSTATE_UINT32(reg_status, Exynos4210RngState), 253 VMSTATE_UINT32(reg_control, Exynos4210RngState), 254 VMSTATE_END_OF_LIST() 255 } 256 }; 257 258 static void exynos4210_rng_class_init(ObjectClass *klass, void *data) 259 { 260 DeviceClass *dc = DEVICE_CLASS(klass); 261 262 dc->reset = exynos4210_rng_reset; 263 dc->vmsd = &exynos4210_rng_vmstate; 264 } 265 266 static const TypeInfo exynos4210_rng_info = { 267 .name = TYPE_EXYNOS4210_RNG, 268 .parent = TYPE_SYS_BUS_DEVICE, 269 .instance_size = sizeof(Exynos4210RngState), 270 .instance_init = exynos4210_rng_init, 271 .class_init = exynos4210_rng_class_init, 272 }; 273 274 static void exynos4210_rng_register(void) 275 { 276 type_register_static(&exynos4210_rng_info); 277 } 278 279 type_init(exynos4210_rng_register) 280