xref: /openbmc/qemu/hw/misc/exynos4210_pmu.c (revision 9d49b1c9edf829e571093088ddff0b73db3110c6)
1  /*
2   *  Exynos4210 Power Management Unit (PMU) Emulation
3   *
4   *  Copyright (C) 2011 Samsung Electronics Co Ltd.
5   *    Maksim Kozlov <m.kozlov@samsung.com>
6   *
7   *  This program is free software; you can redistribute it and/or modify it
8   *  under the terms of the GNU General Public License as published by the
9   *  Free Software Foundation; either version 2 of the License, or
10   *  (at your option) any later version.
11   *
12   *  This program is distributed in the hope that it will be useful, but WITHOUT
13   *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14   *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15   *  for more details.
16   *
17   *  You should have received a copy of the GNU General Public License along
18   *  with this program; if not, see <http://www.gnu.org/licenses/>.
19   */
20  
21  /*
22   * This model implements PMU registers just as a bulk of memory. Currently,
23   * the only reason this device exists is that secondary CPU boot loader
24   * uses PMU INFORM5 register as a holding pen.
25   */
26  
27  #include "qemu/osdep.h"
28  #include "hw/sysbus.h"
29  #include "migration/vmstate.h"
30  #include "qemu/module.h"
31  #include "sysemu/runstate.h"
32  #include "qom/object.h"
33  
34  #ifndef DEBUG_PMU
35  #define DEBUG_PMU           0
36  #endif
37  
38  #ifndef DEBUG_PMU_EXTEND
39  #define DEBUG_PMU_EXTEND    0
40  #endif
41  
42  #if DEBUG_PMU
43  #define  PRINT_DEBUG(fmt, args...)  \
44          do { \
45              fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
46          } while (0)
47  
48  #if DEBUG_PMU_EXTEND
49  #define  PRINT_DEBUG_EXTEND(fmt, args...) \
50          do { \
51              fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
52          } while (0)
53  #else
54  #define  PRINT_DEBUG_EXTEND(fmt, args...)  do {} while (0)
55  #endif /* EXTEND */
56  
57  #else
58  #define  PRINT_DEBUG(fmt, args...)   do {} while (0)
59  #define  PRINT_DEBUG_EXTEND(fmt, args...)  do {} while (0)
60  #endif
61  
62  /*
63   *  Offsets for PMU registers
64   */
65  #define OM_STAT                  0x0000 /* OM status register */
66  #define RTC_CLKO_SEL             0x000C /* Controls RTCCLKOUT */
67  #define GNSS_RTC_OUT_CTRL        0x0010 /* Controls GNSS_RTC_OUT */
68  /* Decides whether system-level low-power mode is used. */
69  #define SYSTEM_POWER_DOWN_CTRL   0x0200
70  /* Sets control options for CENTRAL_SEQ */
71  #define SYSTEM_POWER_DOWN_OPTION 0x0208
72  #define SWRESET                  0x0400 /* Generate software reset */
73  #define RST_STAT                 0x0404 /* Reset status register */
74  #define WAKEUP_STAT              0x0600 /* Wakeup status register  */
75  #define EINT_WAKEUP_MASK         0x0604 /* Configure External INTerrupt mask */
76  #define WAKEUP_MASK              0x0608 /* Configure wakeup source mask */
77  #define HDMI_PHY_CONTROL         0x0700 /* HDMI PHY control register */
78  #define USBDEVICE_PHY_CONTROL    0x0704 /* USB Device PHY control register */
79  #define USBHOST_PHY_CONTROL      0x0708 /* USB HOST PHY control register */
80  #define DAC_PHY_CONTROL          0x070C /* DAC control register  */
81  #define MIPI_PHY0_CONTROL        0x0710 /* MIPI PHY control register */
82  #define MIPI_PHY1_CONTROL        0x0714 /* MIPI PHY control register */
83  #define ADC_PHY_CONTROL          0x0718 /* TS-ADC control register */
84  #define PCIe_PHY_CONTROL         0x071C /* TS-PCIe control register */
85  #define SATA_PHY_CONTROL         0x0720 /* TS-SATA control register */
86  #define INFORM0                  0x0800 /* Information register 0  */
87  #define INFORM1                  0x0804 /* Information register 1  */
88  #define INFORM2                  0x0808 /* Information register 2  */
89  #define INFORM3                  0x080C /* Information register 3  */
90  #define INFORM4                  0x0810 /* Information register 4  */
91  #define INFORM5                  0x0814 /* Information register 5  */
92  #define INFORM6                  0x0818 /* Information register 6  */
93  #define INFORM7                  0x081C /* Information register 7  */
94  #define PMU_DEBUG                0x0A00 /* PMU debug register */
95  /* Registers to set system-level low-power option */
96  #define ARM_CORE0_SYS_PWR_REG              0x1000
97  #define ARM_CORE1_SYS_PWR_REG              0x1010
98  #define ARM_COMMON_SYS_PWR_REG             0x1080
99  #define ARM_CPU_L2_0_SYS_PWR_REG           0x10C0
100  #define ARM_CPU_L2_1_SYS_PWR_REG           0x10C4
101  #define CMU_ACLKSTOP_SYS_PWR_REG           0x1100
102  #define CMU_SCLKSTOP_SYS_PWR_REG           0x1104
103  #define CMU_RESET_SYS_PWR_REG              0x110C
104  #define APLL_SYSCLK_SYS_PWR_REG            0x1120
105  #define MPLL_SYSCLK_SYS_PWR_REG            0x1124
106  #define VPLL_SYSCLK_SYS_PWR_REG            0x1128
107  #define EPLL_SYSCLK_SYS_PWR_REG            0x112C
108  #define CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG  0x1138
109  #define CMU_RESET_GPS_ALIVE_SYS_PWR_REG    0x113C
110  #define CMU_CLKSTOP_CAM_SYS_PWR_REG        0x1140
111  #define CMU_CLKSTOP_TV_SYS_PWR_REG         0x1144
112  #define CMU_CLKSTOP_MFC_SYS_PWR_REG        0x1148
113  #define CMU_CLKSTOP_G3D_SYS_PWR_REG        0x114C
114  #define CMU_CLKSTOP_LCD0_SYS_PWR_REG       0x1150
115  #define CMU_CLKSTOP_LCD1_SYS_PWR_REG       0x1154
116  #define CMU_CLKSTOP_MAUDIO_SYS_PWR_REG     0x1158
117  #define CMU_CLKSTOP_GPS_SYS_PWR_REG        0x115C
118  #define CMU_RESET_CAM_SYS_PWR_REG          0x1160
119  #define CMU_RESET_TV_SYS_PWR_REG           0x1164
120  #define CMU_RESET_MFC_SYS_PWR_REG          0x1168
121  #define CMU_RESET_G3D_SYS_PWR_REG          0x116C
122  #define CMU_RESET_LCD0_SYS_PWR_REG         0x1170
123  #define CMU_RESET_LCD1_SYS_PWR_REG         0x1174
124  #define CMU_RESET_MAUDIO_SYS_PWR_REG       0x1178
125  #define CMU_RESET_GPS_SYS_PWR_REG          0x117C
126  #define TOP_BUS_SYS_PWR_REG                0x1180
127  #define TOP_RETENTION_SYS_PWR_REG          0x1184
128  #define TOP_PWR_SYS_PWR_REG                0x1188
129  #define LOGIC_RESET_SYS_PWR_REG            0x11A0
130  #define OneNANDXL_MEM_SYS_PWR_REG          0x11C0
131  #define MODEMIF_MEM_SYS_PWR_REG            0x11C4
132  #define USBDEVICE_MEM_SYS_PWR_REG          0x11CC
133  #define SDMMC_MEM_SYS_PWR_REG              0x11D0
134  #define CSSYS_MEM_SYS_PWR_REG              0x11D4
135  #define SECSS_MEM_SYS_PWR_REG              0x11D8
136  #define PCIe_MEM_SYS_PWR_REG               0x11E0
137  #define SATA_MEM_SYS_PWR_REG               0x11E4
138  #define PAD_RETENTION_DRAM_SYS_PWR_REG     0x1200
139  #define PAD_RETENTION_MAUDIO_SYS_PWR_REG   0x1204
140  #define PAD_RETENTION_GPIO_SYS_PWR_REG     0x1220
141  #define PAD_RETENTION_UART_SYS_PWR_REG     0x1224
142  #define PAD_RETENTION_MMCA_SYS_PWR_REG     0x1228
143  #define PAD_RETENTION_MMCB_SYS_PWR_REG     0x122C
144  #define PAD_RETENTION_EBIA_SYS_PWR_REG     0x1230
145  #define PAD_RETENTION_EBIB_SYS_PWR_REG     0x1234
146  #define PAD_ISOLATION_SYS_PWR_REG          0x1240
147  #define PAD_ALV_SEL_SYS_PWR_REG            0x1260
148  #define XUSBXTI_SYS_PWR_REG                0x1280
149  #define XXTI_SYS_PWR_REG                   0x1284
150  #define EXT_REGULATOR_SYS_PWR_REG          0x12C0
151  #define GPIO_MODE_SYS_PWR_REG              0x1300
152  #define GPIO_MODE_MAUDIO_SYS_PWR_REG       0x1340
153  #define CAM_SYS_PWR_REG                    0x1380
154  #define TV_SYS_PWR_REG                     0x1384
155  #define MFC_SYS_PWR_REG                    0x1388
156  #define G3D_SYS_PWR_REG                    0x138C
157  #define LCD0_SYS_PWR_REG                   0x1390
158  #define LCD1_SYS_PWR_REG                   0x1394
159  #define MAUDIO_SYS_PWR_REG                 0x1398
160  #define GPS_SYS_PWR_REG                    0x139C
161  #define GPS_ALIVE_SYS_PWR_REG              0x13A0
162  #define ARM_CORE0_CONFIGURATION 0x2000 /* Configure power mode of ARM_CORE0 */
163  #define ARM_CORE0_STATUS        0x2004 /* Check power mode of ARM_CORE0 */
164  #define ARM_CORE0_OPTION        0x2008 /* Sets control options for ARM_CORE0 */
165  #define ARM_CORE1_CONFIGURATION 0x2080 /* Configure power mode of ARM_CORE1 */
166  #define ARM_CORE1_STATUS        0x2084 /* Check power mode of ARM_CORE1 */
167  #define ARM_CORE1_OPTION        0x2088 /* Sets control options for ARM_CORE0 */
168  #define ARM_COMMON_OPTION       0x2408 /* Sets control options for ARM_COMMON */
169  /* Configure power mode of ARM_CPU_L2_0 */
170  #define ARM_CPU_L2_0_CONFIGURATION 0x2600
171  #define ARM_CPU_L2_0_STATUS        0x2604 /* Check power mode of ARM_CPU_L2_0 */
172  /* Configure power mode of ARM_CPU_L2_1 */
173  #define ARM_CPU_L2_1_CONFIGURATION 0x2620
174  #define ARM_CPU_L2_1_STATUS        0x2624 /* Check power mode of ARM_CPU_L2_1 */
175  /* Sets control options for PAD_RETENTION_MAUDIO */
176  #define PAD_RETENTION_MAUDIO_OPTION 0x3028
177  /* Sets control options for PAD_RETENTION_GPIO */
178  #define PAD_RETENTION_GPIO_OPTION   0x3108
179  /* Sets control options for PAD_RETENTION_UART */
180  #define PAD_RETENTION_UART_OPTION   0x3128
181  /* Sets control options for PAD_RETENTION_MMCA */
182  #define PAD_RETENTION_MMCA_OPTION   0x3148
183  /* Sets control options for PAD_RETENTION_MMCB */
184  #define PAD_RETENTION_MMCB_OPTION   0x3168
185  /* Sets control options for PAD_RETENTION_EBIA */
186  #define PAD_RETENTION_EBIA_OPTION   0x3188
187  /* Sets control options for PAD_RETENTION_EBIB */
188  #define PAD_RETENTION_EBIB_OPTION   0x31A8
189  #define PS_HOLD_CONTROL         0x330C /* PS_HOLD control register */
190  #define XUSBXTI_CONFIGURATION   0x3400 /* Configure the pad of XUSBXTI */
191  #define XUSBXTI_STATUS          0x3404 /* Check the pad of XUSBXTI */
192  /* Sets time required for XUSBXTI to be stabilized */
193  #define XUSBXTI_DURATION        0x341C
194  #define XXTI_CONFIGURATION      0x3420 /* Configure the pad of XXTI */
195  #define XXTI_STATUS             0x3424 /* Check the pad of XXTI */
196  /* Sets time required for XXTI to be stabilized */
197  #define XXTI_DURATION           0x343C
198  /* Sets time required for EXT_REGULATOR to be stabilized */
199  #define EXT_REGULATOR_DURATION  0x361C
200  #define CAM_CONFIGURATION       0x3C00 /* Configure power mode of CAM */
201  #define CAM_STATUS              0x3C04 /* Check power mode of CAM */
202  #define CAM_OPTION              0x3C08 /* Sets control options for CAM */
203  #define TV_CONFIGURATION        0x3C20 /* Configure power mode of TV */
204  #define TV_STATUS               0x3C24 /* Check power mode of TV */
205  #define TV_OPTION               0x3C28 /* Sets control options for TV */
206  #define MFC_CONFIGURATION       0x3C40 /* Configure power mode of MFC */
207  #define MFC_STATUS              0x3C44 /* Check power mode of MFC */
208  #define MFC_OPTION              0x3C48 /* Sets control options for MFC */
209  #define G3D_CONFIGURATION       0x3C60 /* Configure power mode of G3D */
210  #define G3D_STATUS              0x3C64 /* Check power mode of G3D */
211  #define G3D_OPTION              0x3C68 /* Sets control options for G3D */
212  #define LCD0_CONFIGURATION      0x3C80 /* Configure power mode of LCD0 */
213  #define LCD0_STATUS             0x3C84 /* Check power mode of LCD0 */
214  #define LCD0_OPTION             0x3C88 /* Sets control options for LCD0 */
215  #define LCD1_CONFIGURATION      0x3CA0 /* Configure power mode of LCD1 */
216  #define LCD1_STATUS             0x3CA4 /* Check power mode of LCD1 */
217  #define LCD1_OPTION             0x3CA8 /* Sets control options for LCD1 */
218  #define GPS_CONFIGURATION       0x3CE0 /* Configure power mode of GPS */
219  #define GPS_STATUS              0x3CE4 /* Check power mode of GPS */
220  #define GPS_OPTION              0x3CE8 /* Sets control options for GPS */
221  #define GPS_ALIVE_CONFIGURATION 0x3D00 /* Configure power mode of GPS */
222  #define GPS_ALIVE_STATUS        0x3D04 /* Check power mode of GPS */
223  #define GPS_ALIVE_OPTION        0x3D08 /* Sets control options for GPS */
224  
225  #define EXYNOS4210_PMU_REGS_MEM_SIZE 0x3d0c
226  
227  typedef struct Exynos4210PmuReg {
228      const char  *name; /* for debug only */
229      uint32_t     offset;
230      uint32_t     reset_value;
231  } Exynos4210PmuReg;
232  
233  static const Exynos4210PmuReg exynos4210_pmu_regs[] = {
234      {"OM_STAT", OM_STAT, 0x00000000},
235      {"RTC_CLKO_SEL", RTC_CLKO_SEL, 0x00000000},
236      {"GNSS_RTC_OUT_CTRL", GNSS_RTC_OUT_CTRL, 0x00000001},
237      {"SYSTEM_POWER_DOWN_CTRL", SYSTEM_POWER_DOWN_CTRL, 0x00010000},
238      {"SYSTEM_POWER_DOWN_OPTION", SYSTEM_POWER_DOWN_OPTION, 0x03030000},
239      {"SWRESET", SWRESET, 0x00000000},
240      {"RST_STAT", RST_STAT, 0x00000000},
241      {"WAKEUP_STAT", WAKEUP_STAT, 0x00000000},
242      {"EINT_WAKEUP_MASK", EINT_WAKEUP_MASK, 0x00000000},
243      {"WAKEUP_MASK", WAKEUP_MASK, 0x00000000},
244      {"HDMI_PHY_CONTROL", HDMI_PHY_CONTROL, 0x00960000},
245      {"USBDEVICE_PHY_CONTROL", USBDEVICE_PHY_CONTROL, 0x00000000},
246      {"USBHOST_PHY_CONTROL", USBHOST_PHY_CONTROL, 0x00000000},
247      {"DAC_PHY_CONTROL", DAC_PHY_CONTROL, 0x00000000},
248      {"MIPI_PHY0_CONTROL", MIPI_PHY0_CONTROL, 0x00000000},
249      {"MIPI_PHY1_CONTROL", MIPI_PHY1_CONTROL, 0x00000000},
250      {"ADC_PHY_CONTROL", ADC_PHY_CONTROL, 0x00000001},
251      {"PCIe_PHY_CONTROL", PCIe_PHY_CONTROL, 0x00000000},
252      {"SATA_PHY_CONTROL", SATA_PHY_CONTROL, 0x00000000},
253      {"INFORM0", INFORM0, 0x00000000},
254      {"INFORM1", INFORM1, 0x00000000},
255      {"INFORM2", INFORM2, 0x00000000},
256      {"INFORM3", INFORM3, 0x00000000},
257      {"INFORM4", INFORM4, 0x00000000},
258      {"INFORM5", INFORM5, 0x00000000},
259      {"INFORM6", INFORM6, 0x00000000},
260      {"INFORM7", INFORM7, 0x00000000},
261      {"PMU_DEBUG", PMU_DEBUG, 0x00000000},
262      {"ARM_CORE0_SYS_PWR_REG", ARM_CORE0_SYS_PWR_REG, 0xFFFFFFFF},
263      {"ARM_CORE1_SYS_PWR_REG", ARM_CORE1_SYS_PWR_REG, 0xFFFFFFFF},
264      {"ARM_COMMON_SYS_PWR_REG", ARM_COMMON_SYS_PWR_REG, 0xFFFFFFFF},
265      {"ARM_CPU_L2_0_SYS_PWR_REG", ARM_CPU_L2_0_SYS_PWR_REG, 0xFFFFFFFF},
266      {"ARM_CPU_L2_1_SYS_PWR_REG", ARM_CPU_L2_1_SYS_PWR_REG, 0xFFFFFFFF},
267      {"CMU_ACLKSTOP_SYS_PWR_REG", CMU_ACLKSTOP_SYS_PWR_REG, 0xFFFFFFFF},
268      {"CMU_SCLKSTOP_SYS_PWR_REG", CMU_SCLKSTOP_SYS_PWR_REG, 0xFFFFFFFF},
269      {"CMU_RESET_SYS_PWR_REG", CMU_RESET_SYS_PWR_REG, 0xFFFFFFFF},
270      {"APLL_SYSCLK_SYS_PWR_REG", APLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF},
271      {"MPLL_SYSCLK_SYS_PWR_REG", MPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF},
272      {"VPLL_SYSCLK_SYS_PWR_REG", VPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF},
273      {"EPLL_SYSCLK_SYS_PWR_REG", EPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF},
274      {"CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG", CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG,
275              0xFFFFFFFF},
276      {"CMU_RESET_GPS_ALIVE_SYS_PWR_REG", CMU_RESET_GPS_ALIVE_SYS_PWR_REG,
277              0xFFFFFFFF},
278      {"CMU_CLKSTOP_CAM_SYS_PWR_REG", CMU_CLKSTOP_CAM_SYS_PWR_REG, 0xFFFFFFFF},
279      {"CMU_CLKSTOP_TV_SYS_PWR_REG", CMU_CLKSTOP_TV_SYS_PWR_REG, 0xFFFFFFFF},
280      {"CMU_CLKSTOP_MFC_SYS_PWR_REG", CMU_CLKSTOP_MFC_SYS_PWR_REG, 0xFFFFFFFF},
281      {"CMU_CLKSTOP_G3D_SYS_PWR_REG", CMU_CLKSTOP_G3D_SYS_PWR_REG, 0xFFFFFFFF},
282      {"CMU_CLKSTOP_LCD0_SYS_PWR_REG", CMU_CLKSTOP_LCD0_SYS_PWR_REG, 0xFFFFFFFF},
283      {"CMU_CLKSTOP_LCD1_SYS_PWR_REG", CMU_CLKSTOP_LCD1_SYS_PWR_REG, 0xFFFFFFFF},
284      {"CMU_CLKSTOP_MAUDIO_SYS_PWR_REG", CMU_CLKSTOP_MAUDIO_SYS_PWR_REG,
285              0xFFFFFFFF},
286      {"CMU_CLKSTOP_GPS_SYS_PWR_REG", CMU_CLKSTOP_GPS_SYS_PWR_REG, 0xFFFFFFFF},
287      {"CMU_RESET_CAM_SYS_PWR_REG", CMU_RESET_CAM_SYS_PWR_REG, 0xFFFFFFFF},
288      {"CMU_RESET_TV_SYS_PWR_REG", CMU_RESET_TV_SYS_PWR_REG, 0xFFFFFFFF},
289      {"CMU_RESET_MFC_SYS_PWR_REG", CMU_RESET_MFC_SYS_PWR_REG, 0xFFFFFFFF},
290      {"CMU_RESET_G3D_SYS_PWR_REG", CMU_RESET_G3D_SYS_PWR_REG, 0xFFFFFFFF},
291      {"CMU_RESET_LCD0_SYS_PWR_REG", CMU_RESET_LCD0_SYS_PWR_REG, 0xFFFFFFFF},
292      {"CMU_RESET_LCD1_SYS_PWR_REG", CMU_RESET_LCD1_SYS_PWR_REG, 0xFFFFFFFF},
293      {"CMU_RESET_MAUDIO_SYS_PWR_REG", CMU_RESET_MAUDIO_SYS_PWR_REG, 0xFFFFFFFF},
294      {"CMU_RESET_GPS_SYS_PWR_REG", CMU_RESET_GPS_SYS_PWR_REG, 0xFFFFFFFF},
295      {"TOP_BUS_SYS_PWR_REG", TOP_BUS_SYS_PWR_REG, 0xFFFFFFFF},
296      {"TOP_RETENTION_SYS_PWR_REG", TOP_RETENTION_SYS_PWR_REG, 0xFFFFFFFF},
297      {"TOP_PWR_SYS_PWR_REG", TOP_PWR_SYS_PWR_REG, 0xFFFFFFFF},
298      {"LOGIC_RESET_SYS_PWR_REG", LOGIC_RESET_SYS_PWR_REG, 0xFFFFFFFF},
299      {"OneNANDXL_MEM_SYS_PWR_REG", OneNANDXL_MEM_SYS_PWR_REG, 0xFFFFFFFF},
300      {"MODEMIF_MEM_SYS_PWR_REG", MODEMIF_MEM_SYS_PWR_REG, 0xFFFFFFFF},
301      {"USBDEVICE_MEM_SYS_PWR_REG", USBDEVICE_MEM_SYS_PWR_REG, 0xFFFFFFFF},
302      {"SDMMC_MEM_SYS_PWR_REG", SDMMC_MEM_SYS_PWR_REG, 0xFFFFFFFF},
303      {"CSSYS_MEM_SYS_PWR_REG", CSSYS_MEM_SYS_PWR_REG, 0xFFFFFFFF},
304      {"SECSS_MEM_SYS_PWR_REG", SECSS_MEM_SYS_PWR_REG, 0xFFFFFFFF},
305      {"PCIe_MEM_SYS_PWR_REG", PCIe_MEM_SYS_PWR_REG, 0xFFFFFFFF},
306      {"SATA_MEM_SYS_PWR_REG", SATA_MEM_SYS_PWR_REG, 0xFFFFFFFF},
307      {"PAD_RETENTION_DRAM_SYS_PWR_REG", PAD_RETENTION_DRAM_SYS_PWR_REG,
308              0xFFFFFFFF},
309      {"PAD_RETENTION_MAUDIO_SYS_PWR_REG", PAD_RETENTION_MAUDIO_SYS_PWR_REG,
310              0xFFFFFFFF},
311      {"PAD_RETENTION_GPIO_SYS_PWR_REG", PAD_RETENTION_GPIO_SYS_PWR_REG,
312              0xFFFFFFFF},
313      {"PAD_RETENTION_UART_SYS_PWR_REG", PAD_RETENTION_UART_SYS_PWR_REG,
314              0xFFFFFFFF},
315      {"PAD_RETENTION_MMCA_SYS_PWR_REG", PAD_RETENTION_MMCA_SYS_PWR_REG,
316              0xFFFFFFFF},
317      {"PAD_RETENTION_MMCB_SYS_PWR_REG", PAD_RETENTION_MMCB_SYS_PWR_REG,
318              0xFFFFFFFF},
319      {"PAD_RETENTION_EBIA_SYS_PWR_REG", PAD_RETENTION_EBIA_SYS_PWR_REG,
320              0xFFFFFFFF},
321      {"PAD_RETENTION_EBIB_SYS_PWR_REG", PAD_RETENTION_EBIB_SYS_PWR_REG,
322              0xFFFFFFFF},
323      {"PAD_ISOLATION_SYS_PWR_REG", PAD_ISOLATION_SYS_PWR_REG, 0xFFFFFFFF},
324      {"PAD_ALV_SEL_SYS_PWR_REG", PAD_ALV_SEL_SYS_PWR_REG, 0xFFFFFFFF},
325      {"XUSBXTI_SYS_PWR_REG", XUSBXTI_SYS_PWR_REG, 0xFFFFFFFF},
326      {"XXTI_SYS_PWR_REG", XXTI_SYS_PWR_REG, 0xFFFFFFFF},
327      {"EXT_REGULATOR_SYS_PWR_REG", EXT_REGULATOR_SYS_PWR_REG, 0xFFFFFFFF},
328      {"GPIO_MODE_SYS_PWR_REG", GPIO_MODE_SYS_PWR_REG, 0xFFFFFFFF},
329      {"GPIO_MODE_MAUDIO_SYS_PWR_REG", GPIO_MODE_MAUDIO_SYS_PWR_REG, 0xFFFFFFFF},
330      {"CAM_SYS_PWR_REG", CAM_SYS_PWR_REG, 0xFFFFFFFF},
331      {"TV_SYS_PWR_REG", TV_SYS_PWR_REG, 0xFFFFFFFF},
332      {"MFC_SYS_PWR_REG", MFC_SYS_PWR_REG, 0xFFFFFFFF},
333      {"G3D_SYS_PWR_REG", G3D_SYS_PWR_REG, 0xFFFFFFFF},
334      {"LCD0_SYS_PWR_REG", LCD0_SYS_PWR_REG, 0xFFFFFFFF},
335      {"LCD1_SYS_PWR_REG", LCD1_SYS_PWR_REG, 0xFFFFFFFF},
336      {"MAUDIO_SYS_PWR_REG", MAUDIO_SYS_PWR_REG, 0xFFFFFFFF},
337      {"GPS_SYS_PWR_REG", GPS_SYS_PWR_REG, 0xFFFFFFFF},
338      {"GPS_ALIVE_SYS_PWR_REG", GPS_ALIVE_SYS_PWR_REG, 0xFFFFFFFF},
339      {"ARM_CORE0_CONFIGURATION", ARM_CORE0_CONFIGURATION, 0x00000003},
340      {"ARM_CORE0_STATUS", ARM_CORE0_STATUS, 0x00030003},
341      {"ARM_CORE0_OPTION", ARM_CORE0_OPTION, 0x01010001},
342      {"ARM_CORE1_CONFIGURATION", ARM_CORE1_CONFIGURATION, 0x00000003},
343      {"ARM_CORE1_STATUS", ARM_CORE1_STATUS, 0x00030003},
344      {"ARM_CORE1_OPTION", ARM_CORE1_OPTION, 0x01010001},
345      {"ARM_COMMON_OPTION", ARM_COMMON_OPTION, 0x00000001},
346      {"ARM_CPU_L2_0_CONFIGURATION", ARM_CPU_L2_0_CONFIGURATION, 0x00000003},
347      {"ARM_CPU_L2_0_STATUS", ARM_CPU_L2_0_STATUS, 0x00000003},
348      {"ARM_CPU_L2_1_CONFIGURATION", ARM_CPU_L2_1_CONFIGURATION, 0x00000003},
349      {"ARM_CPU_L2_1_STATUS", ARM_CPU_L2_1_STATUS, 0x00000003},
350      {"PAD_RETENTION_MAUDIO_OPTION", PAD_RETENTION_MAUDIO_OPTION, 0x00000000},
351      {"PAD_RETENTION_GPIO_OPTION", PAD_RETENTION_GPIO_OPTION, 0x00000000},
352      {"PAD_RETENTION_UART_OPTION", PAD_RETENTION_UART_OPTION, 0x00000000},
353      {"PAD_RETENTION_MMCA_OPTION", PAD_RETENTION_MMCA_OPTION, 0x00000000},
354      {"PAD_RETENTION_MMCB_OPTION", PAD_RETENTION_MMCB_OPTION, 0x00000000},
355      {"PAD_RETENTION_EBIA_OPTION", PAD_RETENTION_EBIA_OPTION, 0x00000000},
356      {"PAD_RETENTION_EBIB_OPTION", PAD_RETENTION_EBIB_OPTION, 0x00000000},
357      /*
358       * PS_HOLD_CONTROL: reset value and manually toggle high the DATA bit.
359       * DATA bit high, set usually by bootloader, keeps system on.
360       */
361      {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200 | BIT(8)},
362      {"XUSBXTI_CONFIGURATION", XUSBXTI_CONFIGURATION, 0x00000001},
363      {"XUSBXTI_STATUS", XUSBXTI_STATUS, 0x00000001},
364      {"XUSBXTI_DURATION", XUSBXTI_DURATION, 0xFFF00000},
365      {"XXTI_CONFIGURATION", XXTI_CONFIGURATION, 0x00000001},
366      {"XXTI_STATUS", XXTI_STATUS, 0x00000001},
367      {"XXTI_DURATION", XXTI_DURATION, 0xFFF00000},
368      {"EXT_REGULATOR_DURATION", EXT_REGULATOR_DURATION, 0xFFF03FFF},
369      {"CAM_CONFIGURATION", CAM_CONFIGURATION, 0x00000007},
370      {"CAM_STATUS", CAM_STATUS, 0x00060007},
371      {"CAM_OPTION", CAM_OPTION, 0x00000001},
372      {"TV_CONFIGURATION", TV_CONFIGURATION, 0x00000007},
373      {"TV_STATUS", TV_STATUS, 0x00060007},
374      {"TV_OPTION", TV_OPTION, 0x00000001},
375      {"MFC_CONFIGURATION", MFC_CONFIGURATION, 0x00000007},
376      {"MFC_STATUS", MFC_STATUS, 0x00060007},
377      {"MFC_OPTION", MFC_OPTION, 0x00000001},
378      {"G3D_CONFIGURATION", G3D_CONFIGURATION, 0x00000007},
379      {"G3D_STATUS", G3D_STATUS, 0x00060007},
380      {"G3D_OPTION", G3D_OPTION, 0x00000001},
381      {"LCD0_CONFIGURATION", LCD0_CONFIGURATION, 0x00000007},
382      {"LCD0_STATUS", LCD0_STATUS, 0x00060007},
383      {"LCD0_OPTION", LCD0_OPTION, 0x00000001},
384      {"LCD1_CONFIGURATION", LCD1_CONFIGURATION, 0x00000007},
385      {"LCD1_STATUS", LCD1_STATUS, 0x00060007},
386      {"LCD1_OPTION", LCD1_OPTION, 0x00000001},
387      {"GPS_CONFIGURATION", GPS_CONFIGURATION, 0x00000007},
388      {"GPS_STATUS", GPS_STATUS, 0x00060007},
389      {"GPS_OPTION", GPS_OPTION, 0x00000001},
390      {"GPS_ALIVE_CONFIGURATION", GPS_ALIVE_CONFIGURATION, 0x00000007},
391      {"GPS_ALIVE_STATUS", GPS_ALIVE_STATUS, 0x00060007},
392      {"GPS_ALIVE_OPTION", GPS_ALIVE_OPTION, 0x00000001},
393  };
394  
395  #define PMU_NUM_OF_REGISTERS ARRAY_SIZE(exynos4210_pmu_regs)
396  
397  #define TYPE_EXYNOS4210_PMU "exynos4210.pmu"
398  OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210PmuState, EXYNOS4210_PMU)
399  
400  struct Exynos4210PmuState {
401      SysBusDevice parent_obj;
402  
403      MemoryRegion iomem;
404      uint32_t reg[PMU_NUM_OF_REGISTERS];
405  };
406  
407  static void exynos4210_pmu_poweroff(void)
408  {
409      PRINT_DEBUG("QEMU PMU: PS_HOLD bit down, powering off\n");
410      qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
411  }
412  
413  static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset,
414                                      unsigned size)
415  {
416      Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
417      const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
418      unsigned int i;
419  
420      for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
421          if (reg_p->offset == offset) {
422              PRINT_DEBUG_EXTEND("%s [0x%04x] -> 0x%04x\n", reg_p->name,
423                                     (uint32_t)offset, s->reg[i]);
424              return s->reg[i];
425          }
426          reg_p++;
427      }
428      PRINT_DEBUG("QEMU PMU ERROR: bad read offset 0x%04x\n", (uint32_t)offset);
429      return 0;
430  }
431  
432  static void exynos4210_pmu_write(void *opaque, hwaddr offset,
433                                   uint64_t val, unsigned size)
434  {
435      Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
436      const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
437      unsigned int i;
438  
439      for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
440          if (reg_p->offset == offset) {
441              PRINT_DEBUG_EXTEND("%s <0x%04x> <- 0x%04x\n", reg_p->name,
442                      (uint32_t)offset, (uint32_t)val);
443              s->reg[i] = val;
444              if ((offset == PS_HOLD_CONTROL) && ((val & BIT(8)) == 0)) {
445                  /*
446                   * We are interested only in setting data bit
447                   * of PS_HOLD_CONTROL register to indicate power off request.
448                   */
449                  exynos4210_pmu_poweroff();
450              }
451              return;
452          }
453          reg_p++;
454      }
455      PRINT_DEBUG("QEMU PMU ERROR: bad write offset 0x%04x\n", (uint32_t)offset);
456  }
457  
458  static const MemoryRegionOps exynos4210_pmu_ops = {
459      .read = exynos4210_pmu_read,
460      .write = exynos4210_pmu_write,
461      .endianness = DEVICE_NATIVE_ENDIAN,
462      .valid = {
463          .min_access_size = 4,
464          .max_access_size = 4,
465          .unaligned = false
466      }
467  };
468  
469  static void exynos4210_pmu_reset(DeviceState *dev)
470  {
471      Exynos4210PmuState *s = EXYNOS4210_PMU(dev);
472      unsigned i;
473  
474      /* Set default values for registers */
475      for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
476          s->reg[i] = exynos4210_pmu_regs[i].reset_value;
477      }
478  }
479  
480  static void exynos4210_pmu_init(Object *obj)
481  {
482      Exynos4210PmuState *s = EXYNOS4210_PMU(obj);
483      SysBusDevice *dev = SYS_BUS_DEVICE(obj);
484  
485      /* memory mapping */
486      memory_region_init_io(&s->iomem, obj, &exynos4210_pmu_ops, s,
487                            "exynos4210.pmu", EXYNOS4210_PMU_REGS_MEM_SIZE);
488      sysbus_init_mmio(dev, &s->iomem);
489  }
490  
491  static const VMStateDescription exynos4210_pmu_vmstate = {
492      .name = "exynos4210.pmu",
493      .version_id = 1,
494      .minimum_version_id = 1,
495      .fields = (const VMStateField[]) {
496          VMSTATE_UINT32_ARRAY(reg, Exynos4210PmuState, PMU_NUM_OF_REGISTERS),
497          VMSTATE_END_OF_LIST()
498      }
499  };
500  
501  static void exynos4210_pmu_class_init(ObjectClass *klass, void *data)
502  {
503      DeviceClass *dc = DEVICE_CLASS(klass);
504  
505      device_class_set_legacy_reset(dc, exynos4210_pmu_reset);
506      dc->vmsd = &exynos4210_pmu_vmstate;
507  }
508  
509  static const TypeInfo exynos4210_pmu_info = {
510      .name          = TYPE_EXYNOS4210_PMU,
511      .parent        = TYPE_SYS_BUS_DEVICE,
512      .instance_size = sizeof(Exynos4210PmuState),
513      .instance_init = exynos4210_pmu_init,
514      .class_init    = exynos4210_pmu_class_init,
515  };
516  
517  static void exynos4210_pmu_register(void)
518  {
519      type_register_static(&exynos4210_pmu_info);
520  }
521  
522  type_init(exynos4210_pmu_register)
523