1 /* 2 * Exynos4210 Power Management Unit (PMU) Emulation 3 * 4 * Copyright (C) 2011 Samsung Electronics Co Ltd. 5 * Maksim Kozlov <m.kozlov@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 /* 22 * This model implements PMU registers just as a bulk of memory. Currently, 23 * the only reason this device exists is that secondary CPU boot loader 24 * uses PMU INFORM5 register as a holding pen. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "hw/sysbus.h" 29 #include "sysemu/sysemu.h" 30 31 #ifndef DEBUG_PMU 32 #define DEBUG_PMU 0 33 #endif 34 35 #ifndef DEBUG_PMU_EXTEND 36 #define DEBUG_PMU_EXTEND 0 37 #endif 38 39 #if DEBUG_PMU 40 #define PRINT_DEBUG(fmt, args...) \ 41 do { \ 42 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ 43 } while (0) 44 45 #if DEBUG_PMU_EXTEND 46 #define PRINT_DEBUG_EXTEND(fmt, args...) \ 47 do { \ 48 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ 49 } while (0) 50 #else 51 #define PRINT_DEBUG_EXTEND(fmt, args...) do {} while (0) 52 #endif /* EXTEND */ 53 54 #else 55 #define PRINT_DEBUG(fmt, args...) do {} while (0) 56 #define PRINT_DEBUG_EXTEND(fmt, args...) do {} while (0) 57 #endif 58 59 /* 60 * Offsets for PMU registers 61 */ 62 #define OM_STAT 0x0000 /* OM status register */ 63 #define RTC_CLKO_SEL 0x000C /* Controls RTCCLKOUT */ 64 #define GNSS_RTC_OUT_CTRL 0x0010 /* Controls GNSS_RTC_OUT */ 65 /* Decides whether system-level low-power mode is used. */ 66 #define SYSTEM_POWER_DOWN_CTRL 0x0200 67 /* Sets control options for CENTRAL_SEQ */ 68 #define SYSTEM_POWER_DOWN_OPTION 0x0208 69 #define SWRESET 0x0400 /* Generate software reset */ 70 #define RST_STAT 0x0404 /* Reset status register */ 71 #define WAKEUP_STAT 0x0600 /* Wakeup status register */ 72 #define EINT_WAKEUP_MASK 0x0604 /* Configure External INTerrupt mask */ 73 #define WAKEUP_MASK 0x0608 /* Configure wakeup source mask */ 74 #define HDMI_PHY_CONTROL 0x0700 /* HDMI PHY control register */ 75 #define USBDEVICE_PHY_CONTROL 0x0704 /* USB Device PHY control register */ 76 #define USBHOST_PHY_CONTROL 0x0708 /* USB HOST PHY control register */ 77 #define DAC_PHY_CONTROL 0x070C /* DAC control register */ 78 #define MIPI_PHY0_CONTROL 0x0710 /* MIPI PHY control register */ 79 #define MIPI_PHY1_CONTROL 0x0714 /* MIPI PHY control register */ 80 #define ADC_PHY_CONTROL 0x0718 /* TS-ADC control register */ 81 #define PCIe_PHY_CONTROL 0x071C /* TS-PCIe control register */ 82 #define SATA_PHY_CONTROL 0x0720 /* TS-SATA control register */ 83 #define INFORM0 0x0800 /* Information register 0 */ 84 #define INFORM1 0x0804 /* Information register 1 */ 85 #define INFORM2 0x0808 /* Information register 2 */ 86 #define INFORM3 0x080C /* Information register 3 */ 87 #define INFORM4 0x0810 /* Information register 4 */ 88 #define INFORM5 0x0814 /* Information register 5 */ 89 #define INFORM6 0x0818 /* Information register 6 */ 90 #define INFORM7 0x081C /* Information register 7 */ 91 #define PMU_DEBUG 0x0A00 /* PMU debug register */ 92 /* Registers to set system-level low-power option */ 93 #define ARM_CORE0_SYS_PWR_REG 0x1000 94 #define ARM_CORE1_SYS_PWR_REG 0x1010 95 #define ARM_COMMON_SYS_PWR_REG 0x1080 96 #define ARM_CPU_L2_0_SYS_PWR_REG 0x10C0 97 #define ARM_CPU_L2_1_SYS_PWR_REG 0x10C4 98 #define CMU_ACLKSTOP_SYS_PWR_REG 0x1100 99 #define CMU_SCLKSTOP_SYS_PWR_REG 0x1104 100 #define CMU_RESET_SYS_PWR_REG 0x110C 101 #define APLL_SYSCLK_SYS_PWR_REG 0x1120 102 #define MPLL_SYSCLK_SYS_PWR_REG 0x1124 103 #define VPLL_SYSCLK_SYS_PWR_REG 0x1128 104 #define EPLL_SYSCLK_SYS_PWR_REG 0x112C 105 #define CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG 0x1138 106 #define CMU_RESET_GPS_ALIVE_SYS_PWR_REG 0x113C 107 #define CMU_CLKSTOP_CAM_SYS_PWR_REG 0x1140 108 #define CMU_CLKSTOP_TV_SYS_PWR_REG 0x1144 109 #define CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1148 110 #define CMU_CLKSTOP_G3D_SYS_PWR_REG 0x114C 111 #define CMU_CLKSTOP_LCD0_SYS_PWR_REG 0x1150 112 #define CMU_CLKSTOP_LCD1_SYS_PWR_REG 0x1154 113 #define CMU_CLKSTOP_MAUDIO_SYS_PWR_REG 0x1158 114 #define CMU_CLKSTOP_GPS_SYS_PWR_REG 0x115C 115 #define CMU_RESET_CAM_SYS_PWR_REG 0x1160 116 #define CMU_RESET_TV_SYS_PWR_REG 0x1164 117 #define CMU_RESET_MFC_SYS_PWR_REG 0x1168 118 #define CMU_RESET_G3D_SYS_PWR_REG 0x116C 119 #define CMU_RESET_LCD0_SYS_PWR_REG 0x1170 120 #define CMU_RESET_LCD1_SYS_PWR_REG 0x1174 121 #define CMU_RESET_MAUDIO_SYS_PWR_REG 0x1178 122 #define CMU_RESET_GPS_SYS_PWR_REG 0x117C 123 #define TOP_BUS_SYS_PWR_REG 0x1180 124 #define TOP_RETENTION_SYS_PWR_REG 0x1184 125 #define TOP_PWR_SYS_PWR_REG 0x1188 126 #define LOGIC_RESET_SYS_PWR_REG 0x11A0 127 #define OneNANDXL_MEM_SYS_PWR_REG 0x11C0 128 #define MODEMIF_MEM_SYS_PWR_REG 0x11C4 129 #define USBDEVICE_MEM_SYS_PWR_REG 0x11CC 130 #define SDMMC_MEM_SYS_PWR_REG 0x11D0 131 #define CSSYS_MEM_SYS_PWR_REG 0x11D4 132 #define SECSS_MEM_SYS_PWR_REG 0x11D8 133 #define PCIe_MEM_SYS_PWR_REG 0x11E0 134 #define SATA_MEM_SYS_PWR_REG 0x11E4 135 #define PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200 136 #define PAD_RETENTION_MAUDIO_SYS_PWR_REG 0x1204 137 #define PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220 138 #define PAD_RETENTION_UART_SYS_PWR_REG 0x1224 139 #define PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228 140 #define PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C 141 #define PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230 142 #define PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234 143 #define PAD_ISOLATION_SYS_PWR_REG 0x1240 144 #define PAD_ALV_SEL_SYS_PWR_REG 0x1260 145 #define XUSBXTI_SYS_PWR_REG 0x1280 146 #define XXTI_SYS_PWR_REG 0x1284 147 #define EXT_REGULATOR_SYS_PWR_REG 0x12C0 148 #define GPIO_MODE_SYS_PWR_REG 0x1300 149 #define GPIO_MODE_MAUDIO_SYS_PWR_REG 0x1340 150 #define CAM_SYS_PWR_REG 0x1380 151 #define TV_SYS_PWR_REG 0x1384 152 #define MFC_SYS_PWR_REG 0x1388 153 #define G3D_SYS_PWR_REG 0x138C 154 #define LCD0_SYS_PWR_REG 0x1390 155 #define LCD1_SYS_PWR_REG 0x1394 156 #define MAUDIO_SYS_PWR_REG 0x1398 157 #define GPS_SYS_PWR_REG 0x139C 158 #define GPS_ALIVE_SYS_PWR_REG 0x13A0 159 #define ARM_CORE0_CONFIGURATION 0x2000 /* Configure power mode of ARM_CORE0 */ 160 #define ARM_CORE0_STATUS 0x2004 /* Check power mode of ARM_CORE0 */ 161 #define ARM_CORE0_OPTION 0x2008 /* Sets control options for ARM_CORE0 */ 162 #define ARM_CORE1_CONFIGURATION 0x2080 /* Configure power mode of ARM_CORE1 */ 163 #define ARM_CORE1_STATUS 0x2084 /* Check power mode of ARM_CORE1 */ 164 #define ARM_CORE1_OPTION 0x2088 /* Sets control options for ARM_CORE0 */ 165 #define ARM_COMMON_OPTION 0x2408 /* Sets control options for ARM_COMMON */ 166 /* Configure power mode of ARM_CPU_L2_0 */ 167 #define ARM_CPU_L2_0_CONFIGURATION 0x2600 168 #define ARM_CPU_L2_0_STATUS 0x2604 /* Check power mode of ARM_CPU_L2_0 */ 169 /* Configure power mode of ARM_CPU_L2_1 */ 170 #define ARM_CPU_L2_1_CONFIGURATION 0x2620 171 #define ARM_CPU_L2_1_STATUS 0x2624 /* Check power mode of ARM_CPU_L2_1 */ 172 /* Sets control options for PAD_RETENTION_MAUDIO */ 173 #define PAD_RETENTION_MAUDIO_OPTION 0x3028 174 /* Sets control options for PAD_RETENTION_GPIO */ 175 #define PAD_RETENTION_GPIO_OPTION 0x3108 176 /* Sets control options for PAD_RETENTION_UART */ 177 #define PAD_RETENTION_UART_OPTION 0x3128 178 /* Sets control options for PAD_RETENTION_MMCA */ 179 #define PAD_RETENTION_MMCA_OPTION 0x3148 180 /* Sets control options for PAD_RETENTION_MMCB */ 181 #define PAD_RETENTION_MMCB_OPTION 0x3168 182 /* Sets control options for PAD_RETENTION_EBIA */ 183 #define PAD_RETENTION_EBIA_OPTION 0x3188 184 /* Sets control options for PAD_RETENTION_EBIB */ 185 #define PAD_RETENTION_EBIB_OPTION 0x31A8 186 #define PS_HOLD_CONTROL 0x330C /* PS_HOLD control register */ 187 #define XUSBXTI_CONFIGURATION 0x3400 /* Configure the pad of XUSBXTI */ 188 #define XUSBXTI_STATUS 0x3404 /* Check the pad of XUSBXTI */ 189 /* Sets time required for XUSBXTI to be stabilized */ 190 #define XUSBXTI_DURATION 0x341C 191 #define XXTI_CONFIGURATION 0x3420 /* Configure the pad of XXTI */ 192 #define XXTI_STATUS 0x3424 /* Check the pad of XXTI */ 193 /* Sets time required for XXTI to be stabilized */ 194 #define XXTI_DURATION 0x343C 195 /* Sets time required for EXT_REGULATOR to be stabilized */ 196 #define EXT_REGULATOR_DURATION 0x361C 197 #define CAM_CONFIGURATION 0x3C00 /* Configure power mode of CAM */ 198 #define CAM_STATUS 0x3C04 /* Check power mode of CAM */ 199 #define CAM_OPTION 0x3C08 /* Sets control options for CAM */ 200 #define TV_CONFIGURATION 0x3C20 /* Configure power mode of TV */ 201 #define TV_STATUS 0x3C24 /* Check power mode of TV */ 202 #define TV_OPTION 0x3C28 /* Sets control options for TV */ 203 #define MFC_CONFIGURATION 0x3C40 /* Configure power mode of MFC */ 204 #define MFC_STATUS 0x3C44 /* Check power mode of MFC */ 205 #define MFC_OPTION 0x3C48 /* Sets control options for MFC */ 206 #define G3D_CONFIGURATION 0x3C60 /* Configure power mode of G3D */ 207 #define G3D_STATUS 0x3C64 /* Check power mode of G3D */ 208 #define G3D_OPTION 0x3C68 /* Sets control options for G3D */ 209 #define LCD0_CONFIGURATION 0x3C80 /* Configure power mode of LCD0 */ 210 #define LCD0_STATUS 0x3C84 /* Check power mode of LCD0 */ 211 #define LCD0_OPTION 0x3C88 /* Sets control options for LCD0 */ 212 #define LCD1_CONFIGURATION 0x3CA0 /* Configure power mode of LCD1 */ 213 #define LCD1_STATUS 0x3CA4 /* Check power mode of LCD1 */ 214 #define LCD1_OPTION 0x3CA8 /* Sets control options for LCD1 */ 215 #define GPS_CONFIGURATION 0x3CE0 /* Configure power mode of GPS */ 216 #define GPS_STATUS 0x3CE4 /* Check power mode of GPS */ 217 #define GPS_OPTION 0x3CE8 /* Sets control options for GPS */ 218 #define GPS_ALIVE_CONFIGURATION 0x3D00 /* Configure power mode of GPS */ 219 #define GPS_ALIVE_STATUS 0x3D04 /* Check power mode of GPS */ 220 #define GPS_ALIVE_OPTION 0x3D08 /* Sets control options for GPS */ 221 222 #define EXYNOS4210_PMU_REGS_MEM_SIZE 0x3d0c 223 224 typedef struct Exynos4210PmuReg { 225 const char *name; /* for debug only */ 226 uint32_t offset; 227 uint32_t reset_value; 228 } Exynos4210PmuReg; 229 230 static const Exynos4210PmuReg exynos4210_pmu_regs[] = { 231 {"OM_STAT", OM_STAT, 0x00000000}, 232 {"RTC_CLKO_SEL", RTC_CLKO_SEL, 0x00000000}, 233 {"GNSS_RTC_OUT_CTRL", GNSS_RTC_OUT_CTRL, 0x00000001}, 234 {"SYSTEM_POWER_DOWN_CTRL", SYSTEM_POWER_DOWN_CTRL, 0x00010000}, 235 {"SYSTEM_POWER_DOWN_OPTION", SYSTEM_POWER_DOWN_OPTION, 0x03030000}, 236 {"SWRESET", SWRESET, 0x00000000}, 237 {"RST_STAT", RST_STAT, 0x00000000}, 238 {"WAKEUP_STAT", WAKEUP_STAT, 0x00000000}, 239 {"EINT_WAKEUP_MASK", EINT_WAKEUP_MASK, 0x00000000}, 240 {"WAKEUP_MASK", WAKEUP_MASK, 0x00000000}, 241 {"HDMI_PHY_CONTROL", HDMI_PHY_CONTROL, 0x00960000}, 242 {"USBDEVICE_PHY_CONTROL", USBDEVICE_PHY_CONTROL, 0x00000000}, 243 {"USBHOST_PHY_CONTROL", USBHOST_PHY_CONTROL, 0x00000000}, 244 {"DAC_PHY_CONTROL", DAC_PHY_CONTROL, 0x00000000}, 245 {"MIPI_PHY0_CONTROL", MIPI_PHY0_CONTROL, 0x00000000}, 246 {"MIPI_PHY1_CONTROL", MIPI_PHY1_CONTROL, 0x00000000}, 247 {"ADC_PHY_CONTROL", ADC_PHY_CONTROL, 0x00000001}, 248 {"PCIe_PHY_CONTROL", PCIe_PHY_CONTROL, 0x00000000}, 249 {"SATA_PHY_CONTROL", SATA_PHY_CONTROL, 0x00000000}, 250 {"INFORM0", INFORM0, 0x00000000}, 251 {"INFORM1", INFORM1, 0x00000000}, 252 {"INFORM2", INFORM2, 0x00000000}, 253 {"INFORM3", INFORM3, 0x00000000}, 254 {"INFORM4", INFORM4, 0x00000000}, 255 {"INFORM5", INFORM5, 0x00000000}, 256 {"INFORM6", INFORM6, 0x00000000}, 257 {"INFORM7", INFORM7, 0x00000000}, 258 {"PMU_DEBUG", PMU_DEBUG, 0x00000000}, 259 {"ARM_CORE0_SYS_PWR_REG", ARM_CORE0_SYS_PWR_REG, 0xFFFFFFFF}, 260 {"ARM_CORE1_SYS_PWR_REG", ARM_CORE1_SYS_PWR_REG, 0xFFFFFFFF}, 261 {"ARM_COMMON_SYS_PWR_REG", ARM_COMMON_SYS_PWR_REG, 0xFFFFFFFF}, 262 {"ARM_CPU_L2_0_SYS_PWR_REG", ARM_CPU_L2_0_SYS_PWR_REG, 0xFFFFFFFF}, 263 {"ARM_CPU_L2_1_SYS_PWR_REG", ARM_CPU_L2_1_SYS_PWR_REG, 0xFFFFFFFF}, 264 {"CMU_ACLKSTOP_SYS_PWR_REG", CMU_ACLKSTOP_SYS_PWR_REG, 0xFFFFFFFF}, 265 {"CMU_SCLKSTOP_SYS_PWR_REG", CMU_SCLKSTOP_SYS_PWR_REG, 0xFFFFFFFF}, 266 {"CMU_RESET_SYS_PWR_REG", CMU_RESET_SYS_PWR_REG, 0xFFFFFFFF}, 267 {"APLL_SYSCLK_SYS_PWR_REG", APLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF}, 268 {"MPLL_SYSCLK_SYS_PWR_REG", MPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF}, 269 {"VPLL_SYSCLK_SYS_PWR_REG", VPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF}, 270 {"EPLL_SYSCLK_SYS_PWR_REG", EPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF}, 271 {"CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG", CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG, 272 0xFFFFFFFF}, 273 {"CMU_RESET_GPS_ALIVE_SYS_PWR_REG", CMU_RESET_GPS_ALIVE_SYS_PWR_REG, 274 0xFFFFFFFF}, 275 {"CMU_CLKSTOP_CAM_SYS_PWR_REG", CMU_CLKSTOP_CAM_SYS_PWR_REG, 0xFFFFFFFF}, 276 {"CMU_CLKSTOP_TV_SYS_PWR_REG", CMU_CLKSTOP_TV_SYS_PWR_REG, 0xFFFFFFFF}, 277 {"CMU_CLKSTOP_MFC_SYS_PWR_REG", CMU_CLKSTOP_MFC_SYS_PWR_REG, 0xFFFFFFFF}, 278 {"CMU_CLKSTOP_G3D_SYS_PWR_REG", CMU_CLKSTOP_G3D_SYS_PWR_REG, 0xFFFFFFFF}, 279 {"CMU_CLKSTOP_LCD0_SYS_PWR_REG", CMU_CLKSTOP_LCD0_SYS_PWR_REG, 0xFFFFFFFF}, 280 {"CMU_CLKSTOP_LCD1_SYS_PWR_REG", CMU_CLKSTOP_LCD1_SYS_PWR_REG, 0xFFFFFFFF}, 281 {"CMU_CLKSTOP_MAUDIO_SYS_PWR_REG", CMU_CLKSTOP_MAUDIO_SYS_PWR_REG, 282 0xFFFFFFFF}, 283 {"CMU_CLKSTOP_GPS_SYS_PWR_REG", CMU_CLKSTOP_GPS_SYS_PWR_REG, 0xFFFFFFFF}, 284 {"CMU_RESET_CAM_SYS_PWR_REG", CMU_RESET_CAM_SYS_PWR_REG, 0xFFFFFFFF}, 285 {"CMU_RESET_TV_SYS_PWR_REG", CMU_RESET_TV_SYS_PWR_REG, 0xFFFFFFFF}, 286 {"CMU_RESET_MFC_SYS_PWR_REG", CMU_RESET_MFC_SYS_PWR_REG, 0xFFFFFFFF}, 287 {"CMU_RESET_G3D_SYS_PWR_REG", CMU_RESET_G3D_SYS_PWR_REG, 0xFFFFFFFF}, 288 {"CMU_RESET_LCD0_SYS_PWR_REG", CMU_RESET_LCD0_SYS_PWR_REG, 0xFFFFFFFF}, 289 {"CMU_RESET_LCD1_SYS_PWR_REG", CMU_RESET_LCD1_SYS_PWR_REG, 0xFFFFFFFF}, 290 {"CMU_RESET_MAUDIO_SYS_PWR_REG", CMU_RESET_MAUDIO_SYS_PWR_REG, 0xFFFFFFFF}, 291 {"CMU_RESET_GPS_SYS_PWR_REG", CMU_RESET_GPS_SYS_PWR_REG, 0xFFFFFFFF}, 292 {"TOP_BUS_SYS_PWR_REG", TOP_BUS_SYS_PWR_REG, 0xFFFFFFFF}, 293 {"TOP_RETENTION_SYS_PWR_REG", TOP_RETENTION_SYS_PWR_REG, 0xFFFFFFFF}, 294 {"TOP_PWR_SYS_PWR_REG", TOP_PWR_SYS_PWR_REG, 0xFFFFFFFF}, 295 {"LOGIC_RESET_SYS_PWR_REG", LOGIC_RESET_SYS_PWR_REG, 0xFFFFFFFF}, 296 {"OneNANDXL_MEM_SYS_PWR_REG", OneNANDXL_MEM_SYS_PWR_REG, 0xFFFFFFFF}, 297 {"MODEMIF_MEM_SYS_PWR_REG", MODEMIF_MEM_SYS_PWR_REG, 0xFFFFFFFF}, 298 {"USBDEVICE_MEM_SYS_PWR_REG", USBDEVICE_MEM_SYS_PWR_REG, 0xFFFFFFFF}, 299 {"SDMMC_MEM_SYS_PWR_REG", SDMMC_MEM_SYS_PWR_REG, 0xFFFFFFFF}, 300 {"CSSYS_MEM_SYS_PWR_REG", CSSYS_MEM_SYS_PWR_REG, 0xFFFFFFFF}, 301 {"SECSS_MEM_SYS_PWR_REG", SECSS_MEM_SYS_PWR_REG, 0xFFFFFFFF}, 302 {"PCIe_MEM_SYS_PWR_REG", PCIe_MEM_SYS_PWR_REG, 0xFFFFFFFF}, 303 {"SATA_MEM_SYS_PWR_REG", SATA_MEM_SYS_PWR_REG, 0xFFFFFFFF}, 304 {"PAD_RETENTION_DRAM_SYS_PWR_REG", PAD_RETENTION_DRAM_SYS_PWR_REG, 305 0xFFFFFFFF}, 306 {"PAD_RETENTION_MAUDIO_SYS_PWR_REG", PAD_RETENTION_MAUDIO_SYS_PWR_REG, 307 0xFFFFFFFF}, 308 {"PAD_RETENTION_GPIO_SYS_PWR_REG", PAD_RETENTION_GPIO_SYS_PWR_REG, 309 0xFFFFFFFF}, 310 {"PAD_RETENTION_UART_SYS_PWR_REG", PAD_RETENTION_UART_SYS_PWR_REG, 311 0xFFFFFFFF}, 312 {"PAD_RETENTION_MMCA_SYS_PWR_REG", PAD_RETENTION_MMCA_SYS_PWR_REG, 313 0xFFFFFFFF}, 314 {"PAD_RETENTION_MMCB_SYS_PWR_REG", PAD_RETENTION_MMCB_SYS_PWR_REG, 315 0xFFFFFFFF}, 316 {"PAD_RETENTION_EBIA_SYS_PWR_REG", PAD_RETENTION_EBIA_SYS_PWR_REG, 317 0xFFFFFFFF}, 318 {"PAD_RETENTION_EBIB_SYS_PWR_REG", PAD_RETENTION_EBIB_SYS_PWR_REG, 319 0xFFFFFFFF}, 320 {"PAD_ISOLATION_SYS_PWR_REG", PAD_ISOLATION_SYS_PWR_REG, 0xFFFFFFFF}, 321 {"PAD_ALV_SEL_SYS_PWR_REG", PAD_ALV_SEL_SYS_PWR_REG, 0xFFFFFFFF}, 322 {"XUSBXTI_SYS_PWR_REG", XUSBXTI_SYS_PWR_REG, 0xFFFFFFFF}, 323 {"XXTI_SYS_PWR_REG", XXTI_SYS_PWR_REG, 0xFFFFFFFF}, 324 {"EXT_REGULATOR_SYS_PWR_REG", EXT_REGULATOR_SYS_PWR_REG, 0xFFFFFFFF}, 325 {"GPIO_MODE_SYS_PWR_REG", GPIO_MODE_SYS_PWR_REG, 0xFFFFFFFF}, 326 {"GPIO_MODE_MAUDIO_SYS_PWR_REG", GPIO_MODE_MAUDIO_SYS_PWR_REG, 0xFFFFFFFF}, 327 {"CAM_SYS_PWR_REG", CAM_SYS_PWR_REG, 0xFFFFFFFF}, 328 {"TV_SYS_PWR_REG", TV_SYS_PWR_REG, 0xFFFFFFFF}, 329 {"MFC_SYS_PWR_REG", MFC_SYS_PWR_REG, 0xFFFFFFFF}, 330 {"G3D_SYS_PWR_REG", G3D_SYS_PWR_REG, 0xFFFFFFFF}, 331 {"LCD0_SYS_PWR_REG", LCD0_SYS_PWR_REG, 0xFFFFFFFF}, 332 {"LCD1_SYS_PWR_REG", LCD1_SYS_PWR_REG, 0xFFFFFFFF}, 333 {"MAUDIO_SYS_PWR_REG", MAUDIO_SYS_PWR_REG, 0xFFFFFFFF}, 334 {"GPS_SYS_PWR_REG", GPS_SYS_PWR_REG, 0xFFFFFFFF}, 335 {"GPS_ALIVE_SYS_PWR_REG", GPS_ALIVE_SYS_PWR_REG, 0xFFFFFFFF}, 336 {"ARM_CORE0_CONFIGURATION", ARM_CORE0_CONFIGURATION, 0x00000003}, 337 {"ARM_CORE0_STATUS", ARM_CORE0_STATUS, 0x00030003}, 338 {"ARM_CORE0_OPTION", ARM_CORE0_OPTION, 0x01010001}, 339 {"ARM_CORE1_CONFIGURATION", ARM_CORE1_CONFIGURATION, 0x00000003}, 340 {"ARM_CORE1_STATUS", ARM_CORE1_STATUS, 0x00030003}, 341 {"ARM_CORE1_OPTION", ARM_CORE1_OPTION, 0x01010001}, 342 {"ARM_COMMON_OPTION", ARM_COMMON_OPTION, 0x00000001}, 343 {"ARM_CPU_L2_0_CONFIGURATION", ARM_CPU_L2_0_CONFIGURATION, 0x00000003}, 344 {"ARM_CPU_L2_0_STATUS", ARM_CPU_L2_0_STATUS, 0x00000003}, 345 {"ARM_CPU_L2_1_CONFIGURATION", ARM_CPU_L2_1_CONFIGURATION, 0x00000003}, 346 {"ARM_CPU_L2_1_STATUS", ARM_CPU_L2_1_STATUS, 0x00000003}, 347 {"PAD_RETENTION_MAUDIO_OPTION", PAD_RETENTION_MAUDIO_OPTION, 0x00000000}, 348 {"PAD_RETENTION_GPIO_OPTION", PAD_RETENTION_GPIO_OPTION, 0x00000000}, 349 {"PAD_RETENTION_UART_OPTION", PAD_RETENTION_UART_OPTION, 0x00000000}, 350 {"PAD_RETENTION_MMCA_OPTION", PAD_RETENTION_MMCA_OPTION, 0x00000000}, 351 {"PAD_RETENTION_MMCB_OPTION", PAD_RETENTION_MMCB_OPTION, 0x00000000}, 352 {"PAD_RETENTION_EBIA_OPTION", PAD_RETENTION_EBIA_OPTION, 0x00000000}, 353 {"PAD_RETENTION_EBIB_OPTION", PAD_RETENTION_EBIB_OPTION, 0x00000000}, 354 /* 355 * PS_HOLD_CONTROL: reset value and manually toggle high the DATA bit. 356 * DATA bit high, set usually by bootloader, keeps system on. 357 */ 358 {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200 | BIT(8)}, 359 {"XUSBXTI_CONFIGURATION", XUSBXTI_CONFIGURATION, 0x00000001}, 360 {"XUSBXTI_STATUS", XUSBXTI_STATUS, 0x00000001}, 361 {"XUSBXTI_DURATION", XUSBXTI_DURATION, 0xFFF00000}, 362 {"XXTI_CONFIGURATION", XXTI_CONFIGURATION, 0x00000001}, 363 {"XXTI_STATUS", XXTI_STATUS, 0x00000001}, 364 {"XXTI_DURATION", XXTI_DURATION, 0xFFF00000}, 365 {"EXT_REGULATOR_DURATION", EXT_REGULATOR_DURATION, 0xFFF03FFF}, 366 {"CAM_CONFIGURATION", CAM_CONFIGURATION, 0x00000007}, 367 {"CAM_STATUS", CAM_STATUS, 0x00060007}, 368 {"CAM_OPTION", CAM_OPTION, 0x00000001}, 369 {"TV_CONFIGURATION", TV_CONFIGURATION, 0x00000007}, 370 {"TV_STATUS", TV_STATUS, 0x00060007}, 371 {"TV_OPTION", TV_OPTION, 0x00000001}, 372 {"MFC_CONFIGURATION", MFC_CONFIGURATION, 0x00000007}, 373 {"MFC_STATUS", MFC_STATUS, 0x00060007}, 374 {"MFC_OPTION", MFC_OPTION, 0x00000001}, 375 {"G3D_CONFIGURATION", G3D_CONFIGURATION, 0x00000007}, 376 {"G3D_STATUS", G3D_STATUS, 0x00060007}, 377 {"G3D_OPTION", G3D_OPTION, 0x00000001}, 378 {"LCD0_CONFIGURATION", LCD0_CONFIGURATION, 0x00000007}, 379 {"LCD0_STATUS", LCD0_STATUS, 0x00060007}, 380 {"LCD0_OPTION", LCD0_OPTION, 0x00000001}, 381 {"LCD1_CONFIGURATION", LCD1_CONFIGURATION, 0x00000007}, 382 {"LCD1_STATUS", LCD1_STATUS, 0x00060007}, 383 {"LCD1_OPTION", LCD1_OPTION, 0x00000001}, 384 {"GPS_CONFIGURATION", GPS_CONFIGURATION, 0x00000007}, 385 {"GPS_STATUS", GPS_STATUS, 0x00060007}, 386 {"GPS_OPTION", GPS_OPTION, 0x00000001}, 387 {"GPS_ALIVE_CONFIGURATION", GPS_ALIVE_CONFIGURATION, 0x00000007}, 388 {"GPS_ALIVE_STATUS", GPS_ALIVE_STATUS, 0x00060007}, 389 {"GPS_ALIVE_OPTION", GPS_ALIVE_OPTION, 0x00000001}, 390 }; 391 392 #define PMU_NUM_OF_REGISTERS ARRAY_SIZE(exynos4210_pmu_regs) 393 394 #define TYPE_EXYNOS4210_PMU "exynos4210.pmu" 395 #define EXYNOS4210_PMU(obj) \ 396 OBJECT_CHECK(Exynos4210PmuState, (obj), TYPE_EXYNOS4210_PMU) 397 398 typedef struct Exynos4210PmuState { 399 SysBusDevice parent_obj; 400 401 MemoryRegion iomem; 402 uint32_t reg[PMU_NUM_OF_REGISTERS]; 403 } Exynos4210PmuState; 404 405 static void exynos4210_pmu_poweroff(void) 406 { 407 PRINT_DEBUG("QEMU PMU: PS_HOLD bit down, powering off\n"); 408 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 409 } 410 411 static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset, 412 unsigned size) 413 { 414 Exynos4210PmuState *s = (Exynos4210PmuState *)opaque; 415 const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs; 416 unsigned int i; 417 418 for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) { 419 if (reg_p->offset == offset) { 420 PRINT_DEBUG_EXTEND("%s [0x%04x] -> 0x%04x\n", reg_p->name, 421 (uint32_t)offset, s->reg[i]); 422 return s->reg[i]; 423 } 424 reg_p++; 425 } 426 PRINT_DEBUG("QEMU PMU ERROR: bad read offset 0x%04x\n", (uint32_t)offset); 427 return 0; 428 } 429 430 static void exynos4210_pmu_write(void *opaque, hwaddr offset, 431 uint64_t val, unsigned size) 432 { 433 Exynos4210PmuState *s = (Exynos4210PmuState *)opaque; 434 const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs; 435 unsigned int i; 436 437 for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) { 438 if (reg_p->offset == offset) { 439 PRINT_DEBUG_EXTEND("%s <0x%04x> <- 0x%04x\n", reg_p->name, 440 (uint32_t)offset, (uint32_t)val); 441 s->reg[i] = val; 442 if ((offset == PS_HOLD_CONTROL) && ((val & BIT(8)) == 0)) { 443 /* 444 * We are interested only in setting data bit 445 * of PS_HOLD_CONTROL register to indicate power off request. 446 */ 447 exynos4210_pmu_poweroff(); 448 } 449 return; 450 } 451 reg_p++; 452 } 453 PRINT_DEBUG("QEMU PMU ERROR: bad write offset 0x%04x\n", (uint32_t)offset); 454 } 455 456 static const MemoryRegionOps exynos4210_pmu_ops = { 457 .read = exynos4210_pmu_read, 458 .write = exynos4210_pmu_write, 459 .endianness = DEVICE_NATIVE_ENDIAN, 460 .valid = { 461 .min_access_size = 4, 462 .max_access_size = 4, 463 .unaligned = false 464 } 465 }; 466 467 static void exynos4210_pmu_reset(DeviceState *dev) 468 { 469 Exynos4210PmuState *s = EXYNOS4210_PMU(dev); 470 unsigned i; 471 472 /* Set default values for registers */ 473 for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) { 474 s->reg[i] = exynos4210_pmu_regs[i].reset_value; 475 } 476 } 477 478 static void exynos4210_pmu_init(Object *obj) 479 { 480 Exynos4210PmuState *s = EXYNOS4210_PMU(obj); 481 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 482 483 /* memory mapping */ 484 memory_region_init_io(&s->iomem, obj, &exynos4210_pmu_ops, s, 485 "exynos4210.pmu", EXYNOS4210_PMU_REGS_MEM_SIZE); 486 sysbus_init_mmio(dev, &s->iomem); 487 } 488 489 static const VMStateDescription exynos4210_pmu_vmstate = { 490 .name = "exynos4210.pmu", 491 .version_id = 1, 492 .minimum_version_id = 1, 493 .fields = (VMStateField[]) { 494 VMSTATE_UINT32_ARRAY(reg, Exynos4210PmuState, PMU_NUM_OF_REGISTERS), 495 VMSTATE_END_OF_LIST() 496 } 497 }; 498 499 static void exynos4210_pmu_class_init(ObjectClass *klass, void *data) 500 { 501 DeviceClass *dc = DEVICE_CLASS(klass); 502 503 dc->reset = exynos4210_pmu_reset; 504 dc->vmsd = &exynos4210_pmu_vmstate; 505 } 506 507 static const TypeInfo exynos4210_pmu_info = { 508 .name = TYPE_EXYNOS4210_PMU, 509 .parent = TYPE_SYS_BUS_DEVICE, 510 .instance_size = sizeof(Exynos4210PmuState), 511 .instance_init = exynos4210_pmu_init, 512 .class_init = exynos4210_pmu_class_init, 513 }; 514 515 static void exynos4210_pmu_register(void) 516 { 517 type_register_static(&exynos4210_pmu_info); 518 } 519 520 type_init(exynos4210_pmu_register) 521