1 /* 2 * QEMU educational PCI device 3 * 4 * Copyright (c) 2012-2015 Jiri Slaby 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/pci/pci.h" 28 #include "hw/pci/msi.h" 29 #include "qemu/timer.h" 30 #include "qemu/main-loop.h" /* iothread mutex */ 31 #include "qapi/visitor.h" 32 33 #define EDU(obj) OBJECT_CHECK(EduState, obj, "edu") 34 35 #define FACT_IRQ 0x00000001 36 #define DMA_IRQ 0x00000100 37 38 #define DMA_START 0x40000 39 #define DMA_SIZE 4096 40 41 typedef struct { 42 PCIDevice pdev; 43 MemoryRegion mmio; 44 45 QemuThread thread; 46 QemuMutex thr_mutex; 47 QemuCond thr_cond; 48 bool stopping; 49 50 uint32_t addr4; 51 uint32_t fact; 52 #define EDU_STATUS_COMPUTING 0x01 53 #define EDU_STATUS_IRQFACT 0x80 54 uint32_t status; 55 56 uint32_t irq_status; 57 58 #define EDU_DMA_RUN 0x1 59 #define EDU_DMA_DIR(cmd) (((cmd) & 0x2) >> 1) 60 # define EDU_DMA_FROM_PCI 0 61 # define EDU_DMA_TO_PCI 1 62 #define EDU_DMA_IRQ 0x4 63 struct dma_state { 64 dma_addr_t src; 65 dma_addr_t dst; 66 dma_addr_t cnt; 67 dma_addr_t cmd; 68 } dma; 69 QEMUTimer dma_timer; 70 char dma_buf[DMA_SIZE]; 71 uint64_t dma_mask; 72 } EduState; 73 74 static bool edu_msi_enabled(EduState *edu) 75 { 76 return msi_enabled(&edu->pdev); 77 } 78 79 static void edu_raise_irq(EduState *edu, uint32_t val) 80 { 81 edu->irq_status |= val; 82 if (edu->irq_status) { 83 if (edu_msi_enabled(edu)) { 84 msi_notify(&edu->pdev, 0); 85 } else { 86 pci_set_irq(&edu->pdev, 1); 87 } 88 } 89 } 90 91 static void edu_lower_irq(EduState *edu, uint32_t val) 92 { 93 edu->irq_status &= ~val; 94 95 if (!edu->irq_status && !edu_msi_enabled(edu)) { 96 pci_set_irq(&edu->pdev, 0); 97 } 98 } 99 100 static bool within(uint32_t addr, uint32_t start, uint32_t end) 101 { 102 return start <= addr && addr < end; 103 } 104 105 static void edu_check_range(uint32_t addr, uint32_t size1, uint32_t start, 106 uint32_t size2) 107 { 108 uint32_t end1 = addr + size1; 109 uint32_t end2 = start + size2; 110 111 if (within(addr, start, end2) && 112 end1 > addr && within(end1, start, end2)) { 113 return; 114 } 115 116 hw_error("EDU: DMA range 0x%.8x-0x%.8x out of bounds (0x%.8x-0x%.8x)!", 117 addr, end1 - 1, start, end2 - 1); 118 } 119 120 static dma_addr_t edu_clamp_addr(const EduState *edu, dma_addr_t addr) 121 { 122 dma_addr_t res = addr & edu->dma_mask; 123 124 if (addr != res) { 125 printf("EDU: clamping DMA %#.16"PRIx64" to %#.16"PRIx64"!\n", addr, res); 126 } 127 128 return res; 129 } 130 131 static void edu_dma_timer(void *opaque) 132 { 133 EduState *edu = opaque; 134 bool raise_irq = false; 135 136 if (!(edu->dma.cmd & EDU_DMA_RUN)) { 137 return; 138 } 139 140 if (EDU_DMA_DIR(edu->dma.cmd) == EDU_DMA_FROM_PCI) { 141 uint32_t dst = edu->dma.dst; 142 edu_check_range(dst, edu->dma.cnt, DMA_START, DMA_SIZE); 143 dst -= DMA_START; 144 pci_dma_read(&edu->pdev, edu_clamp_addr(edu, edu->dma.src), 145 edu->dma_buf + dst, edu->dma.cnt); 146 } else { 147 uint32_t src = edu->dma.src; 148 edu_check_range(src, edu->dma.cnt, DMA_START, DMA_SIZE); 149 src -= DMA_START; 150 pci_dma_write(&edu->pdev, edu_clamp_addr(edu, edu->dma.dst), 151 edu->dma_buf + src, edu->dma.cnt); 152 } 153 154 edu->dma.cmd &= ~EDU_DMA_RUN; 155 if (edu->dma.cmd & EDU_DMA_IRQ) { 156 raise_irq = true; 157 } 158 159 if (raise_irq) { 160 edu_raise_irq(edu, DMA_IRQ); 161 } 162 } 163 164 static void dma_rw(EduState *edu, bool write, dma_addr_t *val, dma_addr_t *dma, 165 bool timer) 166 { 167 if (write && (edu->dma.cmd & EDU_DMA_RUN)) { 168 return; 169 } 170 171 if (write) { 172 *dma = *val; 173 } else { 174 *val = *dma; 175 } 176 177 if (timer) { 178 timer_mod(&edu->dma_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 100); 179 } 180 } 181 182 static uint64_t edu_mmio_read(void *opaque, hwaddr addr, unsigned size) 183 { 184 EduState *edu = opaque; 185 uint64_t val = ~0ULL; 186 187 if (size != 4) { 188 return val; 189 } 190 191 switch (addr) { 192 case 0x00: 193 val = 0x010000edu; 194 break; 195 case 0x04: 196 val = edu->addr4; 197 break; 198 case 0x08: 199 qemu_mutex_lock(&edu->thr_mutex); 200 val = edu->fact; 201 qemu_mutex_unlock(&edu->thr_mutex); 202 break; 203 case 0x20: 204 val = atomic_read(&edu->status); 205 break; 206 case 0x24: 207 val = edu->irq_status; 208 break; 209 case 0x80: 210 dma_rw(edu, false, &val, &edu->dma.src, false); 211 break; 212 case 0x88: 213 dma_rw(edu, false, &val, &edu->dma.dst, false); 214 break; 215 case 0x90: 216 dma_rw(edu, false, &val, &edu->dma.cnt, false); 217 break; 218 case 0x98: 219 dma_rw(edu, false, &val, &edu->dma.cmd, false); 220 break; 221 } 222 223 return val; 224 } 225 226 static void edu_mmio_write(void *opaque, hwaddr addr, uint64_t val, 227 unsigned size) 228 { 229 EduState *edu = opaque; 230 231 if (addr < 0x80 && size != 4) { 232 return; 233 } 234 235 if (addr >= 0x80 && size != 4 && size != 8) { 236 return; 237 } 238 239 switch (addr) { 240 case 0x04: 241 edu->addr4 = ~val; 242 break; 243 case 0x08: 244 if (atomic_read(&edu->status) & EDU_STATUS_COMPUTING) { 245 break; 246 } 247 /* EDU_STATUS_COMPUTING cannot go 0->1 concurrently, because it is only 248 * set in this function and it is under the iothread mutex. 249 */ 250 qemu_mutex_lock(&edu->thr_mutex); 251 edu->fact = val; 252 atomic_or(&edu->status, EDU_STATUS_COMPUTING); 253 qemu_cond_signal(&edu->thr_cond); 254 qemu_mutex_unlock(&edu->thr_mutex); 255 break; 256 case 0x20: 257 if (val & EDU_STATUS_IRQFACT) { 258 atomic_or(&edu->status, EDU_STATUS_IRQFACT); 259 } else { 260 atomic_and(&edu->status, ~EDU_STATUS_IRQFACT); 261 } 262 break; 263 case 0x60: 264 edu_raise_irq(edu, val); 265 break; 266 case 0x64: 267 edu_lower_irq(edu, val); 268 break; 269 case 0x80: 270 dma_rw(edu, true, &val, &edu->dma.src, false); 271 break; 272 case 0x88: 273 dma_rw(edu, true, &val, &edu->dma.dst, false); 274 break; 275 case 0x90: 276 dma_rw(edu, true, &val, &edu->dma.cnt, false); 277 break; 278 case 0x98: 279 if (!(val & EDU_DMA_RUN)) { 280 break; 281 } 282 dma_rw(edu, true, &val, &edu->dma.cmd, true); 283 break; 284 } 285 } 286 287 static const MemoryRegionOps edu_mmio_ops = { 288 .read = edu_mmio_read, 289 .write = edu_mmio_write, 290 .endianness = DEVICE_NATIVE_ENDIAN, 291 }; 292 293 /* 294 * We purposely use a thread, so that users are forced to wait for the status 295 * register. 296 */ 297 static void *edu_fact_thread(void *opaque) 298 { 299 EduState *edu = opaque; 300 301 while (1) { 302 uint32_t val, ret = 1; 303 304 qemu_mutex_lock(&edu->thr_mutex); 305 while ((atomic_read(&edu->status) & EDU_STATUS_COMPUTING) == 0 && 306 !edu->stopping) { 307 qemu_cond_wait(&edu->thr_cond, &edu->thr_mutex); 308 } 309 310 if (edu->stopping) { 311 qemu_mutex_unlock(&edu->thr_mutex); 312 break; 313 } 314 315 val = edu->fact; 316 qemu_mutex_unlock(&edu->thr_mutex); 317 318 while (val > 0) { 319 ret *= val--; 320 } 321 322 /* 323 * We should sleep for a random period here, so that students are 324 * forced to check the status properly. 325 */ 326 327 qemu_mutex_lock(&edu->thr_mutex); 328 edu->fact = ret; 329 qemu_mutex_unlock(&edu->thr_mutex); 330 atomic_and(&edu->status, ~EDU_STATUS_COMPUTING); 331 332 if (atomic_read(&edu->status) & EDU_STATUS_IRQFACT) { 333 qemu_mutex_lock_iothread(); 334 edu_raise_irq(edu, FACT_IRQ); 335 qemu_mutex_unlock_iothread(); 336 } 337 } 338 339 return NULL; 340 } 341 342 static void pci_edu_realize(PCIDevice *pdev, Error **errp) 343 { 344 EduState *edu = DO_UPCAST(EduState, pdev, pdev); 345 uint8_t *pci_conf = pdev->config; 346 347 pci_config_set_interrupt_pin(pci_conf, 1); 348 349 if (msi_init(pdev, 0, 1, true, false, errp)) { 350 return; 351 } 352 353 timer_init_ms(&edu->dma_timer, QEMU_CLOCK_VIRTUAL, edu_dma_timer, edu); 354 355 qemu_mutex_init(&edu->thr_mutex); 356 qemu_cond_init(&edu->thr_cond); 357 qemu_thread_create(&edu->thread, "edu", edu_fact_thread, 358 edu, QEMU_THREAD_JOINABLE); 359 360 memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu, 361 "edu-mmio", 1 * MiB); 362 pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio); 363 } 364 365 static void pci_edu_uninit(PCIDevice *pdev) 366 { 367 EduState *edu = DO_UPCAST(EduState, pdev, pdev); 368 369 qemu_mutex_lock(&edu->thr_mutex); 370 edu->stopping = true; 371 qemu_mutex_unlock(&edu->thr_mutex); 372 qemu_cond_signal(&edu->thr_cond); 373 qemu_thread_join(&edu->thread); 374 375 qemu_cond_destroy(&edu->thr_cond); 376 qemu_mutex_destroy(&edu->thr_mutex); 377 378 timer_del(&edu->dma_timer); 379 } 380 381 static void edu_obj_uint64(Object *obj, Visitor *v, const char *name, 382 void *opaque, Error **errp) 383 { 384 uint64_t *val = opaque; 385 386 visit_type_uint64(v, name, val, errp); 387 } 388 389 static void edu_instance_init(Object *obj) 390 { 391 EduState *edu = EDU(obj); 392 393 edu->dma_mask = (1UL << 28) - 1; 394 object_property_add(obj, "dma_mask", "uint64", edu_obj_uint64, 395 edu_obj_uint64, NULL, &edu->dma_mask, NULL); 396 } 397 398 static void edu_class_init(ObjectClass *class, void *data) 399 { 400 PCIDeviceClass *k = PCI_DEVICE_CLASS(class); 401 402 k->realize = pci_edu_realize; 403 k->exit = pci_edu_uninit; 404 k->vendor_id = PCI_VENDOR_ID_QEMU; 405 k->device_id = 0x11e8; 406 k->revision = 0x10; 407 k->class_id = PCI_CLASS_OTHERS; 408 } 409 410 static void pci_edu_register_types(void) 411 { 412 static InterfaceInfo interfaces[] = { 413 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 414 { }, 415 }; 416 static const TypeInfo edu_info = { 417 .name = "edu", 418 .parent = TYPE_PCI_DEVICE, 419 .instance_size = sizeof(EduState), 420 .instance_init = edu_instance_init, 421 .class_init = edu_class_init, 422 .interfaces = interfaces, 423 }; 424 425 type_register_static(&edu_info); 426 } 427 type_init(pci_edu_register_types) 428