1 /* 2 * QEMU educational PCI device 3 * 4 * Copyright (c) 2012-2015 Jiri Slaby 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/pci/pci.h" 28 #include "hw/pci/msi.h" 29 #include "qemu/timer.h" 30 #include "qemu/main-loop.h" /* iothread mutex */ 31 #include "qemu/module.h" 32 #include "qapi/visitor.h" 33 34 #define TYPE_PCI_EDU_DEVICE "edu" 35 #define EDU(obj) OBJECT_CHECK(EduState, obj, TYPE_PCI_EDU_DEVICE) 36 37 #define FACT_IRQ 0x00000001 38 #define DMA_IRQ 0x00000100 39 40 #define DMA_START 0x40000 41 #define DMA_SIZE 4096 42 43 typedef struct { 44 PCIDevice pdev; 45 MemoryRegion mmio; 46 47 QemuThread thread; 48 QemuMutex thr_mutex; 49 QemuCond thr_cond; 50 bool stopping; 51 52 uint32_t addr4; 53 uint32_t fact; 54 #define EDU_STATUS_COMPUTING 0x01 55 #define EDU_STATUS_IRQFACT 0x80 56 uint32_t status; 57 58 uint32_t irq_status; 59 60 #define EDU_DMA_RUN 0x1 61 #define EDU_DMA_DIR(cmd) (((cmd) & 0x2) >> 1) 62 # define EDU_DMA_FROM_PCI 0 63 # define EDU_DMA_TO_PCI 1 64 #define EDU_DMA_IRQ 0x4 65 struct dma_state { 66 dma_addr_t src; 67 dma_addr_t dst; 68 dma_addr_t cnt; 69 dma_addr_t cmd; 70 } dma; 71 QEMUTimer dma_timer; 72 char dma_buf[DMA_SIZE]; 73 uint64_t dma_mask; 74 } EduState; 75 76 static bool edu_msi_enabled(EduState *edu) 77 { 78 return msi_enabled(&edu->pdev); 79 } 80 81 static void edu_raise_irq(EduState *edu, uint32_t val) 82 { 83 edu->irq_status |= val; 84 if (edu->irq_status) { 85 if (edu_msi_enabled(edu)) { 86 msi_notify(&edu->pdev, 0); 87 } else { 88 pci_set_irq(&edu->pdev, 1); 89 } 90 } 91 } 92 93 static void edu_lower_irq(EduState *edu, uint32_t val) 94 { 95 edu->irq_status &= ~val; 96 97 if (!edu->irq_status && !edu_msi_enabled(edu)) { 98 pci_set_irq(&edu->pdev, 0); 99 } 100 } 101 102 static bool within(uint64_t addr, uint64_t start, uint64_t end) 103 { 104 return start <= addr && addr < end; 105 } 106 107 static void edu_check_range(uint64_t addr, uint64_t size1, uint64_t start, 108 uint64_t size2) 109 { 110 uint64_t end1 = addr + size1; 111 uint64_t end2 = start + size2; 112 113 if (within(addr, start, end2) && 114 end1 > addr && within(end1, start, end2)) { 115 return; 116 } 117 118 hw_error("EDU: DMA range 0x%016"PRIx64"-0x%016"PRIx64 119 " out of bounds (0x%016"PRIx64"-0x%016"PRIx64")!", 120 addr, end1 - 1, start, end2 - 1); 121 } 122 123 static dma_addr_t edu_clamp_addr(const EduState *edu, dma_addr_t addr) 124 { 125 dma_addr_t res = addr & edu->dma_mask; 126 127 if (addr != res) { 128 printf("EDU: clamping DMA %#.16"PRIx64" to %#.16"PRIx64"!\n", addr, res); 129 } 130 131 return res; 132 } 133 134 static void edu_dma_timer(void *opaque) 135 { 136 EduState *edu = opaque; 137 bool raise_irq = false; 138 139 if (!(edu->dma.cmd & EDU_DMA_RUN)) { 140 return; 141 } 142 143 if (EDU_DMA_DIR(edu->dma.cmd) == EDU_DMA_FROM_PCI) { 144 uint64_t dst = edu->dma.dst; 145 edu_check_range(dst, edu->dma.cnt, DMA_START, DMA_SIZE); 146 dst -= DMA_START; 147 pci_dma_read(&edu->pdev, edu_clamp_addr(edu, edu->dma.src), 148 edu->dma_buf + dst, edu->dma.cnt); 149 } else { 150 uint64_t src = edu->dma.src; 151 edu_check_range(src, edu->dma.cnt, DMA_START, DMA_SIZE); 152 src -= DMA_START; 153 pci_dma_write(&edu->pdev, edu_clamp_addr(edu, edu->dma.dst), 154 edu->dma_buf + src, edu->dma.cnt); 155 } 156 157 edu->dma.cmd &= ~EDU_DMA_RUN; 158 if (edu->dma.cmd & EDU_DMA_IRQ) { 159 raise_irq = true; 160 } 161 162 if (raise_irq) { 163 edu_raise_irq(edu, DMA_IRQ); 164 } 165 } 166 167 static void dma_rw(EduState *edu, bool write, dma_addr_t *val, dma_addr_t *dma, 168 bool timer) 169 { 170 if (write && (edu->dma.cmd & EDU_DMA_RUN)) { 171 return; 172 } 173 174 if (write) { 175 *dma = *val; 176 } else { 177 *val = *dma; 178 } 179 180 if (timer) { 181 timer_mod(&edu->dma_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 100); 182 } 183 } 184 185 static uint64_t edu_mmio_read(void *opaque, hwaddr addr, unsigned size) 186 { 187 EduState *edu = opaque; 188 uint64_t val = ~0ULL; 189 190 if (addr < 0x80 && size != 4) { 191 return val; 192 } 193 194 if (addr >= 0x80 && size != 4 && size != 8) { 195 return val; 196 } 197 198 switch (addr) { 199 case 0x00: 200 val = 0x010000edu; 201 break; 202 case 0x04: 203 val = edu->addr4; 204 break; 205 case 0x08: 206 qemu_mutex_lock(&edu->thr_mutex); 207 val = edu->fact; 208 qemu_mutex_unlock(&edu->thr_mutex); 209 break; 210 case 0x20: 211 val = atomic_read(&edu->status); 212 break; 213 case 0x24: 214 val = edu->irq_status; 215 break; 216 case 0x80: 217 dma_rw(edu, false, &val, &edu->dma.src, false); 218 break; 219 case 0x88: 220 dma_rw(edu, false, &val, &edu->dma.dst, false); 221 break; 222 case 0x90: 223 dma_rw(edu, false, &val, &edu->dma.cnt, false); 224 break; 225 case 0x98: 226 dma_rw(edu, false, &val, &edu->dma.cmd, false); 227 break; 228 } 229 230 return val; 231 } 232 233 static void edu_mmio_write(void *opaque, hwaddr addr, uint64_t val, 234 unsigned size) 235 { 236 EduState *edu = opaque; 237 238 if (addr < 0x80 && size != 4) { 239 return; 240 } 241 242 if (addr >= 0x80 && size != 4 && size != 8) { 243 return; 244 } 245 246 switch (addr) { 247 case 0x04: 248 edu->addr4 = ~val; 249 break; 250 case 0x08: 251 if (atomic_read(&edu->status) & EDU_STATUS_COMPUTING) { 252 break; 253 } 254 /* EDU_STATUS_COMPUTING cannot go 0->1 concurrently, because it is only 255 * set in this function and it is under the iothread mutex. 256 */ 257 qemu_mutex_lock(&edu->thr_mutex); 258 edu->fact = val; 259 atomic_or(&edu->status, EDU_STATUS_COMPUTING); 260 qemu_cond_signal(&edu->thr_cond); 261 qemu_mutex_unlock(&edu->thr_mutex); 262 break; 263 case 0x20: 264 if (val & EDU_STATUS_IRQFACT) { 265 atomic_or(&edu->status, EDU_STATUS_IRQFACT); 266 } else { 267 atomic_and(&edu->status, ~EDU_STATUS_IRQFACT); 268 } 269 break; 270 case 0x60: 271 edu_raise_irq(edu, val); 272 break; 273 case 0x64: 274 edu_lower_irq(edu, val); 275 break; 276 case 0x80: 277 dma_rw(edu, true, &val, &edu->dma.src, false); 278 break; 279 case 0x88: 280 dma_rw(edu, true, &val, &edu->dma.dst, false); 281 break; 282 case 0x90: 283 dma_rw(edu, true, &val, &edu->dma.cnt, false); 284 break; 285 case 0x98: 286 if (!(val & EDU_DMA_RUN)) { 287 break; 288 } 289 dma_rw(edu, true, &val, &edu->dma.cmd, true); 290 break; 291 } 292 } 293 294 static const MemoryRegionOps edu_mmio_ops = { 295 .read = edu_mmio_read, 296 .write = edu_mmio_write, 297 .endianness = DEVICE_NATIVE_ENDIAN, 298 .valid = { 299 .min_access_size = 4, 300 .max_access_size = 8, 301 }, 302 .impl = { 303 .min_access_size = 4, 304 .max_access_size = 8, 305 }, 306 307 }; 308 309 /* 310 * We purposely use a thread, so that users are forced to wait for the status 311 * register. 312 */ 313 static void *edu_fact_thread(void *opaque) 314 { 315 EduState *edu = opaque; 316 317 while (1) { 318 uint32_t val, ret = 1; 319 320 qemu_mutex_lock(&edu->thr_mutex); 321 while ((atomic_read(&edu->status) & EDU_STATUS_COMPUTING) == 0 && 322 !edu->stopping) { 323 qemu_cond_wait(&edu->thr_cond, &edu->thr_mutex); 324 } 325 326 if (edu->stopping) { 327 qemu_mutex_unlock(&edu->thr_mutex); 328 break; 329 } 330 331 val = edu->fact; 332 qemu_mutex_unlock(&edu->thr_mutex); 333 334 while (val > 0) { 335 ret *= val--; 336 } 337 338 /* 339 * We should sleep for a random period here, so that students are 340 * forced to check the status properly. 341 */ 342 343 qemu_mutex_lock(&edu->thr_mutex); 344 edu->fact = ret; 345 qemu_mutex_unlock(&edu->thr_mutex); 346 atomic_and(&edu->status, ~EDU_STATUS_COMPUTING); 347 348 if (atomic_read(&edu->status) & EDU_STATUS_IRQFACT) { 349 qemu_mutex_lock_iothread(); 350 edu_raise_irq(edu, FACT_IRQ); 351 qemu_mutex_unlock_iothread(); 352 } 353 } 354 355 return NULL; 356 } 357 358 static void pci_edu_realize(PCIDevice *pdev, Error **errp) 359 { 360 EduState *edu = EDU(pdev); 361 uint8_t *pci_conf = pdev->config; 362 363 pci_config_set_interrupt_pin(pci_conf, 1); 364 365 if (msi_init(pdev, 0, 1, true, false, errp)) { 366 return; 367 } 368 369 timer_init_ms(&edu->dma_timer, QEMU_CLOCK_VIRTUAL, edu_dma_timer, edu); 370 371 qemu_mutex_init(&edu->thr_mutex); 372 qemu_cond_init(&edu->thr_cond); 373 qemu_thread_create(&edu->thread, "edu", edu_fact_thread, 374 edu, QEMU_THREAD_JOINABLE); 375 376 memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu, 377 "edu-mmio", 1 * MiB); 378 pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio); 379 } 380 381 static void pci_edu_uninit(PCIDevice *pdev) 382 { 383 EduState *edu = EDU(pdev); 384 385 qemu_mutex_lock(&edu->thr_mutex); 386 edu->stopping = true; 387 qemu_mutex_unlock(&edu->thr_mutex); 388 qemu_cond_signal(&edu->thr_cond); 389 qemu_thread_join(&edu->thread); 390 391 qemu_cond_destroy(&edu->thr_cond); 392 qemu_mutex_destroy(&edu->thr_mutex); 393 394 timer_del(&edu->dma_timer); 395 msi_uninit(pdev); 396 } 397 398 static void edu_obj_uint64(Object *obj, Visitor *v, const char *name, 399 void *opaque, Error **errp) 400 { 401 uint64_t *val = opaque; 402 403 visit_type_uint64(v, name, val, errp); 404 } 405 406 static void edu_instance_init(Object *obj) 407 { 408 EduState *edu = EDU(obj); 409 410 edu->dma_mask = (1UL << 28) - 1; 411 object_property_add(obj, "dma_mask", "uint64", edu_obj_uint64, 412 edu_obj_uint64, NULL, &edu->dma_mask, NULL); 413 } 414 415 static void edu_class_init(ObjectClass *class, void *data) 416 { 417 DeviceClass *dc = DEVICE_CLASS(class); 418 PCIDeviceClass *k = PCI_DEVICE_CLASS(class); 419 420 k->realize = pci_edu_realize; 421 k->exit = pci_edu_uninit; 422 k->vendor_id = PCI_VENDOR_ID_QEMU; 423 k->device_id = 0x11e8; 424 k->revision = 0x10; 425 k->class_id = PCI_CLASS_OTHERS; 426 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 427 } 428 429 static void pci_edu_register_types(void) 430 { 431 static InterfaceInfo interfaces[] = { 432 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 433 { }, 434 }; 435 static const TypeInfo edu_info = { 436 .name = TYPE_PCI_EDU_DEVICE, 437 .parent = TYPE_PCI_DEVICE, 438 .instance_size = sizeof(EduState), 439 .instance_init = edu_instance_init, 440 .class_init = edu_class_init, 441 .interfaces = interfaces, 442 }; 443 444 type_register_static(&edu_info); 445 } 446 type_init(pci_edu_register_types) 447