1 /* 2 * QEMU educational PCI device 3 * 4 * Copyright (c) 2012-2015 Jiri Slaby 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/pci/pci.h" 28 #include "hw/pci/msi.h" 29 #include "qemu/timer.h" 30 #include "qemu/main-loop.h" /* iothread mutex */ 31 #include "qapi/visitor.h" 32 33 #define TYPE_PCI_EDU_DEVICE "edu" 34 #define EDU(obj) OBJECT_CHECK(EduState, obj, TYPE_PCI_EDU_DEVICE) 35 36 #define FACT_IRQ 0x00000001 37 #define DMA_IRQ 0x00000100 38 39 #define DMA_START 0x40000 40 #define DMA_SIZE 4096 41 42 typedef struct { 43 PCIDevice pdev; 44 MemoryRegion mmio; 45 46 QemuThread thread; 47 QemuMutex thr_mutex; 48 QemuCond thr_cond; 49 bool stopping; 50 51 uint32_t addr4; 52 uint32_t fact; 53 #define EDU_STATUS_COMPUTING 0x01 54 #define EDU_STATUS_IRQFACT 0x80 55 uint32_t status; 56 57 uint32_t irq_status; 58 59 #define EDU_DMA_RUN 0x1 60 #define EDU_DMA_DIR(cmd) (((cmd) & 0x2) >> 1) 61 # define EDU_DMA_FROM_PCI 0 62 # define EDU_DMA_TO_PCI 1 63 #define EDU_DMA_IRQ 0x4 64 struct dma_state { 65 dma_addr_t src; 66 dma_addr_t dst; 67 dma_addr_t cnt; 68 dma_addr_t cmd; 69 } dma; 70 QEMUTimer dma_timer; 71 char dma_buf[DMA_SIZE]; 72 uint64_t dma_mask; 73 } EduState; 74 75 static bool edu_msi_enabled(EduState *edu) 76 { 77 return msi_enabled(&edu->pdev); 78 } 79 80 static void edu_raise_irq(EduState *edu, uint32_t val) 81 { 82 edu->irq_status |= val; 83 if (edu->irq_status) { 84 if (edu_msi_enabled(edu)) { 85 msi_notify(&edu->pdev, 0); 86 } else { 87 pci_set_irq(&edu->pdev, 1); 88 } 89 } 90 } 91 92 static void edu_lower_irq(EduState *edu, uint32_t val) 93 { 94 edu->irq_status &= ~val; 95 96 if (!edu->irq_status && !edu_msi_enabled(edu)) { 97 pci_set_irq(&edu->pdev, 0); 98 } 99 } 100 101 static bool within(uint64_t addr, uint64_t start, uint64_t end) 102 { 103 return start <= addr && addr < end; 104 } 105 106 static void edu_check_range(uint64_t addr, uint64_t size1, uint64_t start, 107 uint64_t size2) 108 { 109 uint64_t end1 = addr + size1; 110 uint64_t end2 = start + size2; 111 112 if (within(addr, start, end2) && 113 end1 > addr && within(end1, start, end2)) { 114 return; 115 } 116 117 hw_error("EDU: DMA range 0x%016"PRIx64"-0x%016"PRIx64 118 " out of bounds (0x%016"PRIx64"-0x%016"PRIx64")!", 119 addr, end1 - 1, start, end2 - 1); 120 } 121 122 static dma_addr_t edu_clamp_addr(const EduState *edu, dma_addr_t addr) 123 { 124 dma_addr_t res = addr & edu->dma_mask; 125 126 if (addr != res) { 127 printf("EDU: clamping DMA %#.16"PRIx64" to %#.16"PRIx64"!\n", addr, res); 128 } 129 130 return res; 131 } 132 133 static void edu_dma_timer(void *opaque) 134 { 135 EduState *edu = opaque; 136 bool raise_irq = false; 137 138 if (!(edu->dma.cmd & EDU_DMA_RUN)) { 139 return; 140 } 141 142 if (EDU_DMA_DIR(edu->dma.cmd) == EDU_DMA_FROM_PCI) { 143 uint64_t dst = edu->dma.dst; 144 edu_check_range(dst, edu->dma.cnt, DMA_START, DMA_SIZE); 145 dst -= DMA_START; 146 pci_dma_read(&edu->pdev, edu_clamp_addr(edu, edu->dma.src), 147 edu->dma_buf + dst, edu->dma.cnt); 148 } else { 149 uint64_t src = edu->dma.src; 150 edu_check_range(src, edu->dma.cnt, DMA_START, DMA_SIZE); 151 src -= DMA_START; 152 pci_dma_write(&edu->pdev, edu_clamp_addr(edu, edu->dma.dst), 153 edu->dma_buf + src, edu->dma.cnt); 154 } 155 156 edu->dma.cmd &= ~EDU_DMA_RUN; 157 if (edu->dma.cmd & EDU_DMA_IRQ) { 158 raise_irq = true; 159 } 160 161 if (raise_irq) { 162 edu_raise_irq(edu, DMA_IRQ); 163 } 164 } 165 166 static void dma_rw(EduState *edu, bool write, dma_addr_t *val, dma_addr_t *dma, 167 bool timer) 168 { 169 if (write && (edu->dma.cmd & EDU_DMA_RUN)) { 170 return; 171 } 172 173 if (write) { 174 *dma = *val; 175 } else { 176 *val = *dma; 177 } 178 179 if (timer) { 180 timer_mod(&edu->dma_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 100); 181 } 182 } 183 184 static uint64_t edu_mmio_read(void *opaque, hwaddr addr, unsigned size) 185 { 186 EduState *edu = opaque; 187 uint64_t val = ~0ULL; 188 189 if (addr < 0x80 && size != 4) { 190 return val; 191 } 192 193 if (addr >= 0x80 && size != 4 && size != 8) { 194 return val; 195 } 196 197 switch (addr) { 198 case 0x00: 199 val = 0x010000edu; 200 break; 201 case 0x04: 202 val = edu->addr4; 203 break; 204 case 0x08: 205 qemu_mutex_lock(&edu->thr_mutex); 206 val = edu->fact; 207 qemu_mutex_unlock(&edu->thr_mutex); 208 break; 209 case 0x20: 210 val = atomic_read(&edu->status); 211 break; 212 case 0x24: 213 val = edu->irq_status; 214 break; 215 case 0x80: 216 dma_rw(edu, false, &val, &edu->dma.src, false); 217 break; 218 case 0x88: 219 dma_rw(edu, false, &val, &edu->dma.dst, false); 220 break; 221 case 0x90: 222 dma_rw(edu, false, &val, &edu->dma.cnt, false); 223 break; 224 case 0x98: 225 dma_rw(edu, false, &val, &edu->dma.cmd, false); 226 break; 227 } 228 229 return val; 230 } 231 232 static void edu_mmio_write(void *opaque, hwaddr addr, uint64_t val, 233 unsigned size) 234 { 235 EduState *edu = opaque; 236 237 if (addr < 0x80 && size != 4) { 238 return; 239 } 240 241 if (addr >= 0x80 && size != 4 && size != 8) { 242 return; 243 } 244 245 switch (addr) { 246 case 0x04: 247 edu->addr4 = ~val; 248 break; 249 case 0x08: 250 if (atomic_read(&edu->status) & EDU_STATUS_COMPUTING) { 251 break; 252 } 253 /* EDU_STATUS_COMPUTING cannot go 0->1 concurrently, because it is only 254 * set in this function and it is under the iothread mutex. 255 */ 256 qemu_mutex_lock(&edu->thr_mutex); 257 edu->fact = val; 258 atomic_or(&edu->status, EDU_STATUS_COMPUTING); 259 qemu_cond_signal(&edu->thr_cond); 260 qemu_mutex_unlock(&edu->thr_mutex); 261 break; 262 case 0x20: 263 if (val & EDU_STATUS_IRQFACT) { 264 atomic_or(&edu->status, EDU_STATUS_IRQFACT); 265 } else { 266 atomic_and(&edu->status, ~EDU_STATUS_IRQFACT); 267 } 268 break; 269 case 0x60: 270 edu_raise_irq(edu, val); 271 break; 272 case 0x64: 273 edu_lower_irq(edu, val); 274 break; 275 case 0x80: 276 dma_rw(edu, true, &val, &edu->dma.src, false); 277 break; 278 case 0x88: 279 dma_rw(edu, true, &val, &edu->dma.dst, false); 280 break; 281 case 0x90: 282 dma_rw(edu, true, &val, &edu->dma.cnt, false); 283 break; 284 case 0x98: 285 if (!(val & EDU_DMA_RUN)) { 286 break; 287 } 288 dma_rw(edu, true, &val, &edu->dma.cmd, true); 289 break; 290 } 291 } 292 293 static const MemoryRegionOps edu_mmio_ops = { 294 .read = edu_mmio_read, 295 .write = edu_mmio_write, 296 .endianness = DEVICE_NATIVE_ENDIAN, 297 .valid = { 298 .min_access_size = 4, 299 .max_access_size = 8, 300 }, 301 .impl = { 302 .min_access_size = 4, 303 .max_access_size = 8, 304 }, 305 306 }; 307 308 /* 309 * We purposely use a thread, so that users are forced to wait for the status 310 * register. 311 */ 312 static void *edu_fact_thread(void *opaque) 313 { 314 EduState *edu = opaque; 315 316 while (1) { 317 uint32_t val, ret = 1; 318 319 qemu_mutex_lock(&edu->thr_mutex); 320 while ((atomic_read(&edu->status) & EDU_STATUS_COMPUTING) == 0 && 321 !edu->stopping) { 322 qemu_cond_wait(&edu->thr_cond, &edu->thr_mutex); 323 } 324 325 if (edu->stopping) { 326 qemu_mutex_unlock(&edu->thr_mutex); 327 break; 328 } 329 330 val = edu->fact; 331 qemu_mutex_unlock(&edu->thr_mutex); 332 333 while (val > 0) { 334 ret *= val--; 335 } 336 337 /* 338 * We should sleep for a random period here, so that students are 339 * forced to check the status properly. 340 */ 341 342 qemu_mutex_lock(&edu->thr_mutex); 343 edu->fact = ret; 344 qemu_mutex_unlock(&edu->thr_mutex); 345 atomic_and(&edu->status, ~EDU_STATUS_COMPUTING); 346 347 if (atomic_read(&edu->status) & EDU_STATUS_IRQFACT) { 348 qemu_mutex_lock_iothread(); 349 edu_raise_irq(edu, FACT_IRQ); 350 qemu_mutex_unlock_iothread(); 351 } 352 } 353 354 return NULL; 355 } 356 357 static void pci_edu_realize(PCIDevice *pdev, Error **errp) 358 { 359 EduState *edu = EDU(pdev); 360 uint8_t *pci_conf = pdev->config; 361 362 pci_config_set_interrupt_pin(pci_conf, 1); 363 364 if (msi_init(pdev, 0, 1, true, false, errp)) { 365 return; 366 } 367 368 timer_init_ms(&edu->dma_timer, QEMU_CLOCK_VIRTUAL, edu_dma_timer, edu); 369 370 qemu_mutex_init(&edu->thr_mutex); 371 qemu_cond_init(&edu->thr_cond); 372 qemu_thread_create(&edu->thread, "edu", edu_fact_thread, 373 edu, QEMU_THREAD_JOINABLE); 374 375 memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu, 376 "edu-mmio", 1 * MiB); 377 pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio); 378 } 379 380 static void pci_edu_uninit(PCIDevice *pdev) 381 { 382 EduState *edu = EDU(pdev); 383 384 qemu_mutex_lock(&edu->thr_mutex); 385 edu->stopping = true; 386 qemu_mutex_unlock(&edu->thr_mutex); 387 qemu_cond_signal(&edu->thr_cond); 388 qemu_thread_join(&edu->thread); 389 390 qemu_cond_destroy(&edu->thr_cond); 391 qemu_mutex_destroy(&edu->thr_mutex); 392 393 timer_del(&edu->dma_timer); 394 msi_uninit(pdev); 395 } 396 397 static void edu_obj_uint64(Object *obj, Visitor *v, const char *name, 398 void *opaque, Error **errp) 399 { 400 uint64_t *val = opaque; 401 402 visit_type_uint64(v, name, val, errp); 403 } 404 405 static void edu_instance_init(Object *obj) 406 { 407 EduState *edu = EDU(obj); 408 409 edu->dma_mask = (1UL << 28) - 1; 410 object_property_add(obj, "dma_mask", "uint64", edu_obj_uint64, 411 edu_obj_uint64, NULL, &edu->dma_mask, NULL); 412 } 413 414 static void edu_class_init(ObjectClass *class, void *data) 415 { 416 DeviceClass *dc = DEVICE_CLASS(class); 417 PCIDeviceClass *k = PCI_DEVICE_CLASS(class); 418 419 k->realize = pci_edu_realize; 420 k->exit = pci_edu_uninit; 421 k->vendor_id = PCI_VENDOR_ID_QEMU; 422 k->device_id = 0x11e8; 423 k->revision = 0x10; 424 k->class_id = PCI_CLASS_OTHERS; 425 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 426 } 427 428 static void pci_edu_register_types(void) 429 { 430 static InterfaceInfo interfaces[] = { 431 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 432 { }, 433 }; 434 static const TypeInfo edu_info = { 435 .name = TYPE_PCI_EDU_DEVICE, 436 .parent = TYPE_PCI_DEVICE, 437 .instance_size = sizeof(EduState), 438 .instance_init = edu_instance_init, 439 .class_init = edu_class_init, 440 .interfaces = interfaces, 441 }; 442 443 type_register_static(&edu_info); 444 } 445 type_init(pci_edu_register_types) 446